AD8045

3 nV/√Hz Ultralow Distortion, High Speed Op Amp AD8045 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES Ultralow distortion SFDR −101 dBc @ 5 MHz −90 dBc @ 20 MHz −63 dBc @ 70 MHz Third-order intercept 43 dBm @ 10 MHz Low noise 3 nV/√Hz 3 pA/√Hz High speed 1 GHz, −3 dB bandwidth (G = +1) 1350 V/µs slew rate 7.5 ns settling time to 0.1% Standard and low distortion pinout Supply current: 15 mA Offset voltage: 1.0 mV max Wide supply voltage range: 3.3 V to 12 V APPLICATIONS Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers CONNECTION DIAGRAMS 1 2 5 6 7 8NC FEEDBACK –IN +IN +VS OUTPUT NC –VS 3 4 04 81 4- 0- 00 1 Figure 1. 8-Lead AD8045 LFCSP (CP-8) 04 81 4- 0- 00 1 1FEEDBACK 2–IN 3+IN –VS 4 8 +VS NC 7 OUTPUT NC 6 5 Figure 2. 8-Lead AD8045 SOIC/EP (RD-8) GENERAL DESCRIPTION The AD8045 is a unity gain stable voltage feedback amplifier with ultralow distortion, low noise, and high slew rate. With a spurious-free dynamic range of −90 dBc @ 20 MHz, the AD8045 is an ideal solution in a variety of applications, including ultrasound, ATE, active filters, and ADC drivers. ADI’s proprietary next generation XFCB process and innovative architecture enables such high performance amplifiers. The AD8045 features a low distortion pinout for the LFCSP, which improves second harmonic distortion and simplifies the layout of the circuit board. The AD8045 has 1 GHz bandwidth, 1350 V/µs slew rate, and settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V to 12 V) and low offset voltage (200 µV), the AD8045 is an ideal candidate for systems that require high dynamic range, preci- sion, and high speed. The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP and the standard 8-lead SOIC. Both packages feature an exposed paddle that provides a low thermal resistance path to the PCB. This enables more efficient heat transfer, and increases reliability. The AD8045 works over the extended industrial temperature range (−40°C to +125°C). 04 81 4- 0- 07 9 FREQUENCY (MHz) 1000.1 1 10 H A R M O N IC D IS TO R TI O N (d B c) –20 –30 –40 –50 –60 –70 –80 –90 –100 –120 –110 HD3 LFCSP HD2 LFCSP G = +1 VS = ±5V VOUT = 2V p-p RL = 1kΩ RS = 100Ω Figure 3. Harmonic Distortion vs. Frequency for Various Packages AD8045 Rev. A | Page 2 of 24 TABLE OF CONTENTS Specifications with ±5 V Supply ..................................................... 3 Specifications with +5 V Supply ..................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Configurations................................................................... 16 Wideband Operation ................................................................. 16 Theory of Operation ...................................................................... 17 Frequency Response................................................................... 17 DC Errors .................................................................................... 17 Output Noise............................................................................... 18 Applications..................................................................................... 19 Low Distortion Pinout............................................................... 19 High Speed ADC Driver ........................................................... 19 90 MHz Active Low-Pass Filter (LPF) ..................................... 20 Printed Circuit Board Layout ....................................................... 22 Signal Routing............................................................................. 22 Power Supply Bypassing ............................................................ 22 Grounding ................................................................................... 22 Exposed Paddle........................................................................... 23 Driving Capacitive Loads.......................................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 REVISION HISTORY 9/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Features......................................................................... 1 Changes to Specifications ............................................................... 4 Changes to Figure 58.....................................................................15 Changes to Figure 63.....................................................................17 Changes to Frequency Response Section ...................................17 Changes to Figure 64.....................................................................17 Changes to DC Errors Section.....................................................17 Changes to Figure 65.....................................................................17 Changes to Figure 66.....................................................................18 Changes to Output Noise Section ...............................................18 Changes to Ordering Guide .........................................................24 7/04—Revision 0: Initial Version AD8045 Rev. A | Page 3 of 24 SPECIFICATIONS WITH ±5 V SUPPLY TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to ground, unless noted otherwise. Exposed paddle must be floating or connected to −VS. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 1000 MHz G = +1, VOUT = 2 V p-p 300 350 G = +2, VOUT = 0.2 V p-p 320 400 MHz Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p, RL = 150 Ω 55 MHz Slew Rate G = +1, VOUT = 4 V step 1000 1350 V/µs Settling Time to 0.1% G = +2, VOUT = 2 V step 7.5 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 fC = 5 MHz, VOUT = 2 V p-p LFCSP −102/−101 dBc SOIC −106/−101 dBc fC = 20 MHz, VOUT = 2 V p-p LFCSP −98/−90 dBc SOIC −97/−90 dBc fC = 70 MHz, VOUT = 2 V p-p LFCSP −71/−71 dBc SOIC −60/−71 dBc Input Voltage Noise f = 100 kHz 3 nV/√Hz Input Current Noise f = 100 kHz 3 pA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degrees DC PERFORMANCE Input Offset Voltage 0.2 1.0 mV Input Offset Voltage Drift See Figure 54 8 µV/°C Input Bias Current 2 6.3 µA Input Bias Current Drift 8 nA/°C Input Bias Offset Current 0.2 1.3 µA Open-Loop Gain VOUT = −3 V to +3 V 62 64 dB INPUT CHARACTERISTICS Input Resistance Common-mode/differential 3.6/1.0 MΩ Input Capacitance Common-mode 1.3 pF Input Common-Mode Voltage Range ±3.8 V Common-Mode Rejection VCM = ±1 V −83 −91 dB OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VIN = ±3 V, G = +2 8 ns Output Voltage Swing RL = 1 kΩ −3.8 to +3.8 −3.9 to +3.9 V RL = 100 Ω −3.4 to +3.5 −3.6 to +3.6 V Output Current 70 mA Short-Circuit Current Sinking/sourcing 90/170 mA Capacitive Load Drive 30% overshoot, G = +2 18 pF POWER SUPPLY Operating Range ±1.65 ±5 ±6 V Quiescent Current 16 19 mA Positive Power Supply Rejection +VS = +5 V to +6 V, −VS = −5 V −61 −68 dB Negative Power Supply Rejection +VS = +5 V, −VS = −5 V to −6 V −66 −73 dB AD8045 Rev. A | Page 4 of 24 SPECIFICATIONS WITH +5 V SUPPLY TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to −VS. Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 900 MHz G = +1, VOUT = 2 V p-p 160 200 MHz G = +2, VOUT = 0.2 V p-p 320 395 MHz Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p, RL = 150 Ω 60 MHz Slew Rate G = +1, VOUT = 2 V step 480 1060 V/µs Settling Time to 0.1% G = +2, VOUT = 2 V step 10 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 fC = 5 MHz, VOUT = 2 V p-p LFCSP −89/−83 dBc SOIC −92/−83 dBc fC = 20 MHz, VOUT = 2 V p-p LFCSP −81/−70 dBc SOIC −83/−70 dBc fC = 70 MHz, VOUT = 2 V p-p LFCSP −57/−46 dBc SOIC −57/−46 dBc Input Voltage Noise f = 100 kHz 3 nV/√Hz Input Current Noise f = 100 kHz 3 pA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degrees DC PERFORMANCE Input Offset Voltage 0.5 1.4 mV Input Offset Voltage Drift See Figure 54 7 µV/°C Input Bias Current 2 6.6 µA Input Bias Current Drift 7 nA/°C Input Bias Offset Current 0.2 1.3 µA Open-Loop Gain VOUT = 2 V to 3 V 61 63 dB INPUT CHARACTERISTICS Input Resistance Common-mode/differential 3/0.9 MΩ Input Capacitance Common-mode 1.3 pF Input Common-Mode Voltage Range 1.2 to 3.8 V Common-Mode Rejection VCM = 2 V to 3 V −78 −94 dB OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VIN = −0.5 V to +3 V, G = +2 10 ns Output Voltage Swing RL = 1 kΩ 2.2 to 3.7 1.1 to 4.0 V RL = 100 Ω 2.5 to 3.5 1.2 to 3.8 V Output Current 55 mA Short-Circuit Current Sinking/sourcing 70/140 mA Capacitive Load Drive 30% overshoot, G = +2 15 pF POWER SUPPLY Operating Range 3.3 5 12 V Quiescent Current 15 18 mA Positive Power Supply Rejection +VS = +5 V to +6 V, −VS = 0 V −65 −67 dB Negative Power Supply Rejection +VS = +5 V, −VS = 0 V to −1 V −70 −73 dB AD8045 Rev. A | Page 5 of 24 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 12.6 V Power Dissipation See Figure 4 Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V Differential Input Voltage ±VS Exposed Paddle Voltage −VS Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +125°C Lead Temperature Range (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type θJA θJC Unit SOIC 80 30 °C/W LFCSP 93 35 °C/W Maximum Power Dissipation The maximum safe power dissipation for the AD8045 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric perform- ance of the AD8045. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the qui- escent power dissipation and the power dissipated in the die due to the AD8045 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power + (Total Drive Power – Load Power) ( ) L 2 OUT L OUTS SSD R V – R V 2 V IVP ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ ×+×= RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. ( ) ( ) L S SSD R /V IVP 24+×= In single-supply operation with RL referenced to −VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduce θJA. Figure 4 shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC standard 4-layer board. θJA values are approximations. 04 81 4- 0- 08 0 AMBIENT TEMPERATURE (°C) 120–40 –20 0 20 40 60 80 100 M A XI M U M P O W ER D IS SI PA TI O N (W at ts ) 0.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 LFCSP SOIC Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec- trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation and loss of functionality. AD8045 Rev. A | Page 6 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 04 81 4- 0- 00 3 FEEDBACK8 –IN7 +IN6 –VS5 NC 1 +VS 2 OUTPUT 3 NC 4 NC = NO CONNECT AD8045 BOTTOM VIEW (Not to Scale) Figure 5. SOIC Pin Configuration 04 81 4- 0- 00 4 BOTTOM VIEW (Not to Scale) 8 7 6 5 4 3 2 1 NC FEEDBACK –IN +IN +VS OUTPUT NC –VS NC = NO CONNECT Figure 6 . 8-Lead LFCSP Pin Configuration Note: The exposed paddle must be connected to −VS or it must be electrically isolated (floating). Table 5. 8-Lead SOIC Pin Function Descriptions Pin No. Mnemonic Description 1 FEEDBACK Feedback Pin 2 −IN Inverting Input 3 +IN Noninverting Input 4 −VS Negative Supply 5 NC NC 6 OUTPUT Output 7 +VS Positive Supply 8 NC NC 9 Exposed Paddle Must Be Connected to −VS or Electrically Isolated Table 6. 8-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 NC No Connect 2 FEEDBACK Feedback Pin 3 −IN Inverting Input 4 +IN Noninverting Input 5 −VS Negative Supply 6 NC No Connect 7 OUTPUT Output 8 +VS Positive Supply 9 Exposed Paddle Must Be Connected to −VS or Electrically Isolated AD8045 Rev. A | Page 7 of 24 TYPICAL PERFORMANCE CHARACTERISTICS 04 81 4- 0- 04 9 FREQUENCY (MHz) 10001 10 100 N O R M A LI ZE D C LO SE D -L O O P G A IN (d B ) 1 0 –1 –2 –3 –4 –5 –6 –7 G = +2 G = –1G = +10 VS = ±5V RL = 1kΩ Figure 7. Small Signal Frequency Response for Various Gains 04 81 4- 0- 05 0 FREQUENCY (MHz) 100010 100 C LO SE D -L O O P G A IN (d B ) 4 3 2 1 0 –1 –3 –2 –4 –5 –6 G = +1 VS = ±5V RS = 100Ω RL = 500Ω RL = 100Ω RL = 1kΩ Figure 8. Small Signal Frequency Response for Various Loads 04 81 4- 0- 05 1 FREQUENCY (MHz) 100010 100 C LO SE D -L O O P G A IN (d B ) 5 4 3 2 0 1 –2 –1 –3 –4 –5 VS = ±5V VS = ±2.5V G = +1 RL = 1kΩ RS = 100Ω Figure 9. Small Signal Frequency Response for Various Supplies 04 81 4- 0- 04 8 FREQUENCY (MHz) 100010 100 C LO SE D -L O O P G A IN (d B ) 12 10 11 8 9 6 7 4 5 2 3 0 1 18pF 5pF 10pF G = +2 VS = ±5V RL = 1kΩ RF = 499Ω 0pF Figure 10. Small Signal Frequency Response for Various Capacitive Loads 04 81 4- 0- 05 2 FREQUENCY (MHz) 100010 100 C LO SE D -L O O P G A IN (d B ) 4 2 0 –1 –3 3 1 –2 –4 –5 –6 –40°C +25°C +125°C G = +1 VS = ±5V RL = 1kΩ Figure 11. Small Signal Frequency Response for Various Temperatures 04 81 4- 0- 03 9 FREQUENCY (MHz) 1 10 100 C LO SE D -L O O P G A IN (d B ) 6.3 6.2 6.1 6.0 5.9 5.8 5.7 VOUT = 2V p-p VOUT = 200mV p-p G = +2 VS = ±5V RF = 499Ω RL = 150Ω Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages AD8045 Rev. A | Page 8 of 24 04 81 4- 0- 04 3 FREQUENCY (MHz) 100010 100 C LO SE D -L O O P G A IN (d B ) 2 0 1 –2 –1 –4 –3 –6 –5 –8 –7 –10 –9 G = +1 RL = 1kΩ RS = 100Ω VOUT = 2V p-p VS = ±2.5V VS = ±5V Figure 13. Large Signal Frequency Response for Various Supplies 04 81 4- 0- 04 2 FREQUENCY (MHz) 100010 100 C LO SE D -L O O P G A IN (d B ) 2 0 1 –2 –1 –4 –3 –6 –5 –8 –9 –7 –10 G = +1 VS = ±5V RS = 100Ω VOUT = 2V p-p RL = 1kΩ RL = 100Ω Figure 14. Large Signal Frequency Response for Various Loads 04 81 4- 0- 04 1 FREQUENCY (MHz) 10001 10 100 N O R M A LI ZE D C LO SE D -L O O P G A IN (d B ) 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 VS = ±5V RF = 499Ω RL = 1kΩ VOUT = 2V p-p G = +10 G = –1 G = +2 Figure 15. Large Signal Frequency Response for Various Gains 04 81 4- 0- 06 4 FREQUENCY (MHz) 10000.01 0.1 1 10 100 O PE N -L O O P PH A SE (D eg re es ) –360 0 –90 –135 –180 –45 –225 –270 –315 O PE N -L O O P G A IN (d B ) 70 50 60 40 20 30 10 0 –10 VS = ±5V RL = 1kΩ Figure 16. Open-Loop Gain and Phase vs. Frequency 04 81 4- 0- 03 0 FREQUENCY (MHz) 1000.1 1 10 H A R M O N IC D IS TO R TI O N (d B c) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 HD3 SOIC AND LFCSP HD2 LFCSP HD2 SOIC G = +1 VS = ±5V VOUT = 2V p-p RL = 1kΩ RS = 100Ω Figure 17. Harmonic Distortion vs. Frequency for Various Packages 04 81 4- 0- 02 8 FREQUENCY (MHz) 0.1 1 10 100 H A R M O N IC D IS TO R TI O N (d B c) –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 G = +1 VS = ±5V VOUT = 4V p-p RL = 1kΩ HD3 LFCSP AND SOIC HD2 LFCSP HD2 SOIC Figure 18. Harmonic Distortion vs. Frequency for Various Packages AD8045 Rev. A | Page 9 of 24 04 81 4- 0- 03 2 FREQUENCY (MHz) 0.1 1 10 100 H A R M O N IC D IS TO R TI O N (d B c) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 G = +1 VS = ±5V VOUT = 2V p-p RL = 100Ω RS = 100Ω HD2 SOIC HD2 LFCSP HD3 SOIC AND LFCSP Figure 19. Harmonic Distortion vs. Frequency for Various Packages 04 81 4- 0- 03 6 FREQUENCY (MHz) 0.1 1 10 100 H A R M O N IC D IS TO R TI O N (d B c) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 G = –1 VS = ±5V VOUT = 2V p-p RL = 1kΩ SOIC AND LFCSP HD2 HD3 Figure 20. Harmonic Distortion vs. Frequency for Various Packages 04 81 4- 0- 03 7 FREQUENCY (MHz) 0.1 1 10 100 H A R M O N IC D IS TO R TI O N (d B c) –30 –50 –40 –60 –80 –70 –100 –90 –110 G = –1 VS = ±5V RL = 150Ω VOUT = 2V p-p HD3 SOIC AND LFCSP HD2 SOIC HD2 LFCSP Figure 21. Harmonic Distortion vs. Frequency for Various Packages 04 81 4- 0-