74ALVC16245-D

© Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 1 1 Publication Order Number: 74ALVC16245/D 74ALVC16245 Low−Voltage 1.8/2.5/3.3V 16−Bit Transceiver With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74ALVC16245 is an advanced performance, non−inverting 16−bit transceiver. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The ALVC16245 is designed with byte control. It can be operated as two separate octals, or with the controls tied together, as a 16−bit wide function. The Transmit/Receive (T/Rn) inputs determine the direction of data flow through the bi−directional transceiver. Transmit (active−HIGH) enables data from A ports to B ports; Receive (active−LOW) enables data from B to A ports. The Output Enable inputs (OEn), when HIGH, disable both A and B ports by placing them in a HIGH Z condition. • Designed for Low Voltage Operation: VCC = 1.65−3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 3.0 ns max for 3.0 to 3.6 V 3.7 ns max for 2.3 to 2.7 V 6.0 ns max for 1.65 to 1.95 V • Static Drive: �24 mA Drive at 3.0 V �12 mA Drive at 2.3 V �4 mA Drive at 1.65 V • Supports Live Insertion and Withdrawal • IOFF Specification Guarantees High Impedance When VCC = 0 V† • Near Zero Static Supply Current in All Three Logic States (40 �A) Substantially Reduces System Power Requirements • Latchup Performance Exceeds �250 mA @ 125°C • ESD Performance: Human Body Model >2000 V; Machine Model >200 V • Second Source to Industry Standard 74ALVC16245 †To ensure the outputs activate in the 3−state condition, the output enable pins should be connected to VCC through a pull−up resistor. The value of the resistor is determined by the current sinking capability of the output connected to the OE pin. MARKING DIAGRAM A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week TSSOP−48 DT SUFFIX CASE 1201 1 48 74ALVC16245DT AWLYYWW 1 48 Device Package Shipping ORDERING INFORMATION 74ALVC16245DTR TSSOP 2500/Tape & Reel http://onsemi.com 74ALVC16245 http://onsemi.com 2 Figure 1. 48−Lead Pinout (Top View) Figure 2. Logic Diagram T/R1 A0:7 B0:7 One of Eight 481 OE1T/R1 472 A0B0 463 A1B1 454 GNDGND 445 A2B2 436 A3B3 427 VCCVCC 418 A4B4 409 A5B5 3910 GNDGND 3811 A6B6 3712 A7B7 3613 A8B8 3514 A9B9 3415 GNDGND 3316 A10B10 3217 A11B11 3118 VCCVCC 3019 A12B12 2920 A13B13 2821 GNDGND 2722 A14B14 2623 A15B15 2524 OE2T/R2 OE1 T/R2 A8:15 B8:15 OE2 1 48 24 25 1 48 25 24 A0 47 A1 46 A2 44 A3 43 B0 2 EN1T/R1 OE1 OE2 T/R2 B1 3 B2 5 B3 6 EN2 EN3 EN4 A4 41 A5 40 A6 38 A7 37 B4 8 B5 9 B6 11 B7 12 A8 36 A9 35 A10 33 A11 32 B8 13 B9 14 B10 16 B11 17 A12 30 A13 29 A14 27 A15 26 B12 19 B13 20 B14 22 B15 23 1 ∇ 2 ∇ 3 ∇ 4 ∇ 1 1 1 1 PIN NAMES Function Output Enable Inputs Transmit/Receive Inputs Side A Inputs or 3−State Outputs Side B Inputs or 3−State Outputs Pins OEn T/Rn A0−A15 B0−B15 Figure 3. IEC Logic Diagram Inputs Outputs Inputs Outputs OE1 T/R1 OE2 T/R2 L L Bus B0:7 Data to Bus A0:7 L L Bus B8:15 Data to Bus A8:15 L H Bus A0:7 Data to Bus B0:7 L H Bus A8:15 Data to Bus B8:15 H X High Z State on A0:7, B0:7 H X High Z State on A8:15, B8:15 H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable 74ALVC16245 http://onsemi.com 3 MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit VCC DC Supply Voltage �0.5 to �4.6 V VI DC Input Voltage �0.5 to �4.6 V VO DC Output Voltage �0.5 to �4.6 V IIK DC Input Diode Current VI < GND �50 mA IOK DC Output Diode Current VO < GND �50 mA IO DC Output Sink/Source Current �50 mA ICC DC Supply Current per Supply Pin �100 mA IGND DC Ground Current per Ground Pin �100 mA TSTG Storage Temperature Range �65 to �150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias �150 °C �JA Thermal Resistance (Note 2) 90 °C/W MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in VESD ESD Withstand Voltage Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) �2000 �200 N/A V ILATCH−UP Latch−Up Performance Above VCC and Below GND at 125°C (Note 6) �250 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit VCC Supply Voltage Operating Data Retention Only 1.65 1.2 3.3 3.3 3.6 3.6 V VI Input Voltage (Note 7) −0.5 3.6 V VO Output Voltage (Active State) (3−State) 0 0 VCC 3.6 V TA Operating Free−Air Temperature −40 +85 °C �t/�V Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V,VCC = 2.5 V �0.2 V VCC = 3.0 V �0.3 V 0 0 20 10 ns/V 7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. 74ALVC16245 http://onsemi.com 4 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol Characteristic Condition Min Max Unit VIH HIGH Level Input Voltage (Note 8) 1.65 V ≤ VCC < 2.3 V 0.65 x VCC V 2.3 V ≤ VCC ≤ 2.7 V 1.7 2.7 V < VCC ≤ 3.6 V 2.0 VIL LOW Level Input Voltage (Note 8) 1.65 V ≤ VCC < 2.3 V 0.35 x VCC V 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V < VCC ≤ 3.6 V 0.8 VOH HIGH Level Output Voltage 1.65 V ≤ VCC ≤ 3.6 V; IOH = −100 �A VCC − 0.2 V VCC = 1.65 V; IOH = −4 mA 1.2 VCC = 2.3 V; IOH = −6 mA 2.0 VCC = 2.3 V; IOH = −12 mA 1.7 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −12 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.0 VOL LOW Level Output Voltage 1.65 V ≤ VCC ≤ 3.6 V; IOL = 100 �A 0.2 V VCC = 1.65 V; IOL = 4 mA 0.45 VCC = 2.3 V; IOL = 6 mA 0.4 VCC = 2.3 V; IOL = 12 mA 0.7 VCC = 2.7 V; IOL = 12 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 II Input Leakage Current 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 3.6 V ±5.0 �A IOZ 3−State Output Current 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 3.6 V; VI = VIH or VIL ±10 �A IOFF Power−Off Leakage Current VCC = 0 V; VI or VO = 3.6 V 10 �A ICC Quiescent Supply Current (Note 9) 1.65 V ≤ VCC ≤ 3.6 V; VI = GND or VCC 40 �A 1.65 V ≤ VCC ≤ 3.6 V; 3.6 V ≤ VI, VO ≤ 3.6 V ±40 �A �ICC Increase in ICC per Input 2.7 V < VCC ≤ 3.6 V; VIH = VCC − 0.6 V 750 �A 8. These values of VI are used to test DC electrical characteristics only. 9. Outputs disabled or 3−state only. AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 �) Limits TA = −40°C to +85°C VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 to1.95 V Symbol Parameter Waveform Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay Input to Output 1 1.0 1.0 3.0 3.0 1.0 1.0 3.7 3.7 1.0 1.0 6.0 6.0 ns tPZH tPZL Output Enable Time to High and Low Level 2 1.0 1.0 4.4 4.4 1.0 1.0 5.7 5.7 1.0 1.0 9.3 9.3 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 1.0 1.0 4.1 4.1 1.0 1.0 5.2 5.2 1.0 1.0 7.6 7.6 ns tOSHL tOSLH Output−to−Output Skew (Note 11) 0.5 0.5 0.5 0.5 0.75 0.75 ns 10.For CL = 50 pF, add approximately 300 ps to the AC maximum specification. 11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. 74ALVC16245 http://onsemi.com 5 CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit CIN Input Capacitance Note 12 6 pF COUT Output Capacitance Note 12 7 pF CPD Power Dissipation Capacitance Note 12, 10 MHz 20 pF 12.VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC. WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns VIH 0V VOH VOL An, Bn Bn, An tPHLtPLH WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns VIH 0V ≈ 0V OEn, T/Rn An, Bn tPZH ≈ VCC tPHZ tPZL tPLZ An, Bn Vm Vm VmVm Vm Vm Figure 4. AC Waveforms Vm VOH Vy Vx VOL Vm Symbol VCC 3.3 V ±0.3 V 2.5 V ±0.2 V 1.8 V ±0.15 V VIH 2.7 V VCC VCC Vm 1.5 V VCC/2 VCC/2 Vx VOL + 0.3 V VOL + 0.15 V VOL + 0.15 V Vy VOH − 0.3 V VOH − 0.15 V VOH − 0.15 V 74ALVC16245 http://onsemi.com 6 OPEN PULSE GENERATOR RT DUT VCC RL RL CL 6V or VCC × 2 GND TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 ±0.3 V; VCC× 2 at VCC = 2.5 ±0.2 V; 1.8 V ±0.15 V tPZH, tPHZ GND CL = 30 pF or equivalent (Includes jig and probe capacitance) RL = 500 � or equivalent RT = ZOUT of pulse generator (typically 50 �) Figure 5. Test Circuit 74ALVC16245 http://onsemi.com 7 Figure 6. Carrier Tape Specifications D1 FOR COMPONENTS 10 PITCHES CUMULATIVE TOLERANCE ON TAPE ±0.2 mm (±0.008") 2.0 mm × 1.2 mm AND LARGER CENTER LINES OF CAVITY EMBOSSMENT USER DIRECTION OF FEED K0 SEE NOTE 2 P0 P2D E F W B0 ++ + K t B1 TOP COVER TAPE P SEE NOTE 2A0 FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0 R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS �R" WITHOUT DAMAGE BENDING RADIUS *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. EMBOSSED CARRIER EMBOSSMENT TYPICAL COMPONENT CAVITY CENTER LINE TYPICAL COMPONENT CENTER LINE MAXIMUM COMPONENT ROTATION 10° CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm 100 mm (3.937") 1 mm (0.039") MAX 250 mm (9.843") 1 mm MAX TAPE EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2) Tape Size B1 Max D D1 E F K P P0 P2 R T W 24mm 20.1mm (0.791") 1.5 + 0.1mm −0.0 (0.059 +0.004" −0.0) 1.5mm Min (0.060") 1.75 ±0.1 mm (0.069 ±0.004") 11.5 ±0.10 mm (0.453 ±0.004") 11.9 mm Max (0.468") 16.0 ±0.1 mm (0.63 ±0.004") 4.0 ±0.1 mm (0.157 ±0.004") 2.0 ±0.1 mm (0.079 ±0.004") 30 mm (1.18") 0.6 mm (0.024") 24.3 mm (0.957") 1. Metric Dimensions Govern−English are in parentheses for reference only. 2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity. 74ALVC16245 http://onsemi.com 8 Figure 7. Reel Dimensions 13.0 mm ±0.2 mm (0.512" ±0.008")1.5 mm MIN (0.06") 50 mm MIN (1.969") 20.2 mm MIN (0.795") FULL RADIUS t MAX G A REEL DIMENSIONS Tape Size A Max G t Max 24 mm 360 mm (14.173") 24.4 mm + 2.0 mm, −0.0 (0.961" + 0.078", −0.00) 30.4 mm (1.197") Figure 8. Reel Winding Direction DIRECTION OF FEED BARCODE LABEL HOLEPOCKET 74ALVC16245 http://onsemi.com 9 TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN TAPE LEADER NO COMPONENTS 400 mm MIN COMPONENTS DIRECTION OF FEED CAVITY TAPE TOP TAPE Figure 9. Tape Ends for Finished Goods Figure 10. Reel Configuration User Direction of Feed L Figure 11. Package Footprint ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É F K G ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ 48 Leads 74ALVC16245 http://onsemi.com 10 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 1201−01 ISSUE A ÇÇÇ ÇÇÇ ÇÇÇ SUM0.12 (0.005) V ST S U M 0. 25 4 (0 .0 10 ) T −V− B A L K −U− 48X REF PIN 1 IDENT. 1 24 2548 0.076 (0.003) SEATING D −T− PLANE DIM MIN MAX MIN MAX INCHESMILLIMETERS A 12.40 12.60 0.488 0.496 B 6.00 6.20 0.236 0.244 C −−− 1.10 −−− 0.043 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.50 BSC 0.0197 BSC H 0.37 −−− 0.015 −−− J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.17 0.27 0.007 0.011 K1 0.17 0.23 0.007 0.009 L 7.95 8.25 0.313 0.325 M 0 8 0 8 � � � � NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. ÉÉÉ ÉÉÉ ÉÉÉ C G H −W− DETAIL E J K1 K J1 SECTION N−N M 0.25 (0.010) F DETAIL E N N ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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