A3984数据手册

24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Tr an sl at or CP1 CP2 VCP VREG MS1 MS2 RESET ROSC SLEEP VDD STEP REF GND ENABLE OUT2B VBB2 SENSE2 GND OUT2A OUT1A SENSE1 VBB1 OUT1B DIR C ha rg e Pu m p R eg O S C & C on tro l L og ic Description The A3984 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A3984 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A3984. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3984 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A3984 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A3984 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set 26184.30E Features and Benefits ▪ Low RDS(ON) outputs ▪ Automatic current decay mode detection/selection ▪ Mixed and Slow current decay modes ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal shutdown circuitry ▪ Crossover-current protection DMOS Microstepping Driver with Translator Continued on the next page… Package: 24-pin TSSOP with exposed thermal pad (suffix LP) Pin-out Diagram Not to scale A3984 DMOS Microstepping Driver with TranslatorA3984 2Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com THERMAL CHARACTERISTICS initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a slow decay for the remainder of the off-time). This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A3984 is supplied in a low-profile (1.2 mm maximum), 24-pin TSSOP with exposed thermal pad (package LP). It is lead (Pb) free, with 100% matte tin leadframe plating. Description (continued) Selection Guide Part Number Packing A3984SLPTR-T 4000 pieces per 13-in. reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage VBB 35 V Output Current IOUT Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction tem- perature of 150°C. ±2 A Logic Input Voltage VIN –0.3 to 7 V Sense Voltage VSENSE 0.5 V Reference Voltage VREF 4 V Operating Ambient Temperature TA Range S –20 to 85 ºC Maximum Junction TJ(max) 150 ºC Storage Temperature Tstg –55 to 150 ºC Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA 4-layer PCB, based on JEDEC standard 28 ºC/W *Additional thermal information available on Allegro Web site. 20 40 60 80 100 120 140 160 180 Temperature (°C) Po w er D is si pa tio n, P D (W ) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 Maximum Power Dissipation, PD(max) (R θJA = 28 ºC/W) DMOS Microstepping Driver with TranslatorA3984 3Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Functional Block Diagram SENSE1 SENSE2 VREG VCP CP2 Control Logic DAC VDD PWM Latch Blanking Mixed Decay DAC STEP DIR RESET MS1 PWM Latch Blanking Mixed Decay Current Regulator CP1 Charge Pump RS2 RS1 VBB1 OUT1A OUT1B VBB2 OUT2A OUT2B 0.1 uF VREF Translator Gate Drive DMOS Full Bridge DMOS Full Bridge 0.1 uF 0.22 uF OSC ROSC MS2 REF ENABLE SLEEP DMOS Microstepping Driver with TranslatorA3984 4Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) 1Negative current is defined as coming out of (sourcing from) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3errI = (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX ITripMAX. Characteristics Symbol Test Conditions Min. Typ.2 Max. Units Output Drivers Load Supply Voltage Range VBB Operating 8 – 35 V During Sleep Mode 0 – 35 V Logic Supply Voltage Range VDD Operating 3.0 – 5.5 V Output On Resistance RDSON Source Driver, IOUT = –1.5 A – 0.350 0.450 Ω Sink Driver, IOUT = 1.5 A – 0.300 0.370 Ω Body Diode Forward Voltage VF Source Diode, IF = –1.5 A – – 1.2 V Sink Diode, IF = 1.5 A – – 1.2 V Motor Supply Current IBB fPWM < 50 kHz – – 4 mA Operating, outputs disabled – – 2 mA Sleep Mode – – 10 μA Logic Supply Current IDD fPWM < 50 kHz – – 8 mA Outputs off – – 5 mA Sleep Mode – – 10 μA Control Logic Logic Input Voltage VIN(1) VDD0.7 – – V VIN(0) – – VDD0.3 V Logic Input Current IIN(1) VIN = VDD0.7 –20 <1.0 20 μA IIN(0) VIN = VDD0.3 –20 <1.0 20 μA Microstep Select 2 MS2 – 50 – kΩ Input Hysteresis VHYS(IN) 150 300 500 mV Blank Time tBLANK 0.7 1 1.3 μs Fixed Off-Time tOFF OSC > 3 V 20 30 40 μs ROSC = 25 kΩ 23 30 37 μs Reference Input Voltage Range VREF 0 – 4 V Reference Input Current IREF –3 0 3 μA Current Trip-Level Error3 errI VREF = 2 V, %ITripMAX = 38.27% – – ±15 % VREF = 2 V, %ITripMAX = 70.71% – – ±5 % VREF = 2 V, %ITripMAX = 100.00% – – ±5 % Crossover Dead Time tDT 100 475 800 ns Protection Thermal Shutdown Temperature TJ – 165 – °C Thermal Shutdown Hysteresis TJHYS – 15 – °C UVLO Enable Threshold UVLO VDD rising 2.35 2.7 3 V UVLO Hysteresis UVHYS 0.05 0.10 – V DMOS Microstepping Driver with TranslatorA3984 5Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Figure 1. Logic Interface Timing Diagram STEP t A t D t C MS1, MS2, RESET, or DIR t B Table 1. Microstep Resolution Truth Table MS1 MS2 Microstep Resolution Excitation Mode L L Full Step 2 Phase H L Half Step 1-2 Phase L H Quarter Step W1-2 Phase H H Sixteenth Step 4W1-2 Phase Time Duration Symbol Typ. Unit STEP minimum, HIGH pulse width tA 1 μs STEP minimum, LOW pulse width tB 1 μs Setup time, input change to STEP tC 200 ns Hold time, input change to STEP tD 200 ns DMOS Microstepping Driver with TranslatorA3984 6Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Functional Description Device Operation. The A3984 is a complete microstep- ping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PMW (pulse width modulated) control cir- cuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 or RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in fig- ures 2 through 5), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of inputs MS1 and MS2, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. RESET Input (RESET). The RESET input sets the translator to a predefined Home state (shown in figures 2 through 5), and turns off all of the DMOS outputs. All STEP inputs are ignored until the RESET input is set to high. Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of inputs MS1 and MS2. Microstep Select (MS1 and MS2). Selects the micro- stepping format, as shown in table 1. MS2 has a 50 kΩ pull- down resistance. Any changes made to these inputs do not take effect until the next STEP rising edge. Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction will be clock- wise and when high, counterclockwise. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Ini- tially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense compara- tor resets the PWM latch. The latch then turns off either the source DMOS FETs (when in Slow Decay Mode) or the sink and source DMOS FETs (when in Mixed Decay Mode). The maximum value of current limiting is set by the selec- tion of RSx and the voltage at the VREF pin. The transcon- ductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF / ( 8  RS ) where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100) × ITripMAX (See table 2 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control cir- cuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The one shot off-time, tOFF, is determined by the selection of an external resistor con- nected from the ROSC timing pin to ground. If the ROSC Functional Description DMOS Microstepping Driver with TranslatorA3984 7Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com pin is tied to an external voltage > 3 V, then tOFF defaults to 30 μs. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of tOFF (μs) is approximately tOFF = ROSC ⁄ 825 Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μs), is approximately tBLANK ≈ 1 μs Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side DMOS gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side DMOS gates. VREG (VREG). This internally-generated voltage is used to operate the sink-side DMOS outputs. The VREG pin must be decoupled with a 0.22 μF capacitor to ground. VREG is internally monitored. In the case of a fault condition, the DMOS outputs of the A3984 are disabled. Enable Input (ENABLE). This input turns on or off all of the DMOS outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, MS1, and MS2, as well as the internal sequencing logic, all remain active, independent of the ENABLE input state. Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the DMOS outputs of the A3984 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the DMOS outputs and resets the translator to the Home state. Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output DMOS FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A3984 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A3984 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 thru 5. As the trip point is reached, the A3984 initially goes into a fast decay mode for 31.25% of the off-time. tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recir- culates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low DMOS RDSON. This reduces power dissipa- tion significantly, and can eliminate the need for external Schottky diodes in many applications. Turning off synchronous rectification prevents the reversal of the load current when a zero-current level is detected. DMOS Microstepping Driver with TranslatorA3984 8Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Figure 4. Decay Modes for Quarter-Step Increments Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments Phase 2 IOUT2A Direction = H (%) Phase 1 IOUT1A Direction = H (%) STEP H om e M ic ro st ep P os iti on H om e M ic ro st ep P os iti on 100.00 70.71 –70.71 0.00 –100.00 100.00 70.71 –70.71 0.00 –100.00 Slow Slow H om e M ic ro st ep P os iti on H om e M ic ro st ep P os iti on 100.00 70.71 –70.71 0.00 –100.00 100.00 70.71 –70.71 0.00 –100.00 Phase 2 IOUT2B Direction = H (%) Phase 1 IOUT1A Direction = H (%) STEP Slow Mixed Slow Mixed Slow Mixed Mixed Slow Mixed Slow Mixed SlowSlow 0.00 100.00 92.39 70.71 38.27 –38.27 –70.71 –92.39 –100.00 0.00 100.00 92.39 70.71 38.27 –38.27 –70.71 –92.39 –100.00 Phase 2 IOUT2B Direction = H (%) Phase 1 IOUT1A Direction = H (%) H om e M ic ro st ep P os iti on Slow Mixed SlowSlow Mixed Slow Mixed Slow MixedMixed STEP Slow DMOS Microstepping Driver with TranslatorA3984 9Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Figure 5. Decay Modes for Sixteenth-Step Increments MixedSlow MixedSlow MixedSlow Slow Slow 100.00 95.69 88.19 83.15 –83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.8 0.00 –100.00 –95.69 –88.19 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.8 100.00 95.69 88.19 83.15 –83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.8 0.00 –100.00 –95.69 –88.19 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.8 Phase 2 IOUT2B Direction = H (%) Phase 1 IOUT1A Direction = H (%) H om e M ic ro st ep P os iti on Mixed STEP DMOS Microstepping Driver with TranslatorA3984 10Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Full Step # Half Step # 1/4 Step # 1/16 Step # Phase 1 Current [% ItripMax] (%) Phase 2 Current [% ItripMax] (%) Step Angle (º) Full Step # Half Step # 1/4 Step # 1/16 Step # Phase 1 Current [% ItripMax] (%) Phase 2 Current [% ItripMax] (%) Step Angle (º) 1 1 1 100.00 0.00 0.0 5 9 33 –100.00 0.00 180.0 2 99.52 9.80 5.6 34 –99.52 –9.80 185.6 3 98.08 19.51 11.3 35 –98.08 –19.51 191.3 4 95.69 29.03 16.9 36 –95.69 –29.03 196.9 2 5 92.39 38.27 22.5 10 37 –92.39 –38.27 202.5 6 88.19 47.14 28.1 38 –88.19 –47.14 208.1 7 83.15 55.56 33.8 39 –83.15 –55.56 213.8 8 77.30 63.44 39.4 40 –77.30 –63.44 219.4 1 2 3 9 70.71 70.71 45.0 3 6 11 41 –70.71 –70.71 225.0 10 63.44 77.30 50.6 42 –63.44 –77.30 230.6 11 55.56 83.15 56.3 43 –55.56 –83.15 236.3 12 47.14 88.19 61.9 44 –47.14 –88.19 241.9 4 13 38.27 92.39 67.5 12 45 –38.27 –92.39 247.5 14 29.03 95.69 73.1 46 –29.03 –95.69 253.1 15 19.51 98.08 78.8 47 –19.51 –98.08 258.8 16 9.80 99.52 84.4 48 –9.80 –99.52 264.4 3 5 17 0.00 100.00 90.0 7 13 49 0.00 –100.00 270.0 18 –9.80 99.52 95.6 50 9.80 –99.52 275.6 19 –19.51 98.08 101.3 51 19.51 –98.08 281.3 20 –29.03 95.69 106.9 52 29.03 –95.69 286.9 6 21 –38.27 92.39 112.5 14 53 38.27 –92.39 292.5 22 –47.14 88.19 118.1 54 47.14 –88.19 298.1 23 –55.56 83.15 123.8 55 55.56 –83.15 303.8 24 –63.44 77.30 129.4 56 63.44 –77.30 309.4 2 4 7 25 –70.71 70.71 135.0 4 8 15 57 70.71 –70.71 315.0 26 –77.30 63.44 140.6 58 77.30 –63.44 320.6 27 –83.15 55.56 146.3 59 83.15 –55.56 326.3 28 –88.19 47.14 151.9 60 88.19 –47.14 331.9 8 29 –92.39 38.27 157.5 16 61 92.39 –38.27 337.5 30 –95.69 29.03 163.1 62 95.69 –29.03 343.1 31 –98.08 19.51 168.8 63 98.08 –19.51 348.8 32 –99.52 9.80 174.4 64 99.52 –9.80 354.4 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H DMOS Microstepping Driver with TranslatorA3984 11Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Pin List Table Name Description Number CP1 Charge pump capacitor 1 1 CP2 Charge pump capacitor 2 2 VCP Reservoir capacitor 3 VREG Regulator decoupling 4 MS1 Logic input 5 MS2 Logic input 6 RESET Logic input 7 ROSC Timing set 8 SLEEP Logic input 9 VDD Logic supply 10 STEP Logic input 11 REF Current trip reference voltage input 12 GND Ground* 13 DIR Logic input 14 OUT1B DMOS Full Bridge 1 Output B 15 VBB1 Load supply 16 SENSE1 Sense resistor for Bridge 1 17 OUT1A DMOS Full Bridge 1 Output A 18 OUT2A DMOS Full Bridge 2 Output A 19 SENSE2 Sense resisto