FPGA可编程逻辑器件芯片XQR4013XL-3CB228M中文规格书

PCIExpressEndpointConnectivity[Figure1-2,callout13]The8-lanePCIExpressedgeconnectorperformsdatatransfersattherateof2.5gigatransferspersecond(GT/s)foraGen1applicationand5.0GT/sforaGen2application.ThePCIetransmitandreceivesignaldatapathshaveacharacteristicimpedanceof85Ω±10%.ThePCIeclockisroutedasa100Ωdifferentialpair.The7seriesFPGAsGTXtransceiversareusedformulti-gigabitpersecondserialinterfaces.TheXC7VX485T-2FFG1761CFPGA(-2speedgrade)includedwiththeVC707boardsupportsuptoGen2x8.ThePCIeclockisinputfromtheedgeconnector.ItisACcoupledtotheFPGAthroughtheMGTREFCLK1pinsofQuad115.PCIE_CLK_Q0_PisconnectedtoFPGAU1pinAB8,andthe_NnetisconnectedtopinAB7.ThePCIExpressclockcircuitisshowninFigure1-14.X-RefTarget-Figure1-14P1PCIExpressEight-LaneEdgeconnectorOEC544A120.01μF25VGNDX7RA13PCIE_CLK_Q0_C_PPCIE_CLK_Q0_PREFCLK+A14PCIE_CLK_Q0_C_NPCIE_CLK_Q0_NREFCLK-A15C545GND0.01μF25VGNDX7RUG885_c1_14_020612Figure1-14:PCIExpressClockPCIelanewidth/sizeisselectedthroughjumperJ49(Figure1-15).Thedefaultlanesizeselectionis1-lane(J49pins1and2jumpered).X-RefTarget-Figure1-15J49PCIE_PRSNT_X112PCIE_PRSNT_BPCIE_PRSNT_X434PCIE_PRSNT_X856UG885_c1_15_020612Figure1-15:PCIExpressLaneSizeSelectJumperJ49Table1-12liststhePCIeedgeconnectorconnectionsatP1.Table1-12:PCIeEdgeConnectorConnectionsGTXQuad115FPGA(U1)PCIeEdgeConnector(P1)FHG1761NetNameFunctionPinPinNamePlacementPCIE_RX0_PY4B14PETp0IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y11PCIE_RX0_NY3B15PETn0IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y11PCIE_RX1_PAA6B19PETp1IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y10PCIE_RX1_NAA5B20PETn1IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y10PCIE_RX2_PAB4B23PETp2IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y9PCIE_RX2_NAB3B24PETn2IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y9PCIE_RX3_PAC6B27PETp3IntegratedEndpointblockreceivepairGTXE2_CHANNEL_X1Y8VC707EvaluationBoardUG885(v1.8)February20,2019FeatureDescriptionsSGMIIGTXTransceiverClockGeneration[Figure1-2,callout16]AnIntegratedCircuitSystemsICS844021Ichip(U2)generatesahigh-quality,low-jitter,125MHzLVDSclockfroma25MHzcrystal(X3).ThisclockissenttoFPGAU1,Bank113GTXtransceiver(clockpinsAH8(P)andAH7(N))drivingtheSGMIIinterface.SeriesACcouplingcapacitorsarepresenttoallowtheclockinputoftheFPGAtosetthecommonmodevoltage.Figure1-17showstheEthernetSGMIIclocksource.X-RefTarget-Figure1-17C300VDDA_SGMIICLKVDD_SGMIICLK18pF50VU2NPOICS844021I-01ClockGeneratorX35OEC2825.00MHz180.1μF25VVDDAVDDX5R2X11SGMIICLK_XTAL_OUT37SGMIICLK_Q0_C_PSGMIICLK_Q0_PR320GND2XTAL_OUTQ01.0MΩ5%C3014GND2X23SGMIICLK_XTAL_IN46SGMIICLK_Q0_C_NSGMIICLK_Q0_N18pF50VXTAL_INNQ0NPO2GNDC290.1μF25VX5RGND_SGMIICLKGND_SGMIICLKGND_SGMIICLKUG885_c1_17_020612VC707EvaluationBoardUG885(v1.8)February20,2019Chapter1:VC707EvaluationBoardFeaturesdriversmustbeinstalledonthehostPCpriortoestablishingcommunicationswiththeVC707board.TheUSBConnectorPinAssignmentsandSignalDefinitionsbetweenJ17andU44arelistedinTable1-19.Table1-19:USBConnectorJ17PinAssignmentsandSignalDefinitionsUSBConnector(J17)CP2103GM(U44)NetNameDescriptionPinNamePinName7REGIN1VBUSUSB_UART_VBUS+5VVBUSPowered8VBUS2D_NUSB_D_NBidirectionaldifferentialserialdata(N-side)4D–3D_PUSB_D_PBidirectionaldifferentialserialdata(P-side)3D+2GND14GNDUSB_UART_GNDSignalground29CNR_GNDTable1-20showstheUSBconnectionsbetweentheFPGAandtheUART.Table1-20:FPGAtoUARTConnectionsFPGA(U1)SchematicNetCP2013Device(U12)PinFunctionDirectionIOSTANDARDNamePinFunctionDirectionAR34RTSOutputLVCMOS18USB_CTS22CTSInputAT32CTSInputLVCMOS18USB_RTS23RTSOutputAU36TXOutputLVCMOS18USB_RX24RXDInputAU33RXInputLVCMOS18USB_TX25TXDOutputRefertotheSiliconLabswebsitefortechnicalinformationontheCP2103GMandtheVCPdrivers[Ref20].HDMIVideoOutput[Figure1-2,callout18]TheVC707boardprovidesaHigh-DefinitionMultimediaInterface(HDMI™)videooutputusingtheAnalogDevicesADV7511KSTZ-PHDMItransmitter(U48).TheHDMIoutputisprovidedonaMolex500254-1927HDMItype-Aconnector(P2).TheADV7511iswiredtosupport1080P60HzYCbCrandRGBvideomodesthrough36-bitinputdatamapping.TheVC707boardsupportsthefollowingHDMIdeviceinterfaces:•36datalines•IndependentVSYNC,HSYNC•Single-endedinputCLK•InterruptOutPintoFPGA•I2C•SPDIFVC707EvaluationBoardUG885(v1.8)February20,2019Chapter1:VC707EvaluationBoardFeaturesTheVC707boardI2CbustopologyisshowninFigure1-22.X-RefTarget-Figure1-22U52PCA954812C1-to-8BusSwitchU1CH0-USER_CLK_SDL/SCLFPGACH1-FMC1_HPC_IIC_SDA/SCLBank15CH2-FMC2_HPC_IIC_SDA/SCL(2.5V)CH3-EEPROM_IIC_SDA/SCLIIC_SDA/SCL_MAINCH4-SFP_IIC_SDA/SCLCH5-IIC_SDA/SCL_HDMICH6-IIC_SDA/SCL_DDR3CH7-SI5324_SDA/SCLUG855_C1_22_021012Figure1-22:I2CBusTopologyUserapplicationsthatcommunicatewithdevicesononeofthedownstreamI2CbusesmustfirstsetupapathtothedesiredbusthroughtheU52busswitchatI2Caddress0x74(0b1110100).Table1-24liststheaddressforeachbus.Table1-24:I2CBusAddressesI2CSwitchI2CDeviceI2CAddressPositionPCA9548NA0b1110100Si570Clock00b1011101FMC1HPC10bXXXXX00FMC2HPC20bXXXXX00M24C08EEPROM30b1010100SFPModule40b1010000ADV7512HDMI50b0111001DDR3SODIMM60b1010000,0b0011000Si5324Clock70b1101000Notes:1.UsethePCA9458(U52)atI2Caddress0x74(0b1110100)tosetupthepathtothesebuses.InformationaboutthePCA9548isavailableontheTISemiconductorwebsite[Ref25].Caution!ThePCA9548U52RESET_Bpin24isconnectedtotheFPGAU1bank15pinAY42vialevel-shifterU70.TheFPGApinAY42LVCMOS18netIIC_MUX_RESET_B_LSmustbedrivenHightoenableI2CbustransactionswiththedevicesconnectedtoU52.VC707EvaluationBoardUG885(v1.8)February20,2019FeatureDescriptionsStatusLEDs[Figure1-2,callout21]Table1-25definesthestatusLEDs.ForusercontrolledLEDsseeUserI/O.Table1-25:StatusLEDsReferenceSignalNameColorDescriptionDesignatorDS11PHY_LED_RXGREENEthernetPHYRXDS11PHY_LED_LINK1000GREENEthernetLinkSpeedis1000Mb/sDS12PHY_LED_TXGREENEthernetPHYTXDS12PHY_LED_LINK100GREENEthernetLinkSpeedis100Mb/sDS13PHY_LED_DUPLEXGREENEthernetLinkisHalf-duplexDS13PHY_LED_LINK10GREENEthernetLinkSpeedis10Mb/sDS14PWRCTL1_VCC4A_PGGREENFMC1HPCPowerGoodDS10FPGA_DONEGREENFPGAConfiguredSuccessfullyGREEN:FPGAInitializationSuccessful,DS1FPGA_INIT_BGREEN/REDRED:FPGAInitializationinProgressDS16VCC12_P_INGREEN12VPowerONUCD9248PowerControllers(U42,U43,U64)DS17PWRCTL_PWRGOODGREENPowerGoodDS18LINEAR_POWER_GOODGREENTPS51200PowerGood(U23)UserI/O[Figure1-2,callout22-26]TheVC707boardprovidesthefollowinguserandgeneralpurposeI/Ocapabilities:•EightuserLEDs(callout22)•GPIO_LED_[7-0]:DS9,DS8,DS7,DS6,DS5,DS4,DS3,DS2•Resetswitchandfiveuserpushbuttons(callout23)•CPU_RESET:SW8•GPIO_SW_[NESWC]:SW3,SW4,SW5,SW7,SW6•8-positionuserDIPSwitch(callout24)•GPIO_DIP_SW[7-0]:SW2•Userrotaryswitch(callout25,hiddenbeneaththeLCD)•ROTARY_PUSH,ROTARY_INCA,ROTARY_INCB:SW10•UserSMA(callout26)•USER_SMA_GPIO_P,USER_SMA_GPIO_N:J33,J34•2linex16characterLCDcharacterdisplay(callout19)•Ifthedisplayisunmounted,connectorJ23pinsareavailableas7independentGPIOs.TheLCDconnectorJ23detailsareshownintheLCDCharacterDisplay(16x2)section.VC707EvaluationBoardUG885(v1.8)February20,2019