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Application Note AN4140 Transformer Design Consideration for off-line Flyback Converters using Fairchild Power Switch (FPSTM) www.fairchildsemi.com ©2003 Fairchild Semiconductor Corporation Rev. 1.0.0 1. Introduction For flyback coverters, the transformer is the most important factor that determines the performance such as the efficiency, output regulation and EMI. Contrary to the normal transformer, the flyback transformer is inherently an inductor that provides energy storage, coupling and isolation for the flyback converter. In the general transformer, the current flows in both the primary and secondary winding at the same time. However, in the flyback transformer, the current flows only in the primary winding while the energy in the core is charged and in the secondary winding while the energy in the core is discharged. Usually gap is introduced between the core to increase the energy storage capacity. This paper presents practical design considerations of transformers for off-line flyback converters employing Fairchild Power Switch (FPS). In order to give insight to the reader, practical design examples are also provided. 2. General Transformer design procedure (1) Choose the proper core Core type : Ferrite is the most widely used core material for commercial SMPS (Switchied mode power supply) applications. Various ferrite cores and bobbins are shown in Figure 1. The type of the core should be chosen with regard to system requirements including number of outputs, physical height, cost and so on. Table 1 shows features and typical application of various cores. Figure 1. Ferrite core (TDK) Table 1. Features and typical applications of various cores Core size : Actually, the initial selection of the core is bound to be crude since there are too many variables. One way to select the proper core is to refer to the manufacture's core selection guide. If there is no proper reference, use the table 2 as a starting point. The core recommended in table 1 is typical for the universal input range, 67kHz switching frequency and 12V single output application. When the input voltage range is 195-265 Vac (European input range) or the switching frequency is higher than 67kHz, a smaller core can be used. For an application with low voltage and/or multiple outputs, usually a larger core should be used than recommended in the table. Table 2. Core quick selection table (For universal input range, fs=67kHz and 12V single output) Core Features Typical Applications EE EI -Low cost Aux. power Battery charger EFD EPC -Low profile LCD Monitor EER -Large winding window area -Various bobbins for multiple output CRT monitor, C-TV DVDP, STB PQ -Large cross sectional area -Relatively expensive Output Power EI core EE core EPC core EER core 0-10W EI12.5 EI16 EI19 EE8 EE10 EE13 EE16 EPC10 EPC13 EPC17 10-20W EI22 EE19 EPC19 20-30W EI25 EE22 EPC25 EER25.5 30-50W EI28 EI30 EE25 EPC30 EER28 50-70W EI35 EE30 EER28L 70-100W EI40 EE35 EER35 100-150W EI50 EE40 EER40 EER42 150-200W EI60 EE50 EE60 EER49 AN4140 APPLICATION NOTE 2 ©2002 Fairchild Semiconductor Corporation Once the core type and size are determined, the following variables are obtained from the core data sheet. - Ae : The cross-sectional area of the core (mm2) - Aw : Winding window area (mm2) - Bsat : Core saturation flux density (tesla) Figure 2 shows the Ae and Aw of a core. The typical B-H characteristics of ferrite core from TDK (PC40) are shown in Figure 3. Since the saturation flux density (Bsat) decreases as the temperature increases, the high temperature character- istics should be considered. If there is no reference data, use Bsat =0.3~0.35 T. Figure 2. Window Area and Cross Sectional Area Figure 3. Typical B-H characteristics of ferrite core (TDK/PC40) (2) Determine the primary side inductance (Lm) of the transformer In order to determine the primary side inductance, the following variables should be determined first. (For a detailed design procedure, please refer to the application note AN4137.) - Pin : Maximum input power - fs : Switching frequency of FPS device - VDCmin : Minimum DC link voltage - Dmax : Maximum duty cycle - KRF : Ripple factor, which is defined at the minimum input voltage and full load condition, as shown in Figure 4. For DCM operation, KRF = 1 and for CCM operation KRF < 1. The ripple factor is closely related with the transformer size and the RMS value of the MOSFET current. Even though the conduction loss in the MOSFET can be reduced through reducing the ripple factor, too small a ripple factor forces an increase in transformer size. Considering both efficiency and core size, it is reasonable to set KRF = 0.3-0.5 for the universal input range and KRF = 0.4-0.8 for the European input range. Meanwhile, in the case of low power applications below 5W where size is most critical, a relatively large ripple factor is used in order to minimize the transformer size. In that case, it is typical to set KRF = 0.5- 0.7 for the universal input range and KRF = 1.0 for the European input range. Figure 4. MOSFET Drain Current and Ripple Factor (KRF) With the given variables, the primary side inductance, Lm is obtained as AwAwAwAw AeAeAeAe 100 500 400 300 200 800 1600 0 0 Magnetic field H (A/m ) Fl ux d en sit y B (m T) M agnetization Curves (typical) M aterial :PC40 100 ℃℃℃℃ 120 ℃℃℃℃ 60 ℃℃℃℃ 25 ℃℃℃℃ I∆ EDCI EDC RF I IK 2 ∆ = CCM operation : KRF < 1 I∆ EDCI EDC RF I IK 2 ∆ = DCM operation : KRF =1 peak dsI peak dsI Dmax Dmax Lm VDC min Dmax⋅( ) 2 2PinfsKRF ----------------------------------------------= (1) APPLICATION NOTE AN4140 3 ©2002 Fairchild Semiconductor Corporation where VDCmin is the minimum DC input voltage, Dmax is the maximum duty cycle, Pin is the maximum input power, fs is the switching frequency of the FPS device and KRF is the ripple factor. Once Lm is determined, the maximum peak current and RMS current of the MOSFET in normal operation are obtained as With the chosen core, the minimum number of turns for the transformer primary side to avoid the core saturation is given by where Lm is the primary side inductance, Iover is the FPS pulse-by-pulse current limit level, Ae is the cross-sectional area of the core and Bsat is the saturation flux density in tesla. If the pulse-by-pulse current limit level of FPS is larger than the peak drain current of the power supply design, it may result in excessive transformer size since Iover is used in determining the minimum primary side turns as shown in equation (6). Therefore, it is required to choose a FPS with proper current limit specifications or to adjust the peak drain current close to Iover by increasing the ripple factor as shown in Figure 5. It is reasonable to design Idspeak to be 70-80% of Iover considering the transient response and tolerance of Iover. Figure 5. Adjustment peak drain current (3) Determine the number of turns for each output Figure 6 shows the simplified diagram of the transformer, whrere Vo1 stands for the reference output that is regulated by the feedback control while Vo(n) stands for the n-th output. First, determine the turns ratio (n) between the primary side and the feedback controlled secondary side as a reference. where Np and Ns1 are the number of turns for primary side and reference output, respectively, Vo1 is the output voltage and VF1 is the diode (DR1) forward voltage drop of the reference output that is regulated by the feedback control. Then, determine the proper integer for Ns1 so that the resulting Np is larger than Npmin obtained from equation (6). The number of turns for the other output (n-th output) is determined as The number of turns for Vcc winding is determined as where Vcc* is the nominal value of the supply voltage of the FPS device, and VFa is the forward voltage drop of Da as defined in Figure 6. Since Vcc increases as the output load increases, it is proper to set Vcc* as Vcc start voltage (refer to the data sheet) to avoid triggering the over voltage protection during normal operation. Figure 6. Simplified diagram of the transformer Ids peak IEDC ∆I 2 -----+= (2) Ids rms 3 IEDC( ) 2 ∆I 2 -----    2+ Dmax 3 --------------= 3( ) where IEDC Pin VDC min Dmax⋅ --------------------------------------= 4( ) and ∆I VDC min Dmax Lmfs -----------------------------------= (5) NP min LmIover BsatAe ------------------- 106 (turns)×= (6) I∆ EDCI Increasing ripple factor (KRF) peak dsI Pulse-by-pulse current limit of FPS (Iover) I∆ peak dsI Decreasing pirmary side Inductance (Lm)= 70-80% of Iover n VR0 Vo1 VF1+ -------------------------- NP Ns1 ---------= = (7) Ns n( ) Vo n( ) VF n( )+ Vo1 VF1+ ---------------------------------= Ns1⋅ turns( ) 8( ) Na Vcc* VFa+ Vo1 VF1+ ----------------------------= Ns1⋅ turns( ) 9( ) Np NS1 - VRO + DR1 Na Da NS(n) DR(n) + VO(n) - + VO1 - + VF(n) - + VF1 -- VFa + + Vcc* - AN4140 APPLICATION NOTE 4 ©2002 Fairchild Semiconductor Corporation Once the number of turns on the primary side have been determined, the gap length of the core is obtained through approximation as where AL is the AL-value with no gap in nH/turns2, Ae is the cross sectional area of the core as shown in Figure 2, Lm is specified in equation (1) and Np is the number of turns for the primary side of the transformer (4) Determine the wire diameter for each winding The wire diameter is determined based on the rms current through the wire. The current density is typically 5A/mm2 when the wire is long (>1m). When the wire is short with a small number of turns, a current density of 6-10 A/mm2 is also acceptable. Avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses as well as to make winding easier. For high current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect. 3. Transformer Construction Method. (1) Winding Sequence (a) Primary winding Figure 7. Primary side winding It is typical to place all the primary winding or a portion of the primary winding innermost on the bobbin. This minimizes the length of wire, reducing the conduction loss in the wire. The EMI noise radiation can be reduced, since the other windings can act as Faraday shields. When the primary side winding has more than two layers, the innermost layer winding should start from the drain pin of FPS as shown in Figure 7. This allows the winding driven by the highest voltage to be shielded by other windings, thereby maximizing the shielding effect. (b) Vcc winding In general, the voltage of each winding is influenced by the voltage of the adjacent winding. The optimum placement of the Vcc winding is determined by the over voltage protection (OVP) sensitivity, the Vcc operating range and control scheme. -Over voltage protection (OVP) sensitivity : When the output voltage goes above its normal operation value due to some abnormal situation, Vcc voltage also increases. FPS uses Vcc voltage to indirectly monitor the over voltage situation in the secondary side. However, a RCD snubber network acts as an another output as shown in Figure 8 and Vcc voltage is also influenced by the snubber capacitor voltage. Because the snubber voltage increases as the drain current increases, OVP of FPS can be triggered not only by the output over voltage condition, but also by the over load condition. The sensitivity of over voltage protection is closely related to the physical distance between windings. If the Vcc winding is close to the secondary side output winding, Vcc voltage will change sensitively to the variation of the output voltage. Meanwhile, if the Vcc winding is placed close to the primary side winding, Vcc voltage will vary sensitively as the snubber capacitor voltage changes. Figure 8. Primary side winding G 40πAe NP 2 1000Lm --------------------- 1 AL ------–       = mm( ) 10( ) 3mm 3mm ........ Np/2 ...... ....... Np/2 ..... .......... Ns ......... ...... Na ... To FPS Drain pin Bobbin Barrier tape Insulation tape Np NS1 - Vsn + Na NS2 + Vcc - + VO2 - + VO1 - APPLICATION NOTE AN4140 5 ©2002 Fairchild Semiconductor Corporation - Vcc operating range : As mentioned above, Vcc voltage is influenced by the snubber capacitor voltage. Since the snubber capacitor voltage changes according to drain current, Vcc voltage can go above its operating range triggering OVP in normal operation. In that case, Vcc winding should be placed closest to the reference output winding that is regulated by feedback control and far from the primary side winding as shown in Figure 9. Figure 9. Winding sequence to reduce Vcc variation - Control scheme : In the case of primary side regulation, the output voltages should follow the Vcc voltage tightly for a good output regulation. Therefore, Vcc winding should be placed close to the secondary windings to maximize the coupling of the Vcc winding with the secondary windings. Meanwhile, Vcc winding should be placed far from primary winding to minimize coupling to the primary. In the case of secondary side regulation, the Vcc winding can be placed between the primary and secondary or on the outermost position. (c) Secondary side winding When it comes to a transformer with multiple outputs, the highest output power winding should be placed closest to the primary side winding, to reduce leakage inductance and to maximize energy transfer efficiency. If a secondary side winding has relatively few turns, the winding should be spaced to traverse the entire width of the winding area for improved coupling. Using multiple parallel strands of wire will also help to increase the fill factor and coupling for the secondary windings with few turns as shown in Figure 10. To maximize the load regulation, the winding of the output with tight regulation requirement should be placed closest to the winding of the reference output that is regulated by the feedback control. Figure 10. Multiple parallel strands winding (2) Winding method -Stacked winding on other winding: A common technique for winding multiple outputs with the same polarity sharing a common ground is to stack the secondary windings instead of winding each output winding separately, as shown in Figure 11. This approach will improve the load regulation of the stacked outputs and reduce the total number of secondary turns. The windings for the lowest voltage output provide the return and part of the winding turns for the next higher voltage output. The turns of both the lowest output and the next higher output provide turns for succeeding outputs. The wire for each output must be sized to accommodate its output current plus the sum of the output currents of all the output stacked on top of it. -Stacked winding on other output: If a transformer has a very high voltage and low current output, the winding can be stacked on the lower voltage output as shown in Figure 12. This approach provides better regulation and reduced diode voltage stress for the stacked output. The wire and rectifier diode for each output must be sized to accommodate its output current plus the sum of the output currents of all the output stacked on top of it. 3mm 3mm .......... Np ......... ........ Ns2 ....... ..... Ns1 (Reference output) ..... ...... Na (Vcc winding) ..... .............. Np .............. .............. Np .............. Secondary winding (4 turns) Secondary winding (3 strands, 4 turns) AN4140 APPLICATION NOTE 6 ©2002 Fairchild Semiconductor Corporation Figure 11. Stacked winding on other winding Figure 12. Stacked winding on other output (3) Minimization of Leakage Inductance The winding order in a transformer has a large effect on the leakage inductance. In a multiple output transformer, the secondary with the highest output power should be placed closest to the primary for the best coupling and lowest leakage. The most common and effective way to minimize the leakage inductance is a sandwich winding as shown in Figure 13. Secondary windings with only a few turns should be spaced across the width of the bobbin window instead of being bunched together, in order to maximize coupling to the primary. Using multiple parallel strands of wire is an additional technique of increasing the fill factor and coupling of a winding with few turns as shown in Figure 10. Figure 13. Sandwich winding (4) Transformer shielding A major source of common mode EMI in Switched Mode Power Supply (SMPS) is the parasitic capacitances coupled to the switching devices. The MOSFET drain voltage drives capacitive current through various parasitic capacitances. Some portion of these capacitive currents flow into the neutral line that is connected to the earth ground and observed as common mode noise. By using an electrostatic separation shield between the windings (at primary winding side, or at secondary winding side, or both), the common mode signal is effectively "shorted" to the ground and the capacitive current is reduced. When properly designed, such shielding can dramatically reduce the conducted and radiated emissions and susceptibility. By using this technique, the size of EMI filter can be reduced. The shield can be easily implemented using copper foil or tightly wound wire. The shield should be virtually grounded to a quiescent point such as primary side DC link, primary ground or secondary ground. Figure 14 shows a shielding example, which allows the removal of the Y-capacitor that is commonly used to reduce common mode EMI. As can be seen, shields are used not only on the bottom but also on the top of the primary winding in order to cancel the coupling of parasitic capaci- tances. Figure 15 also shows the detailed shielding construction. Np NS1 DR1 VO1 NS2 DR2 VO2 Np NS1 DR1 VO1 NS2 DR2 VO2 3mm 3mm .............. Np/2 .............. .............. Ns2 .............. .............. Ns1 .............. .............. Na .............. .............. Np/2 .............. AN4140 APPLICATION NOTE 7 ©2003 Fairchild Semiconductor Corporation Figure 14. Shielding example to remove Y-capacitor (5) Practical examples of transformer construction As described in the above sections, there many factors that should be considered in determining the winding sequence and winding method. In this section some practical examples of transformer construction are presented to give a compre- hensive understanding of practical transformer construction. Figure 15. Shielding method to remove Y-Capacitor a) LCD monitor SMPS example Figure 16 shows a simplified transformer schematic for typical LCD monitor SMPS. The 5V output is for the Micro- processor and 13V output is for the inverter input of LCD back light. While 5V output is regulated with the feedback control, 13V output is determined by the transformer turns ratio and a stacked winding is usually used to maximize the regulation. Np Na NS Drain DC link Shielding A Shielding B 3mm 3mm .............. Np .............. Shield A .............. Na .............. .............. Ns .............. Shield B Primary Winding #1 #2 #3 #4 #5 Winding Directio Winding Direction Insulation Tape Copper Foil #1 #2 #3 #4 #5 TOP BOTTOM Insulation Tape #1 #2 #3 #4 #5 Copper Foil APPLICATION NOTE AN4140 8 ©2003 Fairchild Semiconductor Corporation Transformer construction Example A (Figure 17) : In this example, the leakage inductance is minimized by employing a sandwich winding. The Vcc winding is placed outside to provide shielding effect. Since the Vcc winding is placed on the top half of primary winding, the coupling between the Vcc winding and 5V output winding is poor, which may require a s