e46a_QUANTA LL5 (2009-10-23) REV 1A

1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 A A B B C C D D Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 Block Diagram 1ACustom 1 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 Block Diagram 1ACustom 1 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 Block Diagram 1ACustom 1 38Friday, October 23, 2009 LL5 Intel Calpella Platform with UMA GFX ( rPGA 989 ) PCH DMI X 4 SATA IHDAAUDIO DC/DC AC/BATT CONNECTOR BATT CHARGER Auburndale / Arrandale RUN POWER SW USB2.0 x 3 USB conn x 3 SPI PS/2 KeyboardTouchpad LPC SATA-HDD SATA KBC ITE8502 RTS5159 PCIEx1 USB2.0 USB2.0 EXPRESS-CARD MINI-CARD (F1) 7-in-1 Card Reader WWAN USB2.0 PCIEX1 R5538 CPU CoreREGULATOR 3VPCU, 5VPCU, +15V POWER +1.05V_VTT,+1.05V_PCH REGULATOR (DDR3) 1.5VSUS, SMDDR_VREF,1.5V POWER 3VSUS, 5VSUS, 3V_S5, 5V_S5 SATA-ODD RJ45/MagneticsLAN MINI-CARD WLAN/WiMAXAudio Jacks Card Reader CONN. Audio SPK conn IDT 92HD81B1B Camera FLASH 2Mbyts USB2.0 PCIEx1 FAN / THERMAL FAN G990P11U PG 4,5,6,7 PG 8,9,10,11,12,13 PG 21 PG21 PG 29 PG 29 PG 24 PG 25 PG 23 PG 22 PG 22 PG 30 PG 30 PG 20 PG 20 PG 20 PG 19 PG 19 PG 27 PG 36 PG 38 PG 37 VGA Core PG 41 PG 40 PG 39 PG 34PG 35 PG 16 DDR3 - SODIMM0 DDR3 - SODIMM1 Dual Channel DDR3 800/1067 1.5V SLG8SP585V(QFN32) 14.318MHz CLOCK GEN PG 3 PG 31 PG 15 PG 14 82577LM +1.8V REGULATOR PG 41 Headphone Microphone 25MHz 32.768KHz Discrete+3V, +5V 01 PCIEx1 USB2.0 32.768KHz Biometric USB2.0 BluetoothUSB2.0 PG 28 PG 28 SPIFLASH 2Mbyts PG 9 Discharge PG 34 Ibex Peak-M Intel(R) 5 Series Express Chipset FDI CRT CONN. Panel Connector PG 16 PG 17 LPC SIO PG 30 USB+eSATA PG 23 Re-Driver PG 23 USB2.0 x 1 SATA LVDS VGA 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 A A B B C C D D Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 FRONTPAGE 1AA3 2 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 FRONTPAGE 1AA3 2 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 FRONTPAGE 1AA3 2 38Friday, October 23, 2009 PAGE DESCRIPTION 2 1 Ibex Peak-M Table of Contents Power States POWER PLANE +5V_ODD 3 4-7 16-22 24 25 26 27 28 30 5VSUS CONTROL SIGNAL 3VSUS +5V +3V +1.8V +1.05V_VTT +1.5V +3VRTC VCC_CORE Front Page 31 32 33 34 0.75VSMDDR_VTERM LCDVCC 37 RTL8111DL +1.05V_PCH USB X2/SIM_CARD/LEDs/RF USB x 2 & ESATA Audio Codec ALC269 35 Schematic Block Diagram CLOCK GENERATOR Auburndale CPU 8-13 14-15 DDRIII SO-DIMM Discreate VGA (M92-XT) HDMI Conn. CRT Conn. ONFI Express Card G-Sensor MINI-Card (UWB & WWAN) 38 B To B Conn.39 40 41 42 3V/5V (MAX17101) DDR3 (TPS5116REGR) SATA HDD & ODD 29 MINI-Card (WLAN) 36 1.05V_VTT & 1.05_PCH (RT8204) LANVCC DESCRIPTION ACTIVE INVOLTAGE PAGE VIN 3VPCU 5VPCU +15V 1.5VSUS +5V_HDD BAT-V 10V~+20V +3.0V~+3.3V +3.3V +3.3V +3.3V +3.3V +5V +5V +5V +5V +5V +15V +1.5V +1.8V +0.75V +1.5V +1.05V +1.05V +3.3V 23,32,43,44,45,46,47,48,49,50 9,12,41 9,23,27,30,32,35,39,41,43,44,47 14,43,44,45,46,47,49,50 23,38,43,45,46,47 27,43 23,39,43,48 14,15,30,34,41,43,49 4,6,14,15,43,45,46,49,50 14,15,43,45 12,18,23,24,25,26,28,35,37,41,43,44 3,4,8,9,10,11,12,14,15,17,23,25,26,27,28,29, 30,31,32,33,34,36,37,38,39,40,41,43,44,45,46 ,47,48,50,52 12,18,19,20,31,32,34,45,46 4,6,11,12,43,46,48,52 3,10,12,43,46,52 6,43,48 23 28 MAIN BATTERY+10V~+17V MAIN POWER RTC ITE8052 POWER LARGE POWER SLP_S3# CTRLD POWER SLP_S3# CTRLD POWER LAN POWER DC/DC POWER IC SOURCE SODIMM POWER Sys Management,PCH Resume Well,Intel HD Audio,USB,WLAN WiMAX POWER DDR3 SODIMM REFERENCE POWER LVDS,NVM POWER Mini PCIe,Express Card POWER CPU CORE POWER AuBurndale VTT POWER PCH CORE POWER HDD Power ODD Power LCD Power 3V5V_EN 3V5V_EN 3V5V_EN LAN_ON SUSON SUSON SUSON MAIN_ON MAIN_ON MAIN_ON MAIN_ON MAIN_ON 1.05V_RUN_ON VRON ENVDD MAIN_ON MAIN_ON CHG_PBATT S0~S5 S0~S5 S0~S5 S0~S5 S0~S523 LCD + Camera Conn. K/B & T/P BLUETOOTH FAN & Thermal 47 45 46 iTPM & RFID EEPROM KBC IT8502E 48 CPU (MAX17082) 28 6,12,17,18,21,22,33,43,50 Power Block Dianram51 DIS_1.8V_RUN (OZ8116LN)50 DIS_GFX_VCC (MAX8792)49 Charger44 43 Discharge HOLD & SKEW 02 +VCC_GFX_CORE 18,21,43,49+0.9V~+1.2V VGA CORE POWER MAIN_ON 53 54 Revision & Schematic Value Description BOM Matrix Table 52 XDP GFXVR_EN 3V_S5 +3.3V 8,9,10,11,12,43,52 S5_ON 5V_S5 +5V S5_ONPCH SUS POWER12,29,30,43 SLP_S4# CTRLD POWER SLP_S4# CTRLD POWER S0~S3 S0~S3 S0~S3 S0~S3 S0~S3 S0 S0 S0 S0 S0 S0 S0 S0 S0 S0 S0 S0 S0~S544 5 5 4 4 3 3 2 2 1 1 D D C C B B A A +CK_VDD_MAIN CLK_SDATA CLK_SCLK XTAL_IN CPU_SEL CK_PWRGD_R CLK_SCLK CLK_SDATA XTAL_IN XTAL_OUT XTAL_OUT CPU_SEL +CK_VDD_MAIN CK_PWRGD_R +CK_VDD_MAIN_1 CLK_ICH_14M(10) ICH_SMBCLK(10) ICH_SMBDATA(10) CLK_BUF_BCLK_P (10) CLK_BUF_BCLK_N (10) CLK_BUF_PCIE_3GPLL (10) CLK_BUF_PCIE_3GPLL# (10) CLK_BUF_DREFCLK (10) CLK_BUF_DREFCLK# (10) CLK_BUF_DREFSSCLK (10) CLK_BUF_DREFSSCLK# (10) CLK_SDATA (14,15) CLK_SCLK (14,15) VR_PWRGD_CLKEN#(36) +3V(4,6,8,9,10,11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36) +1.05V_VTT(4,6,8,9,10,11,12,18,30,31,34,36,37) CLK_SIO_14M(28) +1.5V +3V +3V +VDDIO_CLK +1.05V_VTT +3V +3V +VDDIO_CLK +3V +3V Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 Clock Generator 1ACustom 3 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 Clock Generator 1ACustom 3 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 Clock Generator 1ACustom 3 38Friday, October 23, 2009 Place the 22 ohm resistors close to the CK 505 Place each 0.1uF cap as close as possible to each VDD IO pin. Place the 10uF caps on the VDD_IO plane. CPU_SEL 0 1 CPU0/1=133MHz (default) CPU0/1=100MHz 03 EC-A-01 R97 *10K_4 R97 *10K_4 R87 10K_4 R87 10K_4 Q7 2N7002 Q7 2N7002 3 2 1 R86 10K_4 R86 10K_4 C158 30P/50V/NPO_4 C158 30P/50V/NPO_4 C151 0.1U/10V/X5R_4 C151 0.1U/10V/X5R_4 R82 HCB1608KF-181T15_6 R82 HCB1608KF-181T15_6 C162 0.1U/10V/X5R_4 C162 0.1U/10V/X5R_4 R100 1K_4 R100 1K_4 Q8 2N7002 Q8 2N7002 3 2 1 C164 10U/6.3V/X5R_8 C164 10U/6.3V/X5R_8 C157 30P/50V/NPO_4 C157 30P/50V/NPO_4 R81 HCB1608KF-181T15_6 R81 HCB1608KF-181T15_6 C161 0.1U/10V/X5R_4 C161 0.1U/10V/X5R_4 R83 *HCB1608KF-181T15_6 R83 *HCB1608KF-181T15_6 C171 10U/6.3V/X5R_8 C171 10U/6.3V/X5R_8 R92 10K_4 R92 10K_4 C149 *10P/50V/COG_4 C149 *10P/50V/COG_4 C144 0.1U/10V/X5R_4 C144 0.1U/10V/X5R_4 C143 10U/6.3V/X5R_8 C143 10U/6.3V/X5R_8 C145 0.1U/10V/X5R_4 C145 0.1U/10V/X5R_4 Q9 2N7002 Q9 2N7002 3 2 1 Y2 14.318MHZ Y2 14.318MHZ 21 L10 BLM21PG600SN1D 0805 L10 BLM21PG600SN1D 0805 R98 100K_4 R98 100K_4 C156 10U/6.3V/X5R_8 C156 10U/6.3V/X5R_8 C150 0.1U/10V/X5R_4 C150 0.1U/10V/X5R_4 C160 0.1U/10V/X5R_4 C160 0.1U/10V/X5R_4 R91 22_4R91 22_4 R89 22_4R89 22_4 C147 *10P/50V/COG_4 C147 *10P/50V/COG_4 R101 10K_4R101 10K_4 CK505 QFN32 U8 ICS9LRS3197AKLFT CK505 QFN32 U8 ICS9LRS3197AKLFT VDD_CPU_IO18 SRC-2 13 VDD_SRC_IO15 VSS_DOT2 27M_SS 7 DOT96# 4 SRC-1/SATA 10 SRC-1#/SATA 11 SRC-2# 14 27M 6 DOT96 3 VSS_CPU21 CPU-1 20 CPU-0# 22 CPU-0 23 VDD_275 VDD_SRC17 VDD_CPU24 VDD_DOT1 VSS_SATA9 VSS_SRC12 REF_0/CPU_SEL30 CPU_STOP#16 CPU-1# 19 VSS_REF26 VDD_REF29 XOUT27 XIN28 SCLK32 SDATA31 CK_PWRGD/PD#25 GND 33 VSS_278 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SM_RCOMP_2 SM_RCOMP_1 SM_RCOMP_0 CPUDRAMRST# H_COMP0 H_COMP1 H_COMP2 H_COMP3 TP_SKT0CC# H_CATERR# H_PROCHOT# H_VTTPWRGD PM_DRAM_PWRGD XDP_TDO_R XDP_TDI_R XDP_PREQ# XDP_TDO_M XDP_PRDY# XDP_TDI_M H_CPURST# H_PWRGD_XDP H_PROCHOT# H_CATERR# H_CPURST# SYS_AGENT_PWROK H_COMP2 H_COMP0 H_COMP3 H_COMP1 SM_RCOMP_1 SM_RCOMP_2 SM_RCOMP_0 H_VTTPWRGD SYS_AGENT_PWROK XDP_TCLK XDP_TMS XDP_TRST# PM_DRAM_PWRGD XDP_TDO_M XDP_TDI_M XDP_TDO_R XDP_TDI_R XDP_TRST# XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TMS FDI_TXN0 FDI_TXN5 FDI_TXN4 FDI_TXN3 FDI_TXN2 FDI_TXN1 FDI_TXP2 FDI_TXP1 FDI_TXP0 FDI_TXN7 FDI_TXN6 FDI_TXP7 FDI_TXP6 FDI_TXP5 FDI_TXP4 FDI_TXP3 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 FDI_INT XDP_TDO_M +1.5VCPU_PG +1.5VCPU_PG DRAMPWRGD_CPU CPUDRAMRST# PM_EXTTS#0 (14,15) PM_EXTTS#1 (15) CLK_PCIE_3GPLL# (10) CLK_CPU_BCLK# (11) H_PECI(11) PM_SYNC(8) PM_THRMTRIP#(11) PM_DRAM_PWRGD(8) XDP_DBRESET# (8) DELAY_VR_PWRGOOD(8,36) H_PWRGOOD(11) CLK_CPU_BCLK (11) DMI_TXN0(8) DMI_TXN1(8) DMI_TXN2(8) DMI_TXN3(8) DMI_TXP0(8) DMI_TXP1(8) DMI_TXP2(8) DMI_TXP3(8) DMI_RXN0(8) DMI_RXN1(8) DMI_RXN2(8) DMI_RXN3(8) DMI_RXP0(8) DMI_RXP1(8) DMI_RXP2(8) DMI_RXP3(8) HWPG(27,33,34,35,36,37) CLK_PCIE_3GPLL (10) PLTRST#(10,18,23,24,25,28) +1.05V_VTT(3,6,8,9,10,11,12,18,30,31,34,36,37) +3V(3,6,8,9,10,11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36) 1.5VSUS(14,15,31,33) H_PROCHOT#(36) FDI_TXN[7:0](8) FDI_TXP[7:0](8) FDI_FSYNC0(8) FDI_FSYNC1(8) FDI_LSYNC1(8) FDI_LSYNC0(8) FDI_INT(8) DREFSSCLK (10) DREFSSCLK# (10) 3VPCU(9,16,18,21,27,28,29,31,32,35,37) +1.5VCPU_PG (33) DRAMRST_CTRL_EC(27) DDR3_DRAMRST#(14,15) DRAMRST_CTRL_PCH(11) +1.05V_VTT +1.05V_VTT +3V +1.5VCPU +1.05V_VTT 3V_S5 3V_S5 +1.5VCPU 3V_S5 1.5VSUS Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 PROCESSER 1/4(HOST&PCIE) 1ACustom 4 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 PROCESSER 1/4(HOST&PCIE) 1ACustom 4 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 PROCESSER 1/4(HOST&PCIE) 1ACustom 4 38Friday, October 23, 2009 AUBURNDALE PROCESSOR (DMI,PEG,FDI) Processor Pullups Processor Compensation Signals DDR3 Compensation Signals Layout Note: Place these resistors near Processor 04 R80 R84 STUFF STUFF NO_STUFF NO_STUFF Platform REFDES ERB CRB JTAG MAPPING Scan Chain (Default) CPU Only GMCH Only STUFF -> R421, R411, R422 NO STUFF -> R430, R429 STUFF -> R421, R430 NO STUFF -> R411, R429, R422 STUFF -> R429, R422 NO STUFF -> R421, R430, R411 For Calpella S3 power reduction For Calpella S3 power reduction For Calpella S3 power reduction For Calpella S3 power reduction EC-A-02 EC-A-02EC-A-02 EC-A-02 R333 *0_4R333 *0_4 TP10TP10 R328 *0_4R328 *0_4 R331 20/F_4 R331 20/F_4 U5 74AHCT1G08GW U5 74AHCT1G08GW 2 1 4 3 5 TP9TP9 TP18TP18 R51 10K_4R51 10K_4 TP11TP11 Q31 ME2N7002E Q31 ME2N7002E 3 2 1 TP43TP43 R31 49.9/F_4 R31 49.9/F_4 R436 10K_4 R436 10K_4 P C I E X P R E S S - - G R A P H I C S D M I I nt el( R) F D I U20A IC,AUB_CFD_rPGA,R0P9 P C I E X P R E S S - - G R A P H I C S D M I I nt el( R) F D I U20A IC,AUB_CFD_rPGA,R0P9 DMI_RX#[0]A24 DMI_RX#[1]C23 DMI_RX#[2]B22 DMI_RX#[3]A21 DMI_RX[0]B24 DMI_RX[1]D23 DMI_RX[2]B23 DMI_RX[3]A22 DMI_TX#[0]D24 DMI_TX#[1]G24 DMI_TX#[2]F23 DMI_TX#[3]H23 DMI_TX[0]D25 DMI_TX[1]F24 DMI_TX[3]G23 DMI_TX[2]E23 FDI_TX#[0]E22 FDI_TX#[1]D21 FDI_TX#[2]D19 FDI_TX#[3]D18 FDI_TX#[4]G21 FDI_TX#[5]E19 FDI_TX#[6]F21 FDI_TX#[7]G18 FDI_TX[0]D22 FDI_TX[1]C21 FDI_TX[2]D20 FDI_TX[3]C18 FDI_TX[4]G22 FDI_TX[5]E20 FDI_TX[6]F20 FDI_TX[7]G19 FDI_FSYNC[0]F17 FDI_FSYNC[1]E17 FDI_INTC17 FDI_LSYNC[0]F18 FDI_LSYNC[1]D17 PEG_ICOMPI B26 PEG_ICOMPO A26 PEG_RBIAS A25 PEG_RCOMPO B27 PEG_RX#[0] K35 PEG_RX#[1] J34 PEG_RX#[2] J33 PEG_RX#[3] G35 PEG_RX#[4] G32 PEG_RX#[5] F34 PEG_RX#[6] F31 PEG_RX#[7] D35 PEG_RX#[8] E33 PEG_RX#[9] C33 PEG_RX#[10] D32 PEG_RX#[11] B32 PEG_RX#[12] C31 PEG_RX#[13] B28 PEG_RX#[14] B30 PEG_RX#[15] A31 PEG_RX[0] J35 PEG_RX[1] H34 PEG_RX[2] H33 PEG_RX[3] F35 PEG_RX[4] G33 PEG_RX[5] E34 PEG_RX[6] F32 PEG_RX[7] D34 PEG_RX[8] F33 PEG_RX[9] B33 PEG_RX[10] D31 PEG_RX[11] A32 PEG_RX[12] C30 PEG_RX[13] A28 PEG_RX[14] B29 PEG_RX[15] A30 PEG_TX#[0] L33 PEG_TX#[1] M35 PEG_TX#[2] M33 PEG_TX#[3] M30 PEG_TX#[4] L31 PEG_TX#[5] K32 PEG_TX#[6] M29 PEG_TX#[7] J31 PEG_TX#[8] K29 PEG_TX#[9] H30 PEG_TX#[10] H29 PEG_TX#[11] F29 PEG_TX#[12] E28 PEG_TX#[13] D29 PEG_TX#[14] D27 PEG_TX#[15] C26 PEG_TX[0] L34 PEG_TX[1] M34 PEG_TX[2] M32 PEG_TX[3] L30 PEG_TX[4] M31 PEG_TX[5] K31 PEG_TX[6] M28 PEG_TX[7] H31 PEG_TX[8] K28 PEG_TX[9] G30 PEG_TX[10] G29 PEG_TX[11] F28 PEG_TX[12] E27 PEG_TX[13] D28 PEG_TX[14] C27 PEG_TX[15] C25 R61 *68_4 R61 *68_4 R57 *0_4_shortR57 *0_4_short R43 750/F_4 R43 750/F_4 R23 49.9/F_4 R23 49.9/F_4 R60 *51_4R60 *51_4 TP48TP48 R302 49.9/F_4R302 49.9/F_4 Q32 PDTC143TT Q32 PDTC143TT 1 3 2 R435 8.2K_4R435 8.2K_4 TP12TP12 R434 *0_4R434 *0_4 R318 51_4 R318 51_4 TP16TP16 C481 470p/50V_4 C481 470p/50V_4 R430 1.5K/F_4R430 1.5K/F_4 R50 10K_4R50 10K_4 R56 *0_4_shortR56 *0_4_short R432 1K_4 R432 1K_4 TP4TP4 TP15TP15 R52 1.5K/F_4R52 1.5K/F_4 R45 750/F_4 R45 750/F_4 R54 *0_4R54 *0_4 C480 1U/6.3V/X5R_4 C480 1U/6.3V/X5R_4 R41 1K_4 R41 1K_4 TP17TP17 TP50TP50 R437 *0_4R437 *0_4 TP51TP51 R308 24.9/F_4 R308 24.9/F_4 TP6TP6 R327 *0_4R327 *0_4 R44 2K/F_4R44 2K/F_4 TP14TP14 TP47TP47 R309 130/F_4 R309 130/F_4 R334 *0_4R334 *0_4R439 *0_4_shortR439 *0_4_short R53 *1.1K/F_4 R53 *1.1K/F_4 R330 20/F_4 R330 20/F_4 R329 49.9/F_4 R329 49.9/F_4 TP8TP8 R317 *0_4_short R317 *0_4_short R433 10K_4 R433 10K_4 R307 100/F_4 R307 100/F_4 C L O C K S M ISC T H E R M A L P W R M A N AG E M E N T D D R 3 M I S C J T A G & B P M U20B IC,AUB_CFD_rPGA,R0P9 C L O C K S M ISC T H E R M A L P W R M A N AG E M E N T D D R 3 M I S C J T A G & B P M U20B IC,AUB_CFD_rPGA,R0P9 SM_RCOMP[1] AM1 SM_RCOMP[2] AN1 SM_DRAMRST# F6 SM_RCOMP[0] AL1 BCLK# B16 BCLK A16 BCLK_ITP# AT30 BCLK_ITP AR30 PEG_CLK# D16 PEG_CLK E16 DPLL_REF_SSCLK# A17 DPLL_REF_SSCLK A18 CATERR#AK14 COMP3AT23 PECIAT15 PROCHOT#AN26 THERMTRIP#AK15 RESET_OBS#AP26 VCCPWRGOOD_1AN14 VCCPWRGOOD_0AN27 SM_DRAMPWROKAK13 VTTPWRGOODAM15 RSTIN#AL14 PM_EXT_TS#[0] AN15 PM_EXT_TS#[1] AP15 PRDY# AT28 PREQ# AP27 TCK AN28 TMS AP28 TRST# AT27 TDI AT29 TDO AR27 TDI_M AR29 TDO_M AP29 DBR# AN25 BPM#[0] AJ22 BPM#[1] AK22 BPM#[2] AK24 BPM#[3] AJ24 BPM#[4] AJ25 BPM#[5] AH22 BPM#[6] AK23 BPM#[7] AH23 COMP2AT24 PM_SYNCAL15 TAPPWRGOODAM26 COMP1G16 COMP0AT26 SKTOCC#AH24 TP5TP5 U32 TC7SH08FU(F) U32 TC7SH08FU(F) 1 2 4 5 3 R48 68_4 R48 68_4 TP49TP49 TP44TP44 C479 0.1U/10V/X7R_4 C479 0.1U/10V/X7R_4 R62 *0_4_shortR62 *0_4_short R326 *51_4R326 *51_4 R59 *51_4R59 *51_4 R47 *51_4R47 *51_4 TP46TP46 Q30 MMBT3904 Q30 MMBT3904 2 1 3 R335 51_4R335 51_4 R431 10K_4 R431 10K_4 TP7TP7 R438 100K_4 R438 100K_4 TP13TP13 R303 750/F_4R303 750/F_4 5 5 4 4 3 3 2 2 1 1 D D C C B B A A M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ10 M_A_DQ11 M_A_DQ13 M_A_DQ12 M_A_DQ14 M_A_DQ15 M_A_DQ8 M_A_DQ9 M_A_DQ18 M_A_DQ19 M_A_DQ21 M_A_DQ20 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ31 M_A_DQ30 M_A_DQ28 M_A_DQ29 M_A_DQ27 M_A_DQ26 M_A_DQ25 M_A_DQ16 M_A_DQ17 M_A_DQ34 M_A_DQ35 M_A_DQ37 M_A_DQ36 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ47 M_A_DQ46 M_A_DQ44 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ41 M_A_DQ32 M_A_DQ54 M_A_DQ52 M_A_DQ53 M_A_DQ51 M_A_DQ50 M_A_DQ58 M_A_DQ59 M_A_DQ61 M_A_DQ60 M_A_DQ62 M_A_DQ63 M_A_DQ56 M_A_DQ55 M_A_DQ49 M_A_DQ48 M_A_DQ57 M_A_DQ33 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ6 M_B_DQ7 M_B_DQ4 M_B_DQ5 M_B_DQ10 M_B_DQ11 M_B_DQ13 M_B_DQ12 M_B_DQ15 M_B_DQ14 M_B_DQ8 M_B_DQ9 M_B_DQ18 M_B_DQ19 M_B_DQ21 M_B_DQ20 M_B_DQ23 M_B_DQ22 M_B_DQ16 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ28 M_B_DQ29 M_B_DQ27 M_B_DQ26 M_B_DQ17 M_B_DQ34 M_B_DQ35 M_B_DQ37 M_B_DQ36 M_B_DQ39 M_B_DQ38 M_B_DQ32 M_B_DQ41 M_B_DQ40 M_B_DQ46 M_B_DQ47 M_B_DQ44 M_B_DQ45 M_B_DQ43 M_B_DQ42 M_B_DQ33 M_B_DQ53 M_B_DQ51 M_B_DQ50 M_B_DQ63 M_B_DQ62 M_B_DQ56 M_B_DQ57 M_B_DQ48 M_B_DQ54 M_B_DQ55 M_B_DQ52 M_B_DQ49 M_B_DQ58 M_B_DQ59 M_B_DQ61 M_B_DQ60 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A5 M_A_A6 M_A_A7 M_A_A4 M_A_A9 M_A_A10 M_A_A11 M_A_A8 M_A_A12 M_A_A15 M_A_A14 M_A_A13 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS0 M_A_DQS4 M_A_DQS6 M_A_DQS5 M_A_DQS7 M_A_DQS#1 M_A_DQS#0 M_A_DQS#3 M_A_DQS#2 M_A_DQS#5 M_A_DQS#6 M_A_DQS#4 M_A_DQS#7 M_A_DM1 M_A_DM0 M_A_DM3 M_A_DM2 M_A_DM5 M_A_DM6 M_A_DM4 M_A_DM7 M_B_DM1 M_B_DM0 M_B_DM3 M_B_DM2 M_B_DM5 M_B_DM6 M_B_DM4 M_B_DM7 M_B_DQS#1 M_B_DQS#0 M_B_DQS#3 M_B_DQS#2 M_B_DQS#5 M_B_DQS#6 M_B_DQS#4 M_B_DQS#7 M_B_DQS1 M_B_DQS0 M_B_DQS3 M_B_DQS2 M_B_DQS5 M_B_DQS6 M_B_DQS4 M_B_DQS7 M_B_A1 M_B_A9 M_B_A10 M_B_A11 M_B_A8 M_B_A12 M_B_A15 M_B_A14 M_B_A13 M_B_A2 M_B_A3 M_B_A0 M_B_A5 M_B_A6 M_B_A7 M_B_A4 M_B_DQ[63:0](15) M_A_DM[7:0] (14) M_A_A[15:0] (14) M_A_DQS[7:0] (14) M_A_DQS#[7:0] (14) M_A_DQ[63:0](14) M_A_CLK0 (14) M_A_CLK0# (14) M_A_CKE0 (14) M_A_CLK1# (14) M_A_CKE1 (14) M_A_CLK1 (14) M_A_CS#0 (14) M_A_ODT0 (14) M_A_CS#1 (14) M_A_ODT1 (14) M_B_ODT1 (15) M_B_CLK0# (15) M_B_CS#0 (15) M_B_ODT0 (15) M_B_CKE0 (15) M_B_CLK0 (15) M_B_CS#1 (15) M_B_CLK1# (15) M_B_CKE1 (15) M_B_CLK1 (15) M_B_DM[7:0] (15) M_B_A[15:0] (15) M_B_DQS#[7:0] (15) M_B_DQS[7:0] (15) M_A_BS#0(14) M_A_WE#(14) M_A_RAS#(14) M_A_BS#1(14) M_A_BS#2(14) M_A_CAS#(14) M_B_BS#1(15) M_B_BS#2(15) M_B_WE#(15) M_B_RAS#(15) M_B_CAS#(15) M_B_BS#0(15) Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 PROCESSER 2/4(DDR) 1ACustom 5 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 PROCESSER 2/4(DDR) 1ACustom 5 38Friday, October 23, 2009 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : LL5 PROCESSER 2/4(DDR) 1ACustom 5 38Friday, October 23, 2009 AUBURNDALE PROCESSOR (DDR3) 05 D D R S Y S T E M M E M O R Y A U20C IC,AUB_CFD_rPGA,R0P9 D D R S Y S T E M M E M O R Y A U20C IC,AUB_CFD_rPGA,R0P9 SA_BS[0]AC3 SA_BS[1]AB2 SA_BS[2]U7 SA_CAS#AE1 SA_RAS#AB3 SA_WE#AE9 SA_CK[0] AA6 SA_CK[1] Y6 SA_CK#[0] AA7 SA_CK#[1] Y5 SA_CKE[0] P7 SA_CKE[1] P6 SA_CS#[0] AE2 SA_CS#[1] AE8 SA_ODT[0] AD8 SA_ODT[1] AF9 SA_DM[0] B9 SA_DM[1] D7 SA_DM[2] H7 SA_DM[3] M7 SA_DM[4] AG6 SA_DM[5] AM7 SA_DM[6] AN10 SA_DM[7] AN13 SA_DQS[0] C8 SA_DQS#[0] C9 SA_DQS[1] F9 SA_DQS#[1] F8 SA_DQS[2] H9 SA_DQS#[2] J9 SA_DQS[3] M9 SA_DQS#[3] N9 SA_DQS[4] AH8 SA_DQS#[4] AH7 SA_DQS[5] AK10 SA_DQS#[5] AK9 SA_DQS[6] AN11 SA_DQS#[6] AP11 SA_DQS[7] AR13 SA_DQS#[7] AT13 SA_MA[0] Y3 SA_MA[1] W1 SA_MA[2] AA8 SA_MA[3] AA3 SA_MA[4] V1 SA_MA[5] AA9 SA_MA[6] V8 SA_MA[7] T1 SA_MA[8] Y9 SA_MA[9] U6 SA_MA[10] AD4 SA_MA[11] T2 SA_MA[12] U3 SA_MA[13] AG8 SA_MA[14] T3 SA_MA[15] V9 SA_DQ[0]A10 SA_DQ[1]C10 SA_DQ[2]C7 SA_DQ[3]A7 SA_DQ[4]B10 SA_DQ[5]D10 SA_DQ[6]E10 SA_DQ[7]A8 SA_DQ[8]D8 SA_DQ[9]F10 SA_DQ[10]E6 SA_DQ[11]F7 SA_DQ[12]E9 SA_DQ[13]B7 SA_DQ[14]E7 SA_DQ[15]C6 SA_DQ[16]H10 SA_DQ[17]G8 SA_DQ[18]K7 SA_DQ[19]J8 SA_DQ[20]G7 SA_DQ[21]G10 SA_DQ[22]J7 SA_DQ[23]J10 SA_DQ[24]L7 SA_DQ[25]M6 SA_DQ[26]M8 SA_DQ[27]L9 SA_DQ[28]L6 SA_DQ[29]K8 SA_DQ[30]N8 SA_DQ[31]P9 SA_DQ[32]AH5 SA_DQ[33]AF5 SA_DQ[34]AK6 SA_DQ[35]AK7 SA_DQ[36]AF6 SA_DQ[37]AG5 SA_DQ[38]AJ7 SA_DQ[39]AJ6 SA_DQ[40]AJ10 SA_DQ[41]AJ9 SA_DQ[42]AL10 SA_DQ[43]AK12 SA_DQ[44]AK8 SA_DQ[45]AL7 SA_DQ[46]AK11 SA_DQ[47]AL8 SA_DQ[48]AN8 SA_DQ[49]AM10 SA_DQ[50]AR11 SA_DQ[51]AL11 SA_DQ[52]AM9 SA_DQ[53]AN9 SA_DQ[54]AT11 SA_DQ[55]AP12 SA_DQ[56]AM12 SA_DQ[57]AN12 SA_DQ[58]AM13 SA_DQ[59]AT14 SA_DQ[60]AT12 SA_DQ[61]AL13 SA_DQ[62]AR14 SA_DQ[63]AP14 D D R S Y S T E M M E M O R Y - B U20D IC,AUB_CFD_rPGA,R0P9 D D R S Y S T E M M E M O R Y - B U20D IC,AUB_CFD_r