The Hashemite University
Electrical Engineering Department
Dr. Anas Al Tarabsheh Digital Electronics Date: 27/04/2009
Second Exam Second Semester 2008/2009 Exam Duration: 1 hour
Q1) Fig. 1 shows a combines a Schottky BJT (Q1) with an ECL gate.
The normal transistors have: βF =50, VBE (F.A)= 0.75V,VBE (ECL)= 0.75V.
The Schottky transistor has: ( ) VV HARDONCE 5.0=− and ( ) VV HARDONBE 8.0=−
A) If the gate is driven by a similar gate, VVV HOUTHIN 2.4,, =≅ , and
V . When 3Q is conducting then the current mA2VV LOUTLIN 0,, =≅ I RE = .
Determine the right values of 3R and 4R .
B) When 3Q is not conducting, calculate the values of 2EI and 2BV .
C) When the input voltage is at high state with mAI B 11 = , determine 1R and 2R
to hold 2BV at V6.1 .
1
Q2) Fig. 2 shows the circuit and the corresponding load line and characteristics
of a resistor loaded NMOS inverter. The NMOS inverter operates at the
edge-of-saturation (EOS) as shown in Fig.2 b.
2.1) Determine the threshold voltage of the NMOS, . TNV
2.2) Determine the conduction parameter of the NMOS, nK
2.3) Calculate and DDV LR
2.4) Find the dissipated-power in the NMOS only.
2.5) Does the decrease of move the operating point toward the
saturation region? Explain.
INV
2
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