Architecture of FPGAs and CPLDs A Tutorial

Architecture of FPGAs and CPLDs: A Tutorial Stephen Brown and Jonathan Rose Department of Electrical and Computer Engineering University of Toronto email: brown | jayar@eecg.toronto.edu Abstract This paper provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs). We first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips, and give examples of applications of each type of device. Page 2 of 41 1 Introduction to High-Capacity FPDs Prompted by the development of new types of sophisticated field-programmable devices (FPDs), the process of designing digital hardware has changed dramatically over the past few years. Unlike previous generations of technology, in which board-level designs included large numbers of SSI chips containing basic gates, virtually every digital design produced today consists mostly of high-density devices. This applies not only to custom devices like processors and memory, but also for logic circuits such as state machine controllers, counters, registers, and decoders. When such circuits are destined for high-volume systems they have been integrated into high-density gate arrays. However, gate array NRE costs often are too expensive and gate arrays take too long to manufacture to be viable for prototyping or other low-volume scenarios. For these reasons, most prototypes, and also many production designs are now built using FPDs. The most compel- ling advantages of FPDs are instant manufacturing turnaround, low start-up costs, low financial risk and (since programming is done by the end user) ease of design changes. The market for FPDs has grown dramatically over the past decade to the point where there is now a wide assortment of devices to choose from. A designer today faces a daunting task to research the different types of chips, understand what they can best be used for, choose a particu- lar manufacturers’s product, learn the intricacies of vendor-specific software and then design the hardware. Confusion for designers is exacerbated by not only the sheer number of FPDs avail- able, but also by the complexity of the more sophisticated devices. The purpose of this paper is to provide an overview of the architecture of the various types of FPDs. The emphasis is on devices with relatively high logic capacity; all of the most important commercial products are discussed. Before proceeding, we provide definitions of the terminology in this field. This is necessary because the technical jargon has become somewhat inconsistent over the past few years as compa- nies have attempted to compare and contrast their products in literature. Page 3 of 41 1.1 Definitions of Relevant Terminology The most important terminology used in this paper is defined below. • Field-Programmable Device (FPD) — a general term that refers to any type of integrated cir- cuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured “in-system”. Another name for FPDs is programmable logic devices (PLDs); although PLDs encompass the same types of chips as FPDs, we prefer the term FPD because historically the word PLD has referred to rela- tively simple types of devices. • PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable (note: although PLA structures are sometimes embedded into full-custom chips, we refer here only to those PLAs that are provided as separate integrated circuits and are user-programmable). • PAL* — a Programmable Array Logic (PAL) is a relatively small FPD that has a programma- ble AND-plane followed by a fixed OR-plane • SPLD — refers to any type of Simple PLD, usually either a PLA or PAL • CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. Alternative names (that will not be used in this paper) sometimes adopted for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others. • FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer more narrow logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs. • HCPLDs — high-capacity PLDs: a single acronym that refers to both CPLDs and FPGAs. This term has been coined in trade literature for providing an easy way to refer to both types of devices. We do not use this term in the paper. * PAL is a trademark of Advanced Micro Devices. Page 4 of 41 • Interconnect — the wiring resources in an FPD. • Programmable Switch — a user-programmable switch that can connect a logic element to an interconnect wire, or one interconnect wire to another • Logic Block — a relatively small circuit block that is replicated in an array in an FPD. When a circuit is implemented in an FPD, it is first decomposed into smaller sub-circuits that can each be mapped into a logic block. The term logic block is mostly used in the context of FPGAs, but it could also refer to a block of circuitry in a CPLD. • Logic Capacity — the amount of digital logic that can be mapped into a single FPD. This is usually measured in units of “equivalent number of gates in a traditional gate array”. In other words, the capacity of an FPD is measured by the size of gate array that it is comparable to. In simpler terms, logic capacity can be thought of as “number of 2-input NAND gates”. • Logic Density — the amount of logic per unit area in an FPD. • Speed-Performance — measures the maximum operable speed of a circuit when implemented in an FPD. For combinational circuits, it is set by the longest delay through any path, and for sequential circuits it is the maximum clock frequency for which the circuit functions properly. In the remainder of this section, to provide insight into FPD development the evolution of FPDs over the past two decades is described. Additional background information is also included on the semiconductor technologies used in the manufacture of FPDs. 1.2 Evolution of Programmable Logic Devices The first type of user-programmable chip that could implement logic circuits was the Programma- ble Read-Only Memory (PROM), in which address lines can be used as logic circuit inputs and data lines as outputs. Logic functions, however, rarely require more than a few product terms, and a PROM contains a full decoder for its address inputs. PROMS are thus an inefficient architecture for realizing logic circuits, and so are rarely used in practice for that purpose. The first device developed later specifically for implementing logic circuits was the Field-Programmable Logic Array (FPLA), or simply PLA for short. A PLA consists of two levels of logic gates: a program- Page 5 of 41 mable “wired” AND-plane followed by a programmable “wired” OR-plane. A PLA is structured so that any of its inputs (or their complements) can be AND’ed together in the AND-plane; each AND-plane output can thus correspond to any product term of the inputs. Similarly, each OR- plane output can be configured to produce the logical sum of any of the AND-plane outputs. With this structure, PLAs are well-suited for implementing logic functions in sum-of-products form. They are also quite versatile, since both the AND terms and OR terms can have many inputs (this feature is often referred to as wide AND and OR gates). When PLAs were introduced in the early 1970s, by Philips, their main drawbacks were that they were expensive to manufacture and offered somewhat poor speed-performance. Both disad- vantages were due to the two levels of configurable logic, because programmable logic planes were difficult to manufacture and introduced significant propagation delays. To overcome these weaknesses, Programmable Array Logic (PAL) devices were developed. As Figure 1 illustrates, PALs feature only a single level of programmability, consisting of a programmable “wired” AND- plane that feeds fixed OR-gates. To compensate for lack of generality incurred because the OR- Outputs� Plane AND � Inputs & Flip−flop feedbacks D D D D D D Figure 1 - Structure of a PAL. Page 6 of 41 plane is fixed, several variants of PALs are produced, with different numbers of inputs and out- puts, and various sizes of OR-gates. PALs usually contain flip-flops connected to the OR-gate out- puts so that sequential circuits can be realized. PAL devices are important because when introduced they had a profound effect on digital hardware design, and also they are the basis for some of the newer, more sophisticated architectures that will be described shortly. Variants of the basic PAL architecture are featured in several other products known by different acronyms. All small PLDs, including PLAs, PALs, and PAL-like devices are grouped into a single category called Simple PLDs (SPLDs), whose most important characteristics are low cost and very high pin-to-pin speed-performance. As technology has advanced, it has become possible to produce devices with higher capacity than SPLDs. The difficulty with increasing capacity of a strict SPLD architecture is that the struc- ture of the programmable logic-planes grow too quickly in size as the number of inputs is increased. The only feasible way to provide large capacity devices based on SPLD architectures is then to integrate multiple SPLDs onto a single chip and provide interconnect to programmably connect the SPLD blocks together. Many commercial FPD products exist on the market today with this basic structure, and are collectively referred to as Complex PLDs (CPLDs). CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs, and then in three additional series, called MAX 5000, MAX 7000 and MAX 9000. Because of a rapidly growing market for large FPDs, other manufacturers developed devices in the CPLD category and there are now many choices available. All of the most important commercial products will be described in Section 2. CPLDs provide logic capacity up to the equivalent of about 50 typical SPLD devices, but it is somewhat difficult to extend these architectures to higher densities. To build FPDs with very high logic capacity, a different approach is needed. Page 7 of 41 The highest capacity general purpose logic chips available today are the traditional gate arrays sometimes referred to as Mask-Programmable Gate Arrays (MPGAs). MPGAs consist of an array of pre-fabricated transistors that can be customized into the user’s logic circuit by connecting the transistors with custom wires. Customization is performed during chip fabrication by specifying the metal interconnect, and this means that in order for a user to employ an MPGA a large setup cost is involved and manufacturing time is long. Although MPGAs are clearly not FPDs, they are mentioned here because they motivated the design of the user-programmable equivalent: Field- Programmable Gate Arrays (FPGAs). Like MPGAs, FPGAs comprise an array of uncommitted circuit elements, called logic blocks, and interconnect resources, but FPGA configuration is per- formed through programming by the end user. An illustration of a typical FPGA architecture appears in Figure 2. As the only type of FPD that supports very high logic capacity, FPGAs have been responsible for a major shift in the way digital circuits are designed. Figure 2 - Structure of an FPGA. Block Logic I/O Block Page 8 of 41 Figure 3 summarizes the categories of FPDs by listing the logic capacities available in each of the three categories. In the figure, “equivalent gates” refers loosely to “number of 2-input NAND gates”. The chart serves as a guide for selecting a specific device for a given application, depend- ing on the logic capacity needed. However, as we will discuss shortly, each type of FPD is inher- ently better suited for some applications than for others. It should also be mentioned that there exist other special-purpose devices optimized for specific applications (e.g. state machines, ana- log gate arrays, large interconnection problems). However, since use of such devices is limited they will not be described here. The next sub-section discusses the methods used to implement the user-programmable switches that are the key to the user-customization of FPDs. 1.3 User-Programmable Switch Technologies The first type of user-programmable switch developed was the fuse used in PLAs. Although fuses are still used in some smaller devices, we will not discuss them here because they are quickly being replaced by newer technology. For higher density devices, where CMOS dominates the IC industry, different approaches to implementing programmable switches have been developed. For CPLDs the main switch technologies (in commercial products) are floating gate transistors like Figure 3 - FPD Categories by Logic Capacity. 1000 200� 2000� 20000� Equivalent Gates� SPLDs� CPLDs� FPGAs 12000 5000 40000 ** * *** Legend ** * *** Altera MAX 9000 Altera FLEX 10000, AT&T ORCA 2 Altera MAX 7000, AMD Mach, Lattice (p)LSI, Cypress FLASH370, Xilinx XC9500 Page 9 of 41 those used in EPROM and EEPROM, and for FPGAs they are SRAM and antifuse. Each of these is briefly discussed below. An EEPROM or EPROM transistor is used as a programmable switch for CPLDs (and also for many SPLDs) by placing the transistor between two wires in a way that facilitates implemen- tation of wired-AND functions. This is illustrated in Figure 4, which shows EPROM transistors as they might be connected in an AND-plane of a CPLD. An input to the AND-plane can drive a product wire to logic level ‘0’ through an EPROM transistor, if that input is part of the corre- sponding product term. For inputs that are not involved for a product term, the appropriate EPROM transistors are programmed to be permanently turned off. A diagram for an EEPROM- based device would look similar. Although there is no technical reason why EPROM or EEPROM could not be applied to FPGAs, current commercial FPGA products are based either on SRAM or antifuse technologies, as discussed below. An example of usage of SRAM-controlled switches is illustrated in Figure 5, showing two applications of SRAM cells: for controlling the gate nodes of pass-transistor switches and to con- +5 V EPROM input wire� EPROM input wire� product wire Figure 4 - EPROM Programmable Switches. Page 10 of 41 trol the select lines of multiplexers that drive logic block inputs. The figures gives an example of the connection of one logic block (represented by the AND-gate in the upper left corner) to another through two pass-transistor switches, and then a multiplexer, all controlled by SRAM cells. Whether an FPGA uses pass-transistors or multiplexers or both depends on the particular product. The other type of programmable switch used in FPGAs is the antifuse. Antifuses are origi- nally open-circuits and take on low resistance only when programmed. Antifuses are suitable for FPGAs because they can be built using modified CMOS technology. As an example, Actel’s anti- fuse structure, known as PLICE [Ham88], is depicted in Figure 6. The figure shows that an anti- fuse is positioned between two interconnect wires and physically consists of three sandwiched layers: the top and bottom layers are conductors, and the middle layer is an insulator. When unprogrammed, the insulator isolates the top and bottom layers, but when programmed the insula- tor changes to become a low-resistance link. PLICE uses Poly-Si and n+ diffusion as conductors SRAM� Logic Cell Logic Cell Logic CellLogic Cell SRAM� SRAM� Figure 5 - SRAM-controlled Programmable Switches. Page 11 of 41 and ONO (see [Ham88]) as an insulator, but other antifuses rely on metal for conductors, with amorphous silicon as the middle layer [Birk92][Marp94]. Table 1 lists the most important characteristics of the programming technologies discussed in this section. The left-most column of the table indicates whether the programmable switches are one-time programmable (OTP), or can be re-programmed (RP). The next column lists whether the switches are volatile, and the last column names the underlying transistor technology. Name Re-programmable Volatile Technology Fuse no no Bipolar EPROM yes out of circuit no UVCMOS EEPROM yes in circuit no EECMOS SRAM yes in circuit yes CMOS Antifuse no no CMOS+ Table 1 - Summary of Programming Technologies. silicon substrate n+ diffision dielectric � oxide Poly−Siwire wire antifuse Figure 6 - Actel Antifuse Structure. Page 12 of 41 1.4 Computer Aided Design (CAD) Flow for FPDs When designing circuits for implementation in FPDs, it is essential to employ Computer-Aided Design (CAD) programs. Such software tools are discussed briefly in this section to provide a feel for the design process involved. CAD tools are important not only for complex devices like CPLDs and FPGAs, but also for SPLDs. A typical CAD system for SPLDs would include software for the following tasks: initial design entry, logic optimization, device fitting, simulation, and configuration. This design flow is illustrated in Figure 7, which also indicates how some stages feed back to others. Design entry may be done either by creating a schematic diagram with a graphical CAD tool, by using a text- based system to describe a design in a simple hardware description language, or with a mixture of design entry methods. Since initial logic entry is not usually in an optimized form, algorithms are employed to optimize the circuits, after which additional algorithms analyse the resulting logic equations and “fit” them into the SPLD. Simulation is used to verify correct operation, and the user would return to the design entry step to fix errors. When a design simulates correctly it can be loaded into a programming unit and used to configure an SPLD. One final detail to note about Fig- ure 7 is that while the original design entry step is performed manually by the designer, all other steps are carried out automatically by most CAD systems. schematic capture text entry simulateSPLD fix errors configuration file manual automatic merge & translate optimize equations device fitter Figure 7 - CAD Design Flow for SPLDs. Programming Unit Page 13 of 41 The steps involved for implementing circuits in CPLDs are similar to those for SPLDs, but the tools themselves are more sophisticated. Because the devices are complex and can accommodate large designs, it is more common to use a mixture of design entry methods for different modules of a complete circuit. For instance, some modules might be designed with a small hardware description language like ABEL, others drawn using a symbolic schematic capture tool, and still others described via a full-featured hardware description language such as VHDL. Also, for CPLDs the process of “fitting” a design may require steps similar to those described below for FPGAs, depending on how sophisticated the CPLD is. The necessary software for these tasks is supplied either by the CPLD manufacturer or a third party. The design process for FPGAs is similar to that for CPLDs, but additional tools are needed to support the increased complexity of the chips. The major difference is in the “devic