January 2012 Altera Corporation
C51014-4.0 Datasheet
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Serial Configuration (EPCS) Devices
Datasheet
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This datasheet describes serial configuration (EPCS) devices.
Supported Devices
Table 1 lists the supported Altera EPCS devices.
f For more information about programming EPCS devices using the Altera
Programming Unit (APU) or Master Programming Unit (MPU), refer to the Altera
Programming Hardware Datasheet.
f The EPCS device can be re-programmed in system with ByteBlaster II download
cable or an external microprocessor using SRunner. For more information, refer to
AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming.
Features
EPCS devices offer the following features:
■ Supports active serial (AS) x1 configuration scheme
■ Easy-to-use four-pin interface
■ Low cost, low pin count, and non-volatile memory
■ Low current during configuration and near-zero standby mode current
■ 2.7-V to 3.6-V operation
■ EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated
circuit (SOIC) package
■ EPCS64 and EPCS128 devices available in 16-pin SOIC package
Table 1. Altera EPCS Devices
Device Memory Size (bits)
On-Chip
Decompression
Support
ISP Support Cascading Support Reprogrammable
Recommended
Operating
Voltage (V)
EPCS1 1,048,576 No Yes No Yes 3.3
EPCS4 4,194,304 No Yes No Yes 3.3
EPCS16 16,777,216 No Yes No Yes 3.3
EPCS64 67,108,864 No Yes No Yes 3.3
EPCS128 134,217,728 No Yes No Yes 3.3
Page 2 Functional Description
■ Enables the Nios processor to access unused flash memory through AS memory
interface
■ Reprogrammable memory with more than 100,000 erase or program cycles
■ Write protection support for memory sectors using status register bits
■ In-system programming (ISP) support with SRunner software driver
■ ISP support with USB-Blaster, EthernetBlaster, or ByteBlaster II download cables
■ Additional programming support with the APU and programming hardware
from BP Microsystems, System General, and other vendors
■ By default, the memory array is erased and the bits are set to 1
Functional Description
To configure a system using an SRAM-based device, each time you power on the
device, you must load the configuration data. The EPCS device is a flash memory
device that can store configuration data that you use for FPGA configuration purpose
after power on. You can use the EPCS device on all FPGA that support AS x1
configuration scheme.
For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the
EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from
the EPCS64 device to the EPCS128 device.
With the new data decompression feature supported, you can determine using which
EPCS device to store the configuration data for configuring your FPGA.
Example 1 shows how you can calculate the compression ratio to determine which
EPCS device is suitable for the FPGA.
f For more information about the FPGA decompression feature, refer to the
configuration chapter in the appropriate device handbook.
Example 1. Compression Ratio Calculation
EP4SGX530 = 189,000,000 bits
EPCS128 = 134,217,728 bits
Preliminary data indicates that compression typically reduces the
configuration bitstream size by 35% to 55%. Assume worst case that is 35%
decompression.
189,000,000 bits x 0.65 = 122,850,000 bits
The EPCS128 device is suitable.
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
Active Serial FPGA Configuration Page 3
Figure 1 shows the EPCS device block diagram.
Accessing Memory in EPCS Devices
You can access the unused memory locations of the EPCS device to store or retrieve
data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for
creating bus-based (especially microprocessor-based) systems in Altera devices.
SOPC Builder assembles library components such as processors and memories into
custom microprocessor systems.
SOPC Builder includes the EPCS device controller core, which is an interface core
designed specifically to work with the EPCS device. With this core, you can create a
system with a Nios embedded processor that allows software access to any memory
location within the EPCS device.
Active Serial FPGA Configuration
The following Altera FPGAs support the AS configuration scheme with EPCS devices:
■ Arria series
■ Cyclone series
■ All device families in the Stratix series except the Stratix device family
There are four signals on the EPCS device that interface directly with the FPGA’s
control signals. The EPCS device signals are DATA, DCLK, ASDI, and nCS interface with
the DATA0, DCLK, ASDO, and nCSO control signals on the FPGA, respectively.
1 For more information about the EPCS device pin description, refer to Table 22 on
page 36.
Figure 1. EPCS Device Block Diagram
Control
Logic
I/O Shift
Register
Memory
Array
Status RegisterAddress Counter
Decode Logic
Data Buffer
nCS
DCLK
DATA
ASDI
EPCS Device
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 4 Active Serial FPGA Configuration
Figure 2 shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using a download cable.
Figure 2. Altera FPGA Configuration in AS Mode Using a Download Cable (1), (4)
Notes to Figure 2:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the MSEL[] input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
nCE
nCONFIG
nSTATUS
MSEL[]
nCEO
CONF_DONE
ASDO
VCC (1) VCC (1) VCC (1)
VCC (1)
10 kΩ 10 kΩ 10 kΩ
10 kΩ
(3)
Altera FPGA
EPCS Device (2)
Pin 1
N.C.
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
Active Serial FPGA Configuration Page 5
Figure 3 shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using the APU or a third-party programmer.
In an AS configuration, the FPGA acts as the configuration master in the
configuration flow and provides the clock to the EPCS device. The FPGA enables the
EPCS device by pulling the nCS signal low using the nCSO signal as shown in Figure 2
and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device
using the ASDO signal. The EPCS device responds to the instructions by sending the
configuration data to the FPGA’s DATA0 pin on the falling edge of DCLK. The data is
latched into the FPGA on the next DCLK signal’s falling edge.
1 Before the FPGA enters configuration mode, ensure that VCC of the EPCS device is
ready. If VCC is not ready, you must hold nCONFIG low until all power rails of EPCS
device are ready.
The FPGA controls the nSTATUS and CONF_DONE pins during configuration in the AS
mode. If the CONF_DONE signal does not go high at the end of configuration, or if the
signal goes high too early, the FPGA pulses its nSTATUS pin low to start a
reconfiguration. If the configuration is successful, the FPGA releases the CONF_DONE
pin, allowing the external 10-k resistor to pull the CONF_DONE signal high. The FPGA
initialization begins after the CONF_DONE pin goes high. After the initialization, the
FPGA enters user mode.
f For more information about configuring the FPGAs in AS configuration mode or
other configuration modes, refer to the configuration chapter in the appropriate
device handbook.
Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer (1), (4)
Notes to Figure 3:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the MSEL[] input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
nCE
nCONFIG
nSTATUS
MSEL[]
nCEO
CONF_DONE
ASDO
VCC (1) VCC (1) VCC (1)
10 kΩ 10 kΩ 10 kΩ
(3)
Altera FPGA
EPCS Device (2)
N.C.
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 6 Active Serial FPGA Configuration
You can configure multiple devices with a single EPCS device. However, you cannot
cascade EPCS devices. To ensure that the programming file size of the cascaded
FPGAs does not exceed the capacity of an EPCS device, refer to Table 1 on page 1.
Figure 4 shows the AS configuration scheme with multiple FPGAs in the chain. The
first FPGA is the configuration master and its MSEL[] pins are set to AS mode. The
following FPGAs are configuration slave devices and their MSEL[] pins are set to PS
mode.
Figure 4. Multiple Devices in AS Mode (1), (5)
Notes to Figure 4:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the MSEL[] input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) Connect the MSEL[] input pins to select the PS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(5) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
nCE
nCONFIG
nSTATUS
MSEL[ ]
nCEO
CONF_DONE
ASDO
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
(3)
Altera FPGA (Master)
DATA0
DCLK
nCE
nCONFIG
nSTATUS
MSEL[ ]
nCEO
CONF_DONE
(4)
Altera FPGA (Slave)
EPCS Device (2)
N.C.
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 7
EPCS Device Memory Access
This section describes the memory array organization and operation codes of the
EPCS device. For the timing specifications, refer to “Timing Information” on page 29.
Memory Array Organization
Table 2 lists the memory array organization details in EPCS128, EPCS64, EPCS16,
EPCS4, and EPCS1 devices.
Table 3 through Table 7 on page 15 list the address range for each sector in EPCS128,
EPCS64, EPCS16, EPCS4, and EPCS1 devices.
Table 2. Memory Array Organization in EPCS Devices
Details EPCS128 EPCS64 EPCS16 EPCS4 EPCS1
Bytes 16,777,216 bytes
(128 Mb)
8,388,608 bytes
(64 Mb)
2,097,152 bytes
(16 Mb)
524,288 bytes
(4 Mb)
131,072 bytes
(1 Mb)
Number of sectors 64 128 32 8 4
Bytes per sector 262,144 bytes
(2 Mb)
65,536 bytes
(512 Kb)
65,536 bytes
(512 Kb)
65,536 bytes
(512 Kb)
32,768 bytes
(256 Kb)
Pages per sector 1,024 256 256 256 128
Total number of
pages
65,536 32,768 8,192 2,048 512
Bytes per page 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes
Table 3. Address Range for Sectors in EPCS128 Devices (Part 1 of 3)
Sector
Address Range (Byte Addresses in HEX)
Start End
63 H'FC0000 H'FFFFFF
62 H'F80000 H'FBFFFF
61 H'F40000 H'F7FFFF
60 H'F00000 H'F3FFFF
59 H'EC0000 H'EFFFFF
58 H'E80000 H'EBFFFF
57 H'E40000 H'E7FFFF
56 H'E00000 H'E3FFFF
55 H'DC0000 H'DFFFFF
54 H'D80000 H'DBFFFF
53 H'D40000 H'D7FFFF
52 H'D00000 H'D3FFFF
51 H'CC0000 H'CFFFFF
50 H'C80000 H'CBFFFF
49 H'C40000 H'C7FFFF
48 H'C00000 H'C3FFFF
47 H'BC0000 H'BFFFFF
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 8 EPCS Device Memory Access
46 H'B80000 H'BBFFFF
45 H'B40000 H'B7FFFF
44 H'B00000 H'B3FFFF
43 H'AC0000 H'AFFFFF
42 H'A80000 H'ABFFFF
41 H'A40000 H'A7FFFF
40 H'A00000 H'A3FFFF
39 H'9C0000 H'9FFFFF
38 H'980000 H'9BFFFF
37 H'940000 H'97FFFF
36 H'900000 H'93FFFF
35 H'8C0000 H'8FFFFF
34 H'880000 H'8BFFFF
33 H'840000 H'87FFFF
32 H'800000 H'83FFFF
31 H'7C0000 H'7FFFFF
30 H'780000 H'7BFFFF
29 H'740000 H'77FFFF
28 H'700000 H'73FFFF
27 H'6C0000 H'6FFFFF
26 H'680000 H'6BFFFF
25 H'640000 H'67FFFF
24 H'600000 H'63FFFF
23 H'5C0000 H'5FFFFF
22 H'580000 H'5BFFFF
21 H'540000 H'57FFFF
20 H'500000 H'53FFFF
19 H'4C0000 H'4FFFFF
18 H'480000 H'4BFFFF
17 H'440000 H'47FFFF
16 H'400000 H'43FFFF
15 H'3C0000 H'3FFFFF
14 H'380000 H'3BFFFF
13 H'340000 H'37FFFF
12 H'300000 H'33FFFF
11 H'2C0000 H'2FFFFF
10 H'280000 H'2BFFFF
9 H'240000 H'27FFFF
Table 3. Address Range for Sectors in EPCS128 Devices (Part 2 of 3)
Sector
Address Range (Byte Addresses in HEX)
Start End
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 9
8 H'200000 H'23FFFF
7 H'1C0000 H'1FFFFF
6 H'180000 H'1BFFFF
5 H'140000 H'17FFFF
4 H'100000 H'13FFFF
3 H'0C0000 H'0FFFFF
2 H'080000 H'0BFFFF
1 H'040000 H'07FFFF
0 H'000000 H'03FFFF
Table 3. Address Range for Sectors in EPCS128 Devices (Part 3 of 3)
Sector
Address Range (Byte Addresses in HEX)
Start End
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 10 EPCS Device Memory Access
Table 4. Address Range for Sectors in EPCS64 Devices (Part 1 of 4)
Sector
Address Range (Byte Addresses in HEX)
Start End
127 H'7F0000 H'7FFFFF
126 H'7E0000 H'7EFFFF
125 H'7D0000 H'7DFFFF
124 H'7C0000 H'7CFFFF
123 H'7B0000 H'7BFFFF
122 H'7A0000 H'7AFFFF
121 H'790000 H'79FFFF
120 H'780000 H'78FFFF
119 H'770000 H'77FFFF
118 H'760000 H'76FFFF
117 H'750000 H'75FFFF
116 H'740000 H'74FFFF
115 H'730000 H'73FFFF
114 H'720000 H'72FFFF
113 H'710000 H'71FFFF
112 H'700000 H'70FFFF
111 H'6F0000 H'6FFFFF
110 H'6E0000 H'6EFFFF
109 H'6D0000 H'6DFFFF
108 H'6C0000 H'6CFFFF
107 H'6B0000 H'6BFFFF
106 H'6A0000 H'6AFFFF
105 H'690000 H'69FFFF
104 H'680000 H'68FFFF
103 H'670000 H'67FFFF
102 H'660000 H'66FFFF
101 H'650000 H'65FFFF
100 H'640000 H'64FFFF
99 H'630000 H'63FFFF
98 H'620000 H'62FFFF
97 H'610000 H'61FFFF
96 H'600000 H'60FFFF
95 H'5F0000 H'5FFFFF
94 H'5E0000 H'5EFFFF
93 H'5D0000 H'5DFFFF
92 H'5C0000 H'5CFFFF
91 H'5B0000 H'5BFFFF
90 H'5A0000 H'5AFFFF
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 11
89 H'590000 H'59FFFF
88 H'580000 H'58FFFF
87 H'570000 H'57FFFF
86 H'560000 H'56FFFF
85 H'550000 H'55FFFF
84 H'540000 H'54FFFF
83 H'530000 H'53FFFF
82 H'520000 H'52FFFF
81 H'510000 H'51FFFF
80 H'500000 H'50FFFF
79 H'4F0000 H'4FFFFF
78 H'4E0000 H'4EFFFF
77 H'4D0000 H'4DFFFF
76 H'4C0000 H'4CFFFF
75 H'4B0000 H'4BFFFF
74 H'4A0000 H'4AFFFF
73 H'490000 H'49FFFF
72 H'480000 H'48FFFF
71 H'470000 H'47FFFF
70 H'460000 H'46FFFF
69 H'450000 H'45FFFF
68 H'440000 H'44FFFF
67 H'430000 H'43FFFF
66 H'420000 H'42FFFF
65 H'410000 H'41FFFF
64 H'400000 H'40FFFF
63 H'3F0000 H'3FFFFF
62 H'3E0000 H'3EFFFF
61 H'3D0000 H'3DFFFF
60 H'3C0000 H'3CFFFF
59 H'3B0000 H'3BFFFF
58 H'3A0000 H'3AFFFF
57 H'390000 H'39FFFF
56 H'380000 H'38FFFF
55 H'370000 H'37FFFF
54 H'360000 H'36FFFF
53 H'350000 H'35FFFF
52 H'340000 H'34FFFF
Table 4. Address Range for Sectors in EPCS64 Devices (Part 2 of 4)
Sector
Address Range (Byte Addresses in HEX)
Start End
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 12 EPCS Device Memory Access
51 H'330000 H'33FFFF
50 H'320000 H'32FFFF
49 H'310000 H'31FFFF
48 H'300000 H'30FFFF
47 H'2F0000 H'2FFFFF
46 H'2E0000 H'2EFFFF
45 H'2D0000 H'2DFFFF
44 H'2C0000 H'2CFFFF
43 H'2B0000 H'2BFFFF
42 H'2A0000 H'2AFFFF
41 H'290000 H'29FFFF
40 H'280000 H'28FFFF
39 H'270000 H'27FFFF
38 H'260000 H'26FFFF
37 H'250000 H'25FFFF
36 H'240000 H'24FFFF
35 H'230000 H'23FFFF
34 H'220000 H'22FFFF
33 H'210000 H'21FFFF
32 H'200000 H'20FFFF
31 H'1F0000 H'1FFFFF
30 H'1E0000 H'1EFFFF
29 H'1D0000 H'1DFFFF
28 H'1C0000 H'1CFFFF
27 H'1B0000 H'1BFFFF
26 H'1A0000 H'1AFFFF
25 H'190000 H'19FFFF
24 H'180000 H'18FFFF
23 H'170000 H'17FFFF
22 H'160000 H'16FFFF
21 H'150000 H'15FFFF
20 H'140000 H'14FFFF
19 H'130000 H'13FFFF
18 H'120000 H'12FFFF
17 H'110000 H'11FFFF
16 H'100000 H'10FFFF
15 H'0F0000 H'0FFFFF
14 H'0E0000 H'0EFFFF
Table 4. Address Range for Sectors in EPCS64 Devices (Part 3 of 4)
Sector
Address Range (Byte Addresses in HEX)
Start End
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 13
13 H'0D0000 H'0DFFFF
12 H'0C0000 H'0CFFFF
11 H'0B0000 H'0BFFFF
10 H'0A0000 H'0AFFFF
9 H'090000 H'09FFFF
8 H'080000 H'08FFFF
7 H'070000 H'07FFFF
6 H'060000 H'06FFFF
5 H'050000 H'05FFFF
4 H'040000 H'04FFFF
3 H'030000 H'03FFFF
2 H'020000 H'02FFFF
1 H'010000 H'01FFFF
0 H'000000 H'00FFFF
Table 4. Address Range for Sectors in EPCS64 Devices (Part 4 of 4)
Sector
Address Range (Byte Addresses in HEX)
Start End
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 14 EPCS Device Memory Access
Table 5. Address Range for Sectors in EPCS16 Devices
Sector
Address Range (Byte Addresses in HEX)
Start End
31 H'1F0000 H'1FFFFF
30 H'1E0000 H'1EFFFF
29 H'1D0000 H'1DFFFF
28 H'1C0000 H'1CFFFF
27 H'1B0000 H'1BFFFF
26 H'1A0000 H'1AFFFF
25 H'190000 H'19FFFF
24 H'180000 H'18FFFF
23 H'170000 H'17FFFF
22 H'160000 H'16FFFF
21 H'150000 H'15FFFF
20 H'140000 H'14FFFF
19 H'130000 H'13FFFF
18 H'120000 H'12FFFF
17 H'110000 H'11FFFF
16 H'100000 H'10FFFF
15 H'0F0000 H'0FFFFF
14 H'0E0000 H'0EFFFF
13 H'0D0000 H'0DFFFF
12 H'0C0000 H'0CFFFF
11 H'0B0000 H'0BFFFF
10 H'0A0000 H'0AFFFF
9 H'090000 H'09FFFF
8 H'080000 H'08FFFF
7 H'070000 H'07FFFF
6 H'060000 H'06FFFF
5 H'050000 H'05FFFF
4 H'040000 H'04FFFF
3 H'030000 H'03FFFF
2 H'020000 H'02FFFF
1 H'010000 H'01FFFF
0 H'000000 H'00FFFF
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 15
Operation Codes
This section describes the operations that you can use to access the memory in EPCS
devices. Use the DATA, DCLK, ASDI, and nCS signals to access the memory in EPCS
devices. When performing the operation, addresses and data are shifted in and out of
the device serially, with MSB first.
The device samples the AS data input on the first rising edge of the DCLK after the
active low chip select (nCS) input signal is driven low. Shift the operation code, with
MSB first, into the EPCS device serially through the AS data input (ASDI) pin. Each
operation code bit is latched into the EPCS device on the rising edge of the DCLK.
Different op
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