isl5216_eval1

5 5 4 4 3 3 2 2 1 1 D D C C B B A A Table Of Contents Page 1 ISL5216EVAL Schematics - Title Page Page 2 ISL5216EVAL Schematics - ISL5216 Page 3 ISL5216EVAL Schematics - Data Input Page 4 ISL5216EVAL Schematics - Data Output Page 5 ISL5216EVAL Schematics - Clock Distribution Page 6 ISL5216EVAL Schematics - Programable Logic Page 7 ISL5216EVAL Schematics - Control Interface Page 8 ISL5216EVAL Schematics - SRAM Page 9 ISL5216EVAL Schematics - Power ISL5216EVAL Schematics Highest Referenced Designators: C109 J14 JP12 L1 R61 TP11 T9 U17 Y1 Unused Designators: 0 1.0 ISL5216EVAL Schematics - Title Page C 1 9Thursday, May 03, 2001 Intersil Corporation, 2000 Title Size Document Number Rev Date: Sheet of 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Copyrighted by Intersil Corp, 1999 0 1.0 ISL5216EVAL Schematics - ISL5216 C 2 9Thursday, May 03, 2001 Title Size Document Number Rev Date: Sheet of QpdcP1 QpdcA12 QpdcA5 QpdcB10 QpdcC13 QpdcP11 QpdcP0 QpdcA11 QpdcP15 QpdcD7 QpdcC0 QpdcC9 QpdcC12 QpdcP6 QpdcP13 QpdcP9 QpdcA6 QpdcA3 QpdcP5 QpdcD2 QpdcD6 QpdcP3 QpdcB5 QpdcP13 QpdcP9 QpdcP2 QpdcP1 QpdcD0 QpdcC7 QpdcC10 QpdcC11 QpdcP10 QpdcP2 QpdcP8 QpdcB12 QpdcB8 QpdcC4 QpdcA7 QpdcA4 QpdcB2 QpdcB0 QpdcD3 QpdcD5 QpdcC1 QpdcC3 QpdcC8 QpdcA10 QpdcP6 QpdcC2 QpdcA15 QpdcP14 QpdcA13 QpdcA2 QpdcP8 QpdcP3 QpdcD15 QpdcD9 QpdcP4 QpdcA9 QpdcB6 QpdcP7 QpdcD14 QpdcP7 QpdcA1 QpdcB13 QpdcB11 QpdcB9 QpdcD1 QpdcD4 QpdcC5 QpdcD8 QpdcC6 QpdcA0 QpdcB15 QpdcD11 QpdcD12 QpdcP5 QpdcP15 QpdcA8 QpdcB7 QpdcB3 QpdcP12 QpdcP11 QpdcC14 QpdcB14 QpdcB4 QpdcB1 QpdcP10 QpdcD13 QpdcP12 QpdcA14 QpdcP14 QpdcP4 QpdcP0 QpdcD10 QpdcC15 DipSw3 DipSw1 DipSw0 DipSw2 DipSw4 QpdcReset FpgaUnused4 QpdcWr QpdcIntrpt FpgaUnused5 DipSw5 QpdcA[15:0] QpdcB[15:0] QpdcC[15:0] QpdcD[15:0] QpdcP[15:0] QpdcCe QpdcAdd2 QpdcCe QpdcSd1d QpdcOe QpdcSd2b QpdcSd2d QpdcReset QpdcIntrpt QpdcSd2c QpdcSd1a QpdcSyncd QpdcSd2a QpdcSynci QpdcEnib QpdcAdd0 QpdcSyncb QpdcSd1c QpdcEnia QpdcWr QpdcAdd0 QpdcAdd2 QpdcSynca QpdcAdd1 QpdcAdd1 QpdcSd1b QpdcSyncc RxClk2 QpdcSynco QpdcSclk1 QpdcOe QpdcOe QpdcSclk2 QpdcSclk3 PreHostClk Qpdc_tms Qpdc_trstb Qpdc_tdi Qpdc_tck Qpdc_tdo QpdcSyncI_A QpdcSyncI_B QpdcSyncI_C QpdcSyncI_D Am1 Bm1 Cm1 Dm1 QpdcEnic QpdcEnid Vqpdc_2 Vqpdc_3 R53 24 R54 24 TP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 R6 24 TP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 U1 ISL5216 A7 A8 C7 C8 C9 A9 B11 C10 A11 B12 C11 A12 A10 H1 A13 A14 D12 F 2 G 13 H 2 J1 3 K 2 N 6 N 8 N 10 A6 C6 A5 C5 A4 B4 A3 B3 A2 B2 A1 C3 B1 C2 C1 D2 C4 D1 D3 E1 E3 F1 F3 G1 H3 J1 J3 K1 K3 L1 L2 M1 M2 L3 C13 C14 D13 D14 E12 E14 F12 F14 G12 G14 H12 H14 J12 J14 K12 K14 B14 B13 L14 L13 L12 B 6 B 8 B 10 E 2 F1 3 G 2 G 3 H 13 J2 K 13 N 5 M11 M13 M14 N14 M12 P14 N13 P13 N12 P12 P11 M10 P10 M9 P9 M8 P8 M7 P7 M6 P6 M5 P5 M4 P4 N4 P3 N3 P2 M3 P1 N2 N1 N11 B 5 B 7 B 9 E 13 N 7 N 9 C12 D11 D5 E4 D4 K4 L4 L5 L10 L11 K11 D10 E11 G5 G6 G7 G8 G9 K5 K6 K7 K8 K9 G11 G10 F11 F10 F9 F8 F7 F6 F5 F4 E10 E9 E8 E7 E6 E5 D9 D8 D7 D6 G4 J11 J10 J9 J8 J7 J6 J5 J4 H11 H10 H8 H7 H5 H4 H6 K10 L6 L7 L8 L9 H9 SD1A SYNCA SD2A SD1B SD2B SYNCB SD1C SD2C SYNCC SD1D SD2D SYNCD SERCLK CLOCK SYNCI SYNCO RESETb V cc 1 V cc 1 V cc 2 V cc 1 V cc 1 V cc 1 V cc 1 V cc 2 A_15 A_14 A_13 A_12 A_11 A_10 A_09 A_08 A_07 A_06 A_05 A_04 A_03 A_02 A_01 A_00 ENIAb B_15 B_14 B_13 B_12 B_11 B_10 B_09 B_08 B_07 B_06 B_05 B_04 B_03 B_02 B_01 B_00 ENIBb P_15 P_14 P_13 P_12 P_11 P_10 P_09 P_08 P_07 P_06 P_05 P_04 P_03 P_02 P_01 P_00 ADD_1 ADD_0 WRb OEb CEb G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D ENIDb D_01 D_00 D_02 D_03 D_04 D_05 D_06 D_07 D_08 D_10 D_11 D_12 D_13 D_14 D_15 ENICb C_00 C_01 C_02 C_03 C_04 C_05 C_06 C_07 C_08 C_09 C_10 C_11 C_12 C_13 C_14 C_15 D_09 V cc 1 V cc 1 V cc 2 V cc 2 G N D G N D INTRPT ADD_2 NC NC Am1 Bm1 NC NC NC Dm1 NC NC NC Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal SYNCIn_B Thermal SYNCIn_C Thermal Thermal Thermal Thermal Thermal Thermal TMS Thermal Thermal Thermal Thermal Thermal Thermal SYNCIn_D Thermal TDO Thermal TCLK Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal SYNCIn_A Thermal Thermal Thermal Thermal TRSTb Thermal Thermal TDI Cm1 Thermal Thermal Thermal 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Copyrighted by Intersil Corp, 1999 Test point for extra floating point bits for C & D (A & B are connected to the LVDS connectors) 0 1.0 ISL5216EVAL Schematics - Data Input C 3 9Thursday, May 03, 2001 Title Size Document Number Rev Date: Sheet of QpdcD15 QpdcD14 QpdcD13 QpdcD12 QpdcD11 QpdcD10 QpdcD9 QpdcD8 QpdcD7 QpdcD6 QpdcD4 QpdcD3 QpdcD2 QpdcD1 QpdcD0 QpdcD5 RxD7 RxD6 RxD5 RxD4 RxD3 RxD2 RxD1 RxD0 RxD13 RxD15 RxD10 RxD12 RxD9 RxD14 RxD11 RxD8 QpdcC1 RxC15 QpdcC2 QpdcC9 RxC2 QpdcC7 RxC3 QpdcC11 QpdcC8 RxC6 QpdcC4 QpdcC15 RxC5 RxC12 RxC0 RxC8 RxC7 QpdcC5 QpdcC6 RxC1 QpdcC0 QpdcC3 QpdcC14 QpdcC10 RxC10 RxC14 RxC4 QpdcC12 QpdcC13 RxC13 RxC9 RxC11 QpdcB13 QpdcB13 QpdcB0 QpdcB11 QpdcB9 QpdcB4 QpdcB6 QpdcB2 QpdcB1 QpdcB11 QpdcB8 QpdcB14 QpdcB15 QpdcB12 QpdcB10 QpdcB9 QpdcB7 QpdcB1 QpdcB0 QpdcB8 QpdcB3 QpdcB12 QpdcB7 QpdcB5 QpdcB5 QpdcB10 QpdcB14 QpdcB6 QpdcB3 QpdcB15 QpdcB4 QpdcB2 RxC7 RxC13 RxC1 RxC8 RxC12 RxC6 RxC5 RxC10 RxC9 RxC11 RxC15 RxC4 RxC14 RxC3 RxC0 RxC2 RxD7 RxD13 RxD1 RxD8 RxD12 RxD6 RxD5 RxD10 RxD9 RxD11 RxD15 RxD4 RxD14 RxD3 RxD0 RxD2 QpdcA4 QpdcA8 QpdcA15 QpdcA0 QpdcA0 QpdcA3 QpdcA10 QpdcA11 QpdcA10 QpdcA1 QpdcA12 QpdcA7 QpdcA4 QpdcA13 QpdcA2 QpdcA5 QpdcA12 QpdcA5 QpdcA14 QpdcA6 QpdcA1 QpdcA3 QpdcA8 QpdcA15 QpdcA7 QpdcA6 QpdcA2 QpdcA13 QpdcA9 QpdcA14 QpdcA11 QpdcA9 RxClkC1 QpdcA[15:0] QpdcB[15:0] RxClkC1 RxClkC QpdcC[15:0] QpdcD[15:0] RxD[15:0] RxClkA4 QpdcEnia QpdcEnib Am1 RxClkA Bm1 QpdcEnic QpdcEnid Dm1 Cm1 RxC[15:0] V33 V33 V33V33 V33V33 V33 V33J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 JP2 1 2 3 R 8 10 0 R 10 10 0 R 9 10 0 R 7 10 0 JP3 1 2 3 U4 74LPT16374 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 OE1 Q1_0 Q1_1 GND Q1_2 Q1_3 Vcc Q1_4 Q1_5 GND Q1_6 Q1_7 Q2_0 Q2_1 GND Q2_2 Q2_3 Vcc Q2_4 Q2_5 GND Q2_6 Q2_7 OE2 CLK2 D2_7 D2_6 GND D2_5 D2_4 Vcc D2_3 D2_2 GND D2_1 D2_0 D1_7 D1_6 GND D1_5 D1_4 Vcc D1_3 D1_2 GND D1_1 D1_0 CLK1 T1 Z1D13Y680M510KAT2A 1 2 T2 Z1D13Y680M510KAT2A 1 2 TP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 U2 74LPT16374 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 OE1 Q1_0 Q1_1 GND Q1_2 Q1_3 Vcc Q1_4 Q1_5 GND Q1_6 Q1_7 Q2_0 Q2_1 GND Q2_2 Q2_3 Vcc Q2_4 Q2_5 GND Q2_6 Q2_7 OE2 CLK2 D2_7 D2_6 GND D2_5 D2_4 Vcc D2_3 D2_2 GND D2_1 D2_0 D1_7 D1_6 GND D1_5 D1_4 Vcc D1_3 D1_2 GND D1_1 D1_0 CLK1 JP12 1 2 3 4 U3 DS90CR218A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 NC LVDS GND RxIN0- RxIN0+ RxIN1- RxIN1+ LVDS Vcc LVDS GND RxIN2- RxIN2+ RxCLK IN- RxCLK IN+ LVDS GND PLL GND PLL Vcc PLL GND PWRDWN RxCLK OUT RxOUT0 GND RxOUT1 RxOUT2 Vcc RxOUT3 RxOUT4 RxOUT5 GND RxOUT6 RxOUT7 RxOUT8 Vcc RxOUT9 GND RxOUT10 RxOUT11 RxOUT12 Vcc RxOUT13 GND RxOUT14 RxOUT15 RxOUT16 Vcc JP10 123 U5 DS90CR218A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 NC LVDS GND RxIN0- RxIN0+ RxIN1- RxIN1+ LVDS Vcc LVDS GND RxIN2- RxIN2+ RxCLK IN- RxCLK IN+ LVDS GND PLL GND PLL Vcc PLL GND PWRDWN RxCLK OUT RxOUT0 GND RxOUT1 RxOUT2 Vcc RxOUT3 RxOUT4 RxOUT5 GND RxOUT6 RxOUT7 RxOUT8 Vcc RxOUT9 GND RxOUT10 RxOUT11 RxOUT12 Vcc RxOUT13 GND RxOUT14 RxOUT15 RxOUT16 Vcc R 2 10 0 R 3 10 0 R 4 10 0 R 5 10 0 JP9 123 JP4 AMP556591 1 2 3 4 5 6 7 8 J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 JP5 AMP556591 1 2 3 4 5 6 7 8 TP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Copyrighted by Intersil Corp, 1999 0 1.0 ISL5216EVAL Schematics - Data Output C 4 9Thursday, May 03, 2001 Title Size Document Number Rev Date: Sheet of D ac I4 D ac I5 D ac I6 D ac I7 D ac I8 D ac I9 D ac I1 0 D ac I1 1 D ac I1 2 D ac I1 3 D ac I1 4 D ac I1 5 D ac I0 D ac I1 D ac I2 D ac I3 D ac I4 D ac I5 D ac I6 D ac I7 D ac I8 D ac I1 0 D ac I1 1 D ac I9 D ac I1 2 D ac I1 3 D ac I1 4 D ac I1 5 D ac I3 D ac I2 D ac Q 5 D ac Q 7 D ac Q 9 D ac Q 11 D ac Q 6 D ac Q 0 D ac Q 13 D ac Q 5 D ac Q 3 D ac Q 11 D ac Q 4 D ac Q 14 D ac Q 13 D ac Q 4 D ac Q 2 D ac Q 2 D ac Q 15 D ac Q 6 D ac Q 8 D ac Q 8 D ac Q 10 D ac Q 10 D ac Q 7 D ac Q 15 D ac Q 12 D ac Q 9 D ac Q 12 D ac Q 14 D ac Q 1 D ac Q 3 QpdcSd1a QpdcSd2a QpdcSclk2 QpdcSd1b QpdcSd2b QpdcSd1c QpdcSd2c QpdcSd1d QpdcSd2d DacClk1 DacClk2 DacQ[15:0] DacI[15:0] QpdcSyncd QpdcSyncc QpdcSyncb QpdcSynca V33V33 Avdd V33 C4 .1 uF R59 500 C5 .1 uF R52 0 U6 74LPT16244 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 OE1 Y1_0 Y1_1 GND Y1_2 Y1_3 Vcc Y2_0 Y2_1 GND Y2_2 Y2_3 Y3_0 Y3_1 GND Y3_2 Y3_3 Vcc Y4_0 Y4_1 GND Y4_2 Y4_3 OE2 OE3 A4_3 A4_2 GND A4_1 A4_0 Vcc A3_3 A3_2 GND A3_1 A3_0 A2_3 A2_2 GND A2_1 A2_0 Vcc A1_3 A1_2 GND A1_1 A1_0 OE4 J7 161-3501 2 5 1 J8 1 2 3 TP6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C 7 .1 u F R 15 1. 87 K J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C 3 .1 u F C 6 .1 u F R 12 51 R58 500 R 11 51 U7 HI5828 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 252627282930313233343536 37 38 39 40 41 42 43 44 45 46 47 48 ID 05 ID 04 ID 03 ID 02 ID 01 ID 00 ( LS B ) N C N C S LE E P D vd d A G N D IC M P 2 Avdd ICMP1 IOUTA IOUTB REFIO REFLO AGND FSADJ QOUTB QOUTA QCMP1 Avdd Q C M P 2 A G N D D G N D C LK (M S B ) Q D 11 Q D 10 Q D 09 Q D 08 Q D 07 Q D 06 Q D 05 Q D 04 OD03 OD02 OD01 (LSB) OD00 NC NC (MSB) ID11 ID10 ID09 ID08 ID07 ID06 TP5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T5 DNI 1 2 R 13 51 R 14 51 C94 .1 uF C95 .1 uF 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Note: Terminators are to be placed at the end of each clock net as close to the ending compenent as reasonable. Copyrighted by Intersil Corp, 1999 0 1.0 ISL5216EVAL Schematics - Clock Distribution C 5 9Thursday, May 03, 2001 Title Size Document Number Rev Date: Sheet of RxClkAMuxS1 RxClkA4 RxClk2 RxClk4 RxClkCMuxS2 RxClkC1 RxClkAMuxS2 RxClkC RxClkCMuxS1 RxClkA SysClk SysClk V33 V33V33 V33 V33 TP7 1 2 1 2 T9 DNI 1 2 JP1 1 2 3 T6 Z1D13Y680M510KAT2A 1 2 T4 Z1D13Y680M510KAT2A 1 2 R 45 10 K Y1 SG636 1 2 4 3 OE GND Vcc OUT U9 CY2309 16 2 3 14 15 6 7 10 11 1 98 5 12 4 13 CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 REF S1S2 GND GND VDD VDD C9 DNI C8 DNI U8 CY2309 16 2 314 15 6 710 11 1 9 8 512 413 CLKOUT CLKA1 CLKA2CLKA3 CLKA4 CLKB1 CLKB2CLKB3 CLKB4 REF S1 S2 GNDGND VDDVDD R 42 10 K R 43 10 K R 44 10 K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Copyrighted by Intersil Corp, 1999 0 1.0 ISL5216EVAL Schematics - Programable Logic C 6 9Thursday, May 03, 2001 Title Size Document Number Rev Date: Sheet of HostData4 HostData2 HostData5 HostData6 HostData7 HostData3 HostData7 RxD7 RxD5 RxD3 RxD2 Q pd cP 15 Q pd cP 14 Q pd cP 13 Q pd cP 12 Q pd cP 11 Q pd cP 10 Q pd cP 9 Q pd cP 8 Q pd cP 7 Q pd cP 6 Q pd cP 5 Q pd cP 4 Q pd cP 3 Q pd cP 2 Q pd cP 1 Q pd cP 0 R xD 9 RxD6 RxD4 R xD 8 RxD1 PcAdd8 PcAdd7 P cA dd 3 HostData5 D ac I1 4 D ac I1 3 D ac I1 2 D ac I1 1 D ac I1 0 D ac I9 D ac I8 D ac I7 D ac I6 D ac I5 D ac I4 D ac I3 D ac I2 D ac I1 SramAdd10 SramData5 SramAdd9 SramData3 SramAdd12 SramData11 SramData14 SramAdd19 SramAdd11 SramData9 SramAdd14 SramData0 SramData6 SramAdd16 SramData2 SramData8 SramAdd17 SramAdd7 SramData7 SramData10 SramAdd18 SramData15 SramAdd8 SramData4 SramData13 SramAdd13 SramData1 SramData12 SramAdd5 SramAdd6 SramAdd15 SramAdd0 SramAdd1 SramAdd2 SramAdd3 SramAdd4 D ac I0 D ac I1 5 RxD0 D ac Q 0 D ac Q 2 D ac Q 4 D ac Q 9 D ac Q 11 D ac Q 13 D ac Q 8 D ac Q 15 D ac Q 1 D ac Q 3 D ac Q 5 D ac Q 10 D ac Q 12 D ac Q 7 D ac Q 6 D ac Q 14 HostData15 HostData14 HostData13 HostData12 HostData11 HostData9 HostData8 HostData2 HostData10 HostData4 HostData6 HostData0 HostData1 R xD 12 R xD 14 R xD 11 R xD 13 R xD 15 R xD 10 HostData0 HostData1 HostData3 PcAdd9 P cA dd 6 P cA dd 5 P cA dd 4 P ppt 关于艾滋病ppt课件精益管理ppt下载地图下载ppt可编辑假如ppt教学课件下载triz基础知识ppt rClk PpPtrBusy PpAckDataReq PpHostBusy PpInit FpgaDone PpXflag PpDataAvail PpIeee1284Active DipSw1 DipSw4 DipSw2 DipSw3 DipSw5 DipSw6 QpdcSyncd QpdcSd2d QpdcSd1d QpdcSyncc QpdcSd2c QpdcSd1c QpdcSyncb QpdcSd2b QpdcSd1b QpdcSynca QpdcSd2a QpdcSd1a QpdcAdd1 QpdcAdd0 QpdcIntrpt QpdcWr QpdcOe QpdcCe DipSw0 PpHostClk SysClk PcIochrdy PcSbhe FpgaProgram PcIocs16 DipSw7 PcIrq10 PpDataAvail PpInit PpIeee1284Active PpHostBusy PpAckDataReq PpPtrClk PpPtrBusy RxClk4 RxClk4 FpgaDone FpgaProgram DacClk1 JtagTck JtagTms JtagTdi JtagTck JtagTms CpldTdiJtagTdo CpldTdi SramCe1Not SramCe2 SramCe2Not SramRw SramAdvLd SramOeNot FpgaRw FpgaCsOrLdc FpgaResetOrInit RxClkAMuxS2 RxClkAMuxS1 RxClkCMuxS2 RxClkCMuxS1 FpgaCclk FpgaCclk Pp1284Dir PcIrq5 PcAen FpgaRw QpdcIntrpt PcIor PcReset PcIow QpdcSclk1 SysClk DacClk2 DacI[15:0] DacQ[15:0] QpdcSynco QpdcSync1 QpdcSync2 QpdcSync3 SramData[15:0] SramAdd[19:0] SramP1 SramP2 HostData[15:0] RxD[15:0] QpdcP[15:0] HostData[15:0] PcAdd[9:3] Pp1284Hd FpgaCsOrLdc FpgaUnused4 FpgaUnused5 Pp1284Dir PpXflag PpHostClk FpgaResetOrInit QpdcAdd2 SramCenNot QpdcReset V33 V33 V33 V33 R 16 D N I R 17 D N I R 18 0 R 19 D N I R60 10k R 20 D N I R 21 D N I U12 XC9536XL-VQ64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33343536373839404142434445464748 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 N C FB 2_ 5 (G TS 2) V cc in t N C FB 2_ 3 (G TS 1) FB 2_ 4 FB 2_ 2 FB 2_ 1 FB 1_ 1 FB 1_ 2 FB 1_ 4 N C N C N C FB 1_ 3 (G C K 1) FB 1_ 5 (G C K 2) FB1_7 (GCK3) NC FB1_6 FB1_8 GND FB1_9 NC FB1_10 FB1_11 NC FB1_12 TDI TMS TCK NC NC FB 1_ 13N C FB 1_ 14 FB 1_ 15 V cc in t FB 1_ 16 FB 1_ 18N C G N D FB 1_ 17 FB 2_ 17 FB 2_ 16 FB 2_ 15N C N C FB 2_ 14 FB2_18 FB2_13 NC NC TDO GND Vccio FB2_12 FB2_11 NC NC FB2_10 FB2_9 FB2_8 FB2_7 (GSR) FB2_6 T3 DNI 1 2 U11 XCS30XL 23 2 23 1 23 0 22 9 22 8 22 7 22 6 22 5 22 4 22 3 22 2 22 1 22 0 21 9 21 8 21 7 21 6 21 5 21 4 21 3 21 2 21 1 21 0 20 9 20 8 20 7 20 6 20 5 20 4 20 3 20 2 20 1 20 0 19 9 19 8 19 7 19 6 19 5 19 4 19 3 19 2 19 1 19 0 18 9 18 8 18 7 18 6 18 5 18 4 18 3 18 2 18 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 11 0 11 1 11 2 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 53 54 55 56 57 58 59 60 11 3 11 4 11 5 11 6 11 7 11 8 11 9 12 0 180 179 178 177 176 175 174 173 23 6 23 5 23 4 23 3 24 0 23 9 23 8 23 7 IO _2 32 IO _2 31 IO _2 30 IO _2 29 IO _2 28 G N D IO _2 26 IO _2 25 IO _2 24 IO _2 23 V cc IO _2 21 IO _2 20 G N D IO _2 18 IO _2 17 IO _2 16 IO _2 15 IO _2 14 IO _2 13 V cc G N D IO _2 10 IO _2 09 IO _2 08 IO _2 07 IO _2 06 IO _2 05 G N D IO _2 03 IO _2 02 V cc IO _2 00 IO _1 99 IO _1 98 IO _1 97 G N D N C IO _1 94 IO _1 93 IO _1 92 IO _1 91 IO _1 90 IO _1 89 IO _1 88 (C S 1) IO _1 87 IO _1 86 IO _1 85 (G C K 7) IO _1 84 IO _1 83 G N D (T D O ) O 18 1 GND IO_002 (GCK1) IO_003 IO_004 IO_005 IO_006 (TDI) IO_007 (TCK) IO_008 IO_009 IO_010 IO_011 IO_012 IO_013 GND IO_015 IO_016 IO_017 (TMS) IO_018 Vcc IO_020 IO_021 GND IO_023 IO_024 IO_025 IO_026 IO_027 IO_028 GND Vcc IO_031 IO_032 IO_033 IO_034 IO_035 IO_036 GND IO_038 IO_039 Vcc IO_041 IO_042 IO_043 IO_044 GND IO_046 IO_047 IO_048 IO_049 IO_050 IO_051 IO_052 V cc P W R D W N IO _0 63 ( G C K 3) IO _0 64 ( H D C ) IO _0 65 IO _0 66 IO _0 67 IO _0 68 ( LD C ) IO _0 69 IO _0 70 IO _0 71 IO _0 72 IO _0 73 IO _0 74 G N D IO _0 76 IO _0 77 IO _0 78 IO _0 79 V cc IO _0 81 IO _0 82 G N D IO _0 84 IO _0 85 IO _0 86 IO _0 87 IO _0 88 IO _0 89 ( IN IT ) V cc G N D IO _0 92 IO _0 93 IO _0 94 IO _0 95 IO _0 96 IO _0 97 G N D IO _0 99 IO _1 00 V cc IO _1 02 IO _1 03 IO _1 04 IO _1 05 G N D IO _1 07 IO _1 08 IO _1 09 IO _1 10 IO _1 11 IO _1 12 IO_172 IO_171 IO_170 IO_169 IO_168 IO_167 GND IO_165 IO_164 IO_163 IO_162 Vcc IO_160 (D2) IO_159 GND IO_157 IO_156 IO_155 IO_154 IO_153 (D3) IO_152 GND Vcc IO_149 (D4) IO_148 IO_147 IO_146 IO_145 IO_144 GND IO_142 (D5) IO_141 Vcc IO_139 IO_138 IO_137 IO_136 GND IO_134 IO_133 IO_132 IO_131 IO_130 (D6) IO_129 IO_128 IO_127 IO_126 IO_125 (GCK5) IO_124 (D7) IO_123 PROGRAM Vcc IO_053 IO_054 IO_055 IO_056 IO_057 (GCK2) M1 GND M0 IO _1 13 IO _1 14 IO _1 15 IO _1 16 IO _1 17 IO _1 18 ( G C K 4) G N D D O N E Vcc CCLK (GCK6/DOUT) IO_178 (D0/DIN) IO_177 IO_176 IO_175 IO_174 (D1) IO_173 IO _2 36 IO _2 35 IO _2 34 IO _2 33V cc (G C K 8) IO _2 39 IO _2 38 IO _2 37 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Copyrighted by Intersil Corp, 1999 C 9 8 s h o u ld be placed between U14 and T P 3 , b a s i cally to have ground connected t o g ether with C78 JTAG Header for ISL5216 0 1.0 ISL5216EVAL Schematics - Control Interface C 7 9Thursday, May 03, 2001 Title Size Document Number Rev Date: Sheet of HostData0 HostData1 HostData4 HostData3 HostData6 HostData2 HostData5 HostData7 PreInit PreHostBusy PreD2 PreD1 PreD0 PreD6 PreD7 PreDataAvail PreXflag PreAckDataReq PreXflag PreDataAvail PreHostClk PrePtrBusy PrePtrClk PreAckDataReq PrePtrClk PrePtrBusy PreD0 PreD1 PreD2 PreD3 PreD4 PreD5 PreD6 PreD7 Pp1284Hd PpPtrClk PpPtrBusy PpAckDataReq PpXflag PpDataAvail PpHostClk PpHostBusy PpInit PpIeee1284Active PreHostClk PreHostBusy PreInit PreIeee1284Active Pp1284Dir PreD4 PreD5 PreD3 PreIeee1284Active JtagTms JtagTdi JtagTdo HostData[15:0] QpdcSynci QpdcSynco QpdcSync1 QpdcSync3 QpdcSync2 JtagTck QpdcSyncI_A QpdcSyncI_B QpdcSyncI_C QpdcSyncI_D Qpdc_tdo Qpdc_tdi Qpdc_tms Qpdc_tck Qpdc_trst