datasheet_ad9862

REV. 0 a Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD9860/AD9862* Mixed-Signal Front-End (MxFE™) Processor for Broadband Communications *Protected by U.S.Patent No. 5,969,657; other patents pending. MxFE is a trademark of Analog Devices, Inc. GENERAL DESCRIPTION The AD9860 and AD9862 (AD9860/AD9862) are versatile integrated mixed-signal front-ends (MxFE) that are optimized for broadband communication markets. The AD9860/AD9862 are cost effective, mixed signal solutions for wireless or wireline standards based or proprietary broadband modem systems where dynamic performance, power dissipation, cost, and size are all critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs; the AD9862 has 12-bit ADCs and 14-bit DACs. The AD9860/AD9862 receive path (Rx) consists of two channels that each include a high performance, 10-/12-bit, 64 MSPS analog- to-digital converter (ADC), input buffer, Programmable Gain Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The Rx can be used to receive real, diversity, or I/Q data at baseband or low IF. The input buffers provide a constant input impedance for both channels to ease impedance matching with external com- ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain range for both channels. The output data bus can be multi- plexed to accommodate a variety of interface types. The AD9860/AD9862 transmit path (Tx) consists of two chan- nels that contain high performance, 12-/14-bit, 128 MSPS digital-to-analog converters (DAC), programmable gain amplifiers (TxPGA), interpolation filters, a Hilbert filter, and digital mixers for complex or real signal frequency modulation. The Tx latch and demultiplexer circuitry can process real or I/Q data. Interpo- lation rates of 2� and 4� are available to ease requirements on an external reconstruction filter. For single channel systems, the digital Hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. The two 12-/14-bit, high performance DACs produce an output signal that can be scaled over a 20 dB range by the TxPGA. A programmable delay-locked loop (DLL) clock multiplier and integrated timing circuits enable the use of a single external reference clock or an external crystal to generate clocking for all internal blocks and also provides two external clock outputs. Additional features include a programmable sigma-delta output, four auxiliary ADC inputs and three auxiliary DAC outputs. Device programmability is facilitated by a serial port interface (SPI) combined with a register bank. The AD9860/AD9862 is available in a space saving 128-lead LQFP. FUNCTIONAL BLOCK DIAGRAM Tx DATA [0:13] PGA PGA DAC DAC HILBERT FILTER LOGIC LOW ADC ADC PGA PGA 1x 1x IOUT+A IOUT–A IOUT+B IOUT–B AUX_ADC_B2 AUX_ADC_B1 AUX_ADC_A2 AUX_ADC_A1 AUX_DAC_C AUX_DAC_B AUX_DAC_A SIGDELT VIN+A VIN–A VIN+B VIN–B �-� AUX DAC AUX DAC AUX DAC AUX ADC AUX ADC RxA DATA [0:11] RxB DATA [0:11] SPI INTERFACE OSC1 OSC2 CLKOUT1 CLKOUT2 SPI REGISTERS CLOCK DISTRIBUTION BLOCK DLL 1�, 2�, 4� Rx PATH TIMING Tx PATH TIMING AD9860/AD9862 HILBERT FILTER BYPASSABLE DIGITAL QUADRATURE MIXER BYPASSABLE DIGITAL QUADRATURE MIXER BYPASSABLE LOW-PASS INTERPOLATION FILTER NCOFS/4FS/8 BYPASSABLE LOW-PASS DECIMATION FILTER FEATURES Mixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path Includes: Two 10-/12-Bit, 64 MSPS Sampling A/D Converters with Internal or External Independent References, Input Buffers, Programmable Gain Amplifiers, Low-Pass Decimation Filters, and a Digital Hilbert Filter Transmit Signal Path Includes: Two 12-/14-Bit, 128 MSPS D/A Converters with Programmable Full-Scale Output Current, Channel Independent Fine Gain and Offset Control, Digital Hilbert and Interpolation Filters, and Digitally Tunable Real or Complex Up-Converters Delay-Locked Loop Clock Multiplier and Integrated Timing Generation Circuitry Allow for Single Crystal or Clock Operation Programmable Output Clocks, Serial Programmable Interface, Programmable Sigma-Delta, Three Auxiliary DAC Outputs and Two Auxiliary ADCs with Dual Multiplexed Inputs APPLICATIONS Broadband Wireless Systems Fixed Wireless, WLAN, MMDS, LMDS Broadband Wireline Systems Cable Modems, VDSL, PowerPlug Digital Communications Set-Top Boxes, Data Modems Administrator 下划线 Administrator 下划线 REV. 0–2– AD9860/AD9862–SPECIFICATIONS(VA = 3.3 V � 5%, VD = 3.3 V � 10%, fDAC = 128 MHz, fADC = 64 MHzNormal Timing Mode, 2� DLL Setting, RSET = 4 k�, 50 � DAC Load, RxPGA = +6 dB Gain, TxPGA = +20 dB Gain.) Test AD9860/AD9862 Tx PARAMETERS Temp Level Min Typ Max Unit 12-/14-BIT DAC CHARACTERISTICS Resolution NA NA 12/14 Bits Maximum Update Rate 128 MSPS Full-Scale Output Current Full I 2 20 mA Gain Error (Using Internal Reference) 25ºC I –5.5 +0.5 +5.5 %FS Offset Error 25ºC I –1 0.0 +1 %FS Reference Voltage (REFIO Level) 25ºC I 1.15 1.22 1.28 V Negative Differential Nonlinearity (–DNL) 25ºC III –0.5/–0.5 LSB Positive Differential Nonlinearity (+DNL) 25ºC III 1/2 LSB Integral Nonlinearity (INL) 25ºC III ±1/±3 LSB Output Capacitance 25ºC III 5 pF Phase Noise @ 1 kHz Offset, 6 MHz Tone Crystal and OSC IN Multiplier Enabled at 4� 25ºC III –115 dBc/Hz Output Voltage Compliance Range Full II –0.5 +1.5 V TRANSMIT TxPGA CHARACTERISTICS Gain Range 25ºC III 20 dB Step Size Accuracy 25ºC III ±0.1 dB Step Size 25ºC III 0.08 dB Tx DIGITAL FILTER CHARACTERISTICS Hilbert Filter Pass Band (<0.1 dB Ripple) Full II 12.5 38 % fDATA1 2�/4� Interpolator Stop Band2 Full II ±38 % fDATA DYNAMIC PERFORMANCE (AOUT = 20 mA FS, f = 1 MHz) Differential Phase 25ºC III <0.1 Degree Differential Gain 25ºC III <1 LSB AD9860 Signal-to-Noise Ratio (SNR) Full I 68.2 70.7 dB AD9860 Signal-to-Noise and Distortion Ratio Full I 62.5 66.1 dB AD9860 Total Harmonic Distortion (THD) Full I –74.5 –64.0 dB AD9860 Wideband SFDR (to Nyquist) 1 MHz Analog Out, IOUT = 2 mA 25ºC III 70.6 dBc 1 MHz Analog Out, IOUT = 20 mA 25ºC I 64.4 75 dBc 6 MHz Analog Out, IOUT = 20 mA 25ºC III 75 dBc AD9860 Narrowband SFDR (1 MHz Window) 1 MHz Analog Out, IOUT = 2 mA 25ºC III 70.2 dBc 1 MHz Analog Out, IOUT = 20 mA 25ºC I 83 90 dBc AD9862 Signal-to-Noise Ratio (SNR) Full I 68.9 72.0 dB AD9862 Signal-to-Noise and Distortion Ratio Full I 64.75 69.8 dB AD9862 Total Harmonic Distortion (THD) Full I –75.5 –65.0 dB AD9862 Wideband SFDR (to Nyquist) 1 MHz Analog Out, IOUT = 2 mA 25ºC III 70.6 dBc 1 MHz Analog Out, IOUT = 20 mA 25ºC I 64.9 76.0 dBc 6 MHz Analog Out, IOUT = 20 mA 25ºC III 76.0 dBc AD9862 Narrowband SFDR (1 MHz Window) 1 MHz Analog Out, IOUT = 2 mA 25ºC III 70.2 dBc 1 MHz Analog Out, IOUT = 20 mA 25ºC I 83 90 dBc Rx PARAMETERS RECEIVE BUFFER Input Resistance (Differential) Full III 200 W Input Capacitance (Each Input) Full III 5 pF Maximum Input Bandwidth (–3 dB) Full III 140 MHz Analog Input Range (Best Noise Performance) Full II 2 V p-p Diff Analog Input Range (Best THD Performance) Full II 1 V p-p Diff RECEIVE PGA CHARACTERISTICS Gain Error 25ºC I ±0.3 dB Gain Range 25ºC I 19 20 21 dB Step Size Accuracy 25ºC I ±0.2 dB Step Size 25ºC I 1 dB Input Bandwidth (–3 dB, Rx Buffer Bypassed) 25ºC III 250 MHz 10-/12-BIT ADC CHARACTERISTICS Resolution NA NA 10/12 Bits Maximum Conversion Rate Full I 64 MHz REV. 0 AD9860/AD9862 –3– Test AD9860/AD9862 Rx PARAMETERS (continued) Temp Level Min Typ Max Unit DC ACCURACY Differential Nonlinearity 25ºC III ±0.3/±0.4 LSB Integral Nonlinearity 25ºC III ±1.2/±5 LSB Offset Error 25ºC III ±0.1 %FSR Gain Error 25ºC III ±0.2 %FSR Aperture Delay 25ºC III 2.0 ns Aperture Uncertainty (Jitter) 25ºC III 1.2 ps rms Input Referred Noise 25ºC III 250 µV Reference Voltage Error REFT-REFB Error (1 V) 25ºC I ±1 ±4 mV AD9860 DYNAMIC PERFORMANCE (AIN = –0.5 dBFS, f = 5 MHz) Signal-to-Noise Ratio 25∞C I 59.0 60.66 dBc Signal-to-Noise and Distortion Ratio 25∞C I 56.0 58.0 dBc Total Harmonic Distortion 25∞C I –76.5 –70.5 dBc Spurious Free Dynamic Range 25∞C I 70.3 81.0 dBc AD9862 DYNAMIC PERFORMANCE (AIN = –0.5 dBFS, f = 5 MHz) Signal-to-Noise Ratio 25∞C I 62.6 64.2 dBc Signal-to-Noise and Distortion Ratio 25∞C I 62.5 64.14 dBc Total Harmonic Distortion 25∞C I –79.22 –73.2 dBc Spurious Free Dynamic Range 25∞C I 77.09 85.13 dBc CHANNEL-TO-CHANNEL ISOLATION Tx-to-Rx (AOUT = 0 dBFS, fOUT = 7 MHz) 25ºC III >90 dB Rx Channel Crosstalk (f1 = 6 MHz, f2 = 9 MHz) 25ºC III >80 dB PARAMETERS CMOS LOGIC INPUTS Logic “1” Voltage, VIH 25ºC II DRVDD – 0.7 V Logic “0” Voltage, VIL 25ºC II 0.4 V Logic “1” Current 25ºC II 12 µA Logic “0” Current 25ºC II 12 µA Input Capacitance 25ºC III 3 pF CMOS LOGIC OUTPUTS (1 mA Load) Logic “1” Voltage, VOH 25ºC II DRVDD – 0.6 V Logic “0” Voltage, VOL 25ºC II 0.4 V POWER SUPPLY Analog Supply Currents Tx (Both Channels, 20 mA FS Output) 25ºC I 70 76 mA Tx Powered Down 25ºC I 2.5 5.0 mA Rx (Both Channels, Input Buffer Enabled) 25ºC I 275 307 mA Rx (Both Channels, Input Buffer Disabled) 25ºC III 245 mA Rx (32 MSPS, Low Power Mode, Buffer Disabled) 25ºC III 155 mA Rx (16 MSPS, Low Power Mode, Buffer Disabled) 25ºC III 80 mA Rx Path Powered Down 25ºC I 5.0 6.0 mA DLL 25ºC III 12 mA Digital Supply Current AD9860 Both Rx and Tx Path (All Channels Enabled) 2� Interpolation, fDAC = fADC = 64 MSPS 25ºC I 92 112 mA AD9862 Both Rx and Tx Path (All Channels Enabled) 2� Interpolation, fDAC = fADC = 64 MSPS 25ºC I 104 124 mA Tx Path (fDAC = 128 MSPS) Processing Blocks Disabled 25ºC III 45 mA 4� Interpolation 25ºC III 90 mA 4� Interpolation, Coarse Modulation 25ºC III 110 mA 4� Interpolation, Fine Modulation 25ºC III 110 mA 4� Interpolation, Coarse and Fine Modulation 25ºC III 130 mA REV. 0–4– AD9860/AD9862 Test AD9860/AD9862 (20 pF Load) Temp Level Min Typ Max Unit Minimum Reset Pulsewidth Low (tRL) NA NA 5 Clock Cycles Digital Output Rise/Fall Time 25ºC III 2.8 4 ns DLL Output Clock 25ºC III 32 128 MHz DLL Output Duty Cycle 25ºC III 50 % Tx–/Rx–Interface (See Figures 11 and 12) TxSYNC/TxIQ Setup Time (tTx1, tTx3) 25ºC III 3 ns TxSYNC/TxIQ Hold Time (tTx2, tTx4) 25ºC III 3 ns RxSYNC/RxIQ/IF to Valid Time(tRx1, tRx3) 25ºC III 5.2 ns RxSYNC/RxIQ/IF Hold Time (tRx2, tRx4) 25ºC III 0.2 ns Serial Control Bus (See Figures 1 and 2) Maximum SCLK Frequency (fSCLK) Full III 16 MHz Minimum Clock Pulsewidth High (tHI) Full III 30 ns Minimum Clock Pulsewidth Low (tLOW) Full III 30 ns Maximum Clock Rise/Fall Time Full III 1 ms Minimum Data/SEN Setup Time (tS) Full III 25 ns Minimum SEN/Data Hold Time (tH) Full III 0 ns Minimum Data/SCLK Setup Time (tDS) Full III 25 ns Minimum Data Hold Time (tDH) Full III 0 ns Output Data Valid/SCLK Time (tDV) Full III 30 ns AUXILARY ADC Conversion Rate 25ºC III 1.25 MHz Input Range 25ºC III 3 V Resolution 25ºC III 10 Bits AUXILARY DAC Settling Time 25ºC III 8 ms Output Range 25ºC III 3 V Resolution 25ºC III 8 Bits ADC TIMING Latency (All Digital Processing Blocks Disabled) 25ºC III 7 Cycles DAC Timing Latency (All Digital Processing Blocks Disabled) 25ºC III 3 Cycles Latency (2� Interpolation Enabled) 25ºC III 30 Cycles Latency (4� Interpolation Enabled) 25ºC III 72 Cycles Additional Latency (Hilbert Filter Enabled) 25ºC III 36 Cycles Additional Latency (Coarse Modulation Enabled) 25ºC III 5 Cycles Additional Latency (Fine Modulation Enabled) 25ºC III 8 Cycles Output Settling Time (TST) (to 0.1%) 25ºC III 35 ns Specifications subject to change without notice. TIMING CHARACTERISTICS Test AD9860/AD9862 PARAMETERS (continued) Temp Level Min Typ Max Unit POWER SUPPLY (continued) Rx Path (fADC = 64 MSPS) Processing Blocks Disabled 25ºC III 9 mA Decimation Filter Enabled 25ºC III 15 mA Hilbert Filter Enabled 25ºC III 16 mA Hilbert and Decimation Filter Enabled 25ºC III 18.5 mA NOTES 1% fDATA refers to the input data rate of the digital block. 2Interpolation filter stop band is defined by image suppression of 50 dB or greater. Specifications subject to change without notice. REV. 0 AD9860/AD9862 –5– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS1 Power Supply (VAS, VDS) . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . . –0.3 V to AVDD (IQ) + 0.3 V Operating Temperature2 . . . . . . . . . . . . . . . . . –40�C to +70�C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150�C Storage Temperature . . . . . . . . . . . . . . . . . . . –65�C to +150�C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300�C NOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40�C to +85�C) when operated in Half Duplex Mode. EXPLANATION OF TEST LEVELS I. Devices are 100% production tested at 25ºC and guaranteed by design and characterization testing for the extended industrial temperature range (–40ºC to +70ºC). II. Parameter is guaranteed by design and/or characterization testing. III. Parameter is a typical value only. NA. Test level definition is not applicable. THERMAL CHARACTERISTICS Thermal Resistance 128-Lead LQFP �JA = 29ºC/W ORDERING GUIDE Model Temperature Range Package Description Package Option AD9860BST –40∞C to +70∞C* 128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128B AD9862BST –40∞C to +70∞C* 128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128B AD9860PCB Evaluation Board with AD9860 AD9862PCB Evaluation Board with AD9862 *The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40 �C to +85�C) when operated in Half Duplex Mode. REV. 0–6– AD9860/AD9862 PIN CONFIGURATION 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 31 37 AGND AVDD DVDD DGND DGND DVDD Tx11/13 (MSB) Tx10/12 39 40 41 42 43 44 45 46 47 48 49 50 63 6461 6259 6057 5855 5653 5451 52 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 69 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AGND AVDD AVDD AUX_SPI_csb AUX_SPI_clk AUX_SPI_do DGND DVDD RxSYNC D9/D11B (MSB) D8/D10B D7/D9B D6/D8B D5/D7B D4/D6B D3/D5B D2/D4B D1/D3B D0/D2B NC/D1B PIN 1 IDENTIFIER TOP VIEW(Not to Scale) Tx 9/ 11 Tx 8/ 10 Tx 7/ 9 Tx 6/ 8 Tx 5/ 7 Tx 4/ 6 Tx 3/ 5 Tx 2/ 4 Tx 1/ 3 Tx 0/ 2 N C/ Tx 1 N C/ Tx 0 NC/D0B D9/D11A (MSB) D8/D10A D7/D9A D6/D8A D5/D7A D4/D6A D3/D5A D2/D4A D1/D3A D0/D2A NC/D1A NC/D0A DGND DVDD CLKOUT1 AUX_ADC_A1 AGND AVDD AVDD SIGDELT AUX_DAC_A AUX_DAC_B AUX_DAC_C AGND DLL_Lock AGND NC AVDD OSC1 OSC2 AGND CLKSEL AVDD AGND AVDD REFIO FSADJ AVDD AGND IOUT–A IOUT+A AGND AGND IOUT+B IOUT–B AD9860/AD9862 Tx SY NC D G ND DV D D SC LK SD O SD IO SE N D G ND DV D D D G ND DV D D M O DE /T xB LA NK R ES ET B CL KO UT 2 REFT_B REFB_B 101 102 12 8 12 7 12 6 12 5 12 4 12 3 12 2 12 1 12 0 11 9 11 8 11 7 10 4 10 3 10 6 10 5 10 8 10 7 11 0 10 9 11 2 11 1 11 4 11 3 11 6 11 5 AG ND AV D D AV D D AG ND VI N +B VI N –B AG ND AG ND VR EF AG ND AG ND VI N –A VI N +A AG ND AV D D AV D D AG ND R EF B _A R EF T_ A AG ND AV D D AV D D AU X_ A D C_ B2 AU X_ A D C_ B1 AU X_ A D C_ RE F AU X_ A D C_ A2 NC = NO CONNECT REV. 0 AD9860/AD9862 –7– Pin No. Mnemonic Function Clock Pins 10 DLL_Lock DLL Lock Indicator Pin 11, 16 AGND DLL Analog Ground Pins 12 NC No Connect 13 AVDD DLL Analog Supply Pin 14 OSC1 Single Ended Input Clock (or Crystal Oscillator Input) 15 OSC2 Crystal Oscillator Input 17 CLKSEL Controls CLKOUT1 Rate 64 CLKOUT2 Clock Output Generated from Input Clock (DLL Multiplier Setting and CLKOUT2 Divide Factor) 65 CLKOUT1 Clock Output Generated from Input Clock (1� if CLKSEL = 1 or /2 if CLKSEL = 0) Various Pins 1 AUX_ADC_A1 Auxiliary ADC A Input 1 3, 4, 13 AVDD Analog Power Pins 2, 9 AGND Analog Ground Pins 5 SIGDELT Digital Output from Programmable Sigma-Delta 6 AUX_DAC_A Auxiliary DAC A Output 7 AUX_DAC_B Auxiliary DAC B Output 8 AUX_DAC_C Auxiliary DAC C Output 33, 36, 53, DVDD Digital Power Supply Pin 59, 61, 66, 93 34, 35, 52, DGND Digital Ground Pin 58, 60, 67, 94 54 SCLK Serial Bus Clock Input 55 SDO Serial Bus Data Bit 56 SDIO Serial Bus Data Bit 57 SEN Serial Bus Enable 63 RESETB Reset (SPI Registers and Logic) 95 AUX_SPI_do Optional Auxiliary ADC Serial Bus Data Out Bit 96 AUX_SPI_clk Optional Auxiliary ADC Serial Bus Data Out Latch Clock 97 AUX_SPI_csb Optional Auxiliary ADC Serial Bus Chip Select Bit 128 AUX_ADC_A2 Auxiliary ADC A Input 2 126 AUX_ADC_B1 Auxiliary ADC B Input 1 125 AUX_ADC_B2 Auxiliary ADC B Input 2 127 AUX_ADC_REF Auxiliary ADC Reference Pin No. Mnemonic Function Receive Pins 68/70–79 D0A to 10-/12-Bit ADC Output of D9A/D11A Receive Channel A 80/82–91 D0B to 10-/12-Bit ADC Output of D9B/D11B Receive Channel B 92 RxSYNC Synchronization Clock for Channel A and Channel B Rx Paths 98, 99, AVDD Analog Supply Pins 104, 105, 117, 118, 123, 124, 100, 103, AGND Analog Ground Pins 106, 109, 110, 112, 113, 116, 119, 122, 101 REFT_B Top Reference Decoupling for Channel B ADC 102 REFB_B Bottom Reference Decoupling for Channel B ADC 107 VIN+B Receive Channel B Differential (+) Input 108 VIN–B Receive Channel B Differential (�) Input 111 VREF Internal ADC Voltage Reference 114 VIN–A Receive Channel A Differential (�) Input 115 VIN+A Receive Channel A Differential (+) Input 120 REFB_A Bottom Reference Decoupling for Channel A ADC 121 REFT_A Top Reference Decoupling for Channel A ADC Transmit Pins 18, 20 AVDD Analog Supply Pins 23, 32 19, 24, AGND Analog Ground Pins 27, 28, 31 21 REFIO Reference Output, 1.2 V Nominal 22 FSADJ Full-Scale Current Adjust 25 IOUT–A Transmit Channel A DAC Differential (�) Output 26 IOUT+A Transmit Channel A DAC Differential (+) Output 29 IOUT+B Transmit Channel B DAC Differential (+) Output 30 IOUT–B Transmit Channel B DAC Differential (�) Output 37–48/50 Tx11/Tx13 12-/14-Bit Transmit DAC Data to Tx0 (Interleaved Data when Required) 51 TxSYNC Synchronization Input for Transmitter 62 MODE/ Configures Default Timing Mode, TxBLANK* Controls Tx Digital Power Down *The logic level of the Mode/TxBLANK pin at power up defines the default timing mode; a logic low configu