Amplifier_Report

S-Band Power Amplifier Design Report Requirements: Amplifier type: Gallium Nitride Power Amplifier Transistor MAGX-00035-015000P_28 Operating frequency: 2.8 GHz Average RF power gain: >10dB Output P1dB: Larger than 40dBm Input return loss: >19dB Substrate material: Rogers RO4003, = 3.55, 8 mil thickness substrate and 0.5 oz copper The procedures to design a power amplifier can be summarized as follows, 1) Stability test of the transistor 2) Bias network design and optimization 3) Input and output design and optimization 4) Harmonic Balance Simulation or XDB simulation I. Stability Test As long as the stability factor is larger than unity and stability measurement is positive, the transistor is unconditionally stable. Fig. 1 Stability test The results of StabFact1 and StabMeas are: Fig. 2 Stability factor Fig. 3 Stability measurement As the StabFact is larger than Unity and StabMeas is positive, so this transistor is unconditionally stable, and we don’t need to take other measures. II. Bias network design and optimization Because we use HEMT type transistor, here I use FET Curve Tracer to find the Bias point. Fig. 4 DC curve trace The result of this DC curve-tracer is: Fig. 5 DC characteristics Because we use VDD=28 V, Idq=35 mA S parameters, so here I choose the Bias point Vds=3.75 V, and Ids=35 mA. Then we can use Transistor Bias Utility to design the Bias circuit. Fig. 6 SmartComponent for bias point design Then ‘Push into Hierarchy’ can give us the ADS-designed bias circuit, as shown below, Fig.7 DA_FETBias1 after ‘Push into Hierarchy’ So the bias circuit now becomes: Fig. 8 Bias circuit As we can see, Id is 36.1 mA, so we have to optimize R1, R2 and R3 to get the desired current 35mA. Fig. 9 Optimized Bias Circuit After optimization, the desired current is obtained now. III. Input and output design and optimization Here I use SSMatch smart component to design the matching network. Fig. 10 Smartcomponent DA_SSMatch for impendance matching The input impedance is 2.7+j*2.774 Ohm, and I will match it to 50 Ohm. After ‘Push into hierarchy’, the designed iuput matching network is: Fig. 11 input matching network Similarly, the output matching network can be designed using SSmatch. Then the circuit becomes, Fig. 12 Power amplifier Circuit The figure above is the circuit I designed. I have to mention that L1 and L2 are decoupling inductors, and C1 and C2 are decoupling capacitors. In order to meet the requirements of input return loss and gain, we usually have to optimize the length of TL2, TL3, TL5 and TL6. Two goals have been set here: one for S(1,1), and the other for S(2,1). After optimization, we can get the following results: Fig. 13 S-Parameters of Final design We can see that at the operating frequency 2.8 GHz, the input return loss is better than 19dB, the gain is larger than 10dB between 2.7 GHz and 2.9 GHz. 4) Harmonic Balance Simulation or XDB simulation As P1dB larger than 40dBm is required, XDB simulation is first used to find the P1dB. Fig. 14 XDB simulation Unfortunately, XDB simulation cannot find P1dB for this project. Fig. 15 Result of XDB simulation I use Harmonic Balance (HB) Simulation to check what’s going on. Fig. 16 HB simulation Fig. 17 Result of HB simulation As we can see when frequency is 2.9 GHz, there is a perfect linear relation between input power Pin and output power Pdel_dBm, and the gain Gp is about 11dBm. That’s because no nonlinear component is used in this circuit (only S- parameters are used). So we don’t need to worry about P1dB in this case. So Fig. 12 is my final design and the S parameters of the design are shown in Fig. 13. The design meets all the requirements. Resources: 【1】ADS 2008 射频电路设计与仿真实例 【2】ADS射频电路设计基础与典型应用