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首页 Xilinx__ISE_12.1教程

Xilinx__ISE_12.1教程.pdf

Xilinx__ISE_12.1教程

落木萧条
2013-05-04 0人阅读 举报 0 0 暂无简介

简介:本文档为《Xilinx__ISE_12.1教程pdf》,可适用于IT/计算机领域

ISEInDepthTutorialUG(v)April,ISEInDepthTutorialUG(v)April,ISEInDepthTutorialwwwxilinxcomUG(v)April,Xilinxisdisclosingthisuserguide,manual,releasenote,andorspecification(the"Documentation")toyousolelyforuseinthedevelopmentofdesignstooperatewithXilinxhardwaredevicesYoumaynotreproduce,distribute,republish,download,display,post,ortransmittheDocumentationinanyformorbyanymeansincluding,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withoutthepriorwrittenconsentofXilinxXilinxexpresslydisclaimsanyliabilityarisingoutofyouruseoftheDocumentationXilinxreservestheright,atitssolediscretion,tochangetheDocumentationwithoutnoticeatanytimeXilinxassumesnoobligationtocorrectanyerrorscontainedintheDocumentation,ortoadviseyouofanycorrectionsorupdatesXilinxexpresslydisclaimsanyliabilityinconnectionwithtechnicalsupportorassistancethatmaybeprovidedtoyouinconnectionwiththeInformationTHEDOCUMENTATIONISDISCLOSEDTOYOU“ASIS”WITHNOWARRANTYOFANYKINDXILINXMAKESNOOTHERWARRANTIES,WHETHEREXPRESS,IMPLIED,ORSTATUTORY,REGARDINGTHEDOCUMENTATION,INCLUDINGANYWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ORNONINFRINGEMENTOFTHIRDPARTYRIGHTSINNOEVENTWILLXILINXBELIABLEFORANYCONSEQUENTIAL,INDIRECT,EXEMPLARY,SPECIAL,ORINCIDENTALDAMAGES,INCLUDINGANYLOSSOFDATAORLOSTPROFITS,ARISINGFROMYOURUSEOFTHEDOCUMENTATION©Xilinx,IncXILINX,theXilinxlogo,Virtex,Spartan,ISE,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountriesAllothertrademarksarethepropertyoftheirrespectiveownersISEInDepthTutorialwwwxilinxcomUG(v)April,Preface:AboutThisTutorialAbouttheInDepthTutorialTutorialContentsTutorialFlowsHDLDesignFlowSchematicDesignFlowImplementationOnlyFlowAdditionalResourcesChapter:OverviewofISESoftwareSoftwareOverviewProjectNavigatorInterfaceDesignPanelViewPaneHierarchyPaneProcessesPaneFilesPanelLibrariesPanelConsolePanelErrorsPanelWarningsPanelErrorNavigationtoSourceErrorNavigationtoAnswerRecordWorkspaceDesignSummaryReportViewerUsingProjectRevisionManagementFeaturesUnderstandingtheISEProjectFileMakingaCopyofaProjectUsingtheProjectBrowserUsingProjectArchivesCreatinganArchiveRestoringanArchiveChapter:HDLBasedDesignOverviewofHDLBasedDesignGettingStartedRequiredSoftwareOptionalSoftwareRequirementsVHDLorVerilogInstallingtheTutorialProjectFilesStartingtheISESoftwareCreatingaNewProjectStoppingtheTutorialDesignDescriptionTableofContentswwwxilinxcomISEInDepthTutorialUG(v)April,InputsOutputsFunctionalBlocksDesignEntryAddingSourceFilesCorrectingHDLErrorsCreatinganHDLBasedModuleUsingtheNewSourceWizardandISETextEditorUsingtheLanguageTemplatesAddingaLanguageTemplatetoaFileCreatingaCOREGeneratorSoftwareModuleCreatingthetimerpresetCOREGeneratorSoftwareModuleInstantiatingtheCOREGeneratorSoftwareModuleintheHDLCodeCreatingaDCMModuleUsingtheClockingWizardInstantiatingthedcmMacroVHDLDesignInstantiatingthedcmMacroVerilogSynthesizingtheDesignSynthesizingtheDesignUsingXSTEnteringSynthesisOptionsSynthesizingtheDesignUsingtheRTLTechnologyViewerSynthesizingtheDesignUsingSynplifySynplifyProSoftwareEnteringSynthesisOptionsandSynthesizingtheDesignExaminingSynthesisResultsSynthesizingtheDesignUsingPrecisionSynthesisEnteringSynthesisOptionsandSynthesizingtheDesignUsingtheRTLTechnologyViewerChapter:SchematicBasedDesignOverviewofSchematicBasedDesignGettingStartedRequiredSoftwareInstallingtheTutorialProjectFilesStartingtheISESoftwareCreatingaNewProjectStoppingtheTutorialDesignDescriptionInputsOutputsFunctionalBlocksDesignEntryAddingSourceFilesOpeningtheSchematicFileintheXilinxSchematicEditorManipulatingtheWindowViewCreatingaSchematicBasedMacroDefiningthetimecntSchematicAddingIOMarkersAddingSchematicComponentsCorrectingMistakesDrawingWiresAddingBusesISEInDepthTutorialwwwxilinxcomUG(v)April,AddingBusTapsAddingNetNamesCheckingtheSchematicSavingtheSchematicCreatingandPlacingthetimecntSymbolCreatingthetimecntSymbolPlacingthetimecntSymbolCreatingaCOREGeneratorSoftwareModuleCreatingthetimerpresetCOREGeneratorSoftwareModuleCreatingaDCMModuleUsingtheClockingWizardCreatingthedcmSymbolCreatinganHDLBasedModuleUsingtheNewSourceWizardandISETextEditorUsingtheLanguageTemplatesAddingaLanguageTemplatetoaFileCreatingSchematicSymbolsforHDLModulesPlacingthestatmach,timerpreset,dcm,anddebounceSymbolsChangingInstanceNamesUsingHierarchyPushPopSpecifyingDeviceInputsOutputsAddingInputPinsAddingIOMarkersandNetNamesAssigningPinLocationsCompletingtheSchematicChapter:BehavioralSimulationOverviewofBehavioralSimulationFlowModelSimSetupModelSimPE,SE,andDEModelSimXilinxEditionISimSetupGettingStartedRequiredFilesDesignFiles(VHDL,Verilog,orSchematic)TestBenchFileSimulationLibrariesXilinxSimulationLibrariesUpdatingtheXilinxSimulationLibrariesMappingSimulationLibrariesinthemodelsiminiFileAddinganHDLTestBenchAddingtheTutorialTestBenchFileVHDLSimulationVerilogSimulationBehavioralSimulationUsingModelSimLocatingtheSimulationProcessesSpecifyingSimulationPropertiesPerformingSimulationAddingSignalsAddingDividersRerunningSimulationAnalyzingtheSignalswwwxilinxcomISEInDepthTutorialUG(v)April,SavingtheSimulation

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