Fairchild__non-isolation_buck_solution_for_LED_lighting_application_theory_and_design_tips_final

Click to add presentation title Click to edit Master subtitle Click to add date Company Confidential Fairchild non-isolation buck solution for LED lighting application theory and design tips (飞兆半导体不隔离降压式LED照明 方案 气瓶 现场处置方案 .pdf气瓶 现场处置方案 .doc见习基地管理方案.doc关于群访事件的化解方案建筑工地扬尘治理专项方案下载 原理和 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 技巧） Scott Lu/卢文统 Scott.lu@fairchildsemi.com 13823607349 Fairchild PCIA Technical Support Center_ShenZhen Dec 2012 2 1， LED Lighting definition and market trend (LED 照明的定义和市场趋势） 2， MR/GU10/E14/E17 lighting design challenge (MR/GU10/E14/E17 设计挑战） 3，Fairchild non isolation buck solution_FL7701 Key Features (飞兆半导体不隔离方案_FL7701的主要特性） 4，basic operation （基本工作方式） 5，Inductor design （电感参数设计） 6， design tips （设计技巧） 7,demo performance (单模板效果） Content (主要内容） 3 1， LED Lighting definition and market trend (LED 照明的定义和市场趋势） Lamp Type MR(11/13/16/18) GU10 A19(E14/26) R/PAR(16/20/30/38) Input 12/24VAC or DC AC Line AC Line AC Line Socket GU5.3 - 2Pin GU10 - 2Pin E14/E26/27 - Screw E26/27 - Screw Power 1~8W 1~8W 1~20W 3~30W Dimension D:50, L:52, B:5.3[mm] D:50, L:60, B:10[mm] D:40, L:100, E:14[mm] D:60, L:110, E:26[mm] D:50~120, L:64~130 E:26[mm] Strong point: Re usable the existing facilities higher efficiency than halogen lamp Weak point: Poor system efficiency No PFC and THD Advantage: Higher efficiency than MR16 LED Lighting and Halogen lamp Meet PFC & THD requirement 4 2， MR/GU10/E14/E17 lighting design challenge (MR/GU10/E14/E17 设计挑战） Design Challenge • Small driver PCB space : • Round Type : 30mm diameter, Vertical Type : smaller than 30X20mm • Need to add Input stage – Filter, Bridge diode, Capacitor & etc. • PF & THD requirements ≥0.9 for >5W for commercial applications some customer have this requirement even Pout is 3W • Dimming function implementation LED Module 50mm Driver Board 30mm 20mm 30mm 36mm LED Module Driver Board 25mm 12mm 25mm • No flicker/Shimmer for Phase cut dimmer • New dimming techniques 5 3，Fairchild non isolation buck solution_FL7701 Key Features (飞兆半导体不隔离方案_FL7701的主要特性） • Smart Non-isolated PFC Buck LED Driver: FL7701/FLS0116 • Key Features : • FL7701 (controller), FLS0116 (controller+Mosfet) • No Transformer • No electrolytic capacitor for Input, Output, & VDD • No VDD supply for IC • Digital PFC function (>0.9) • Automatic line voltage detection • AC-DC & DC-DC Inputs - Automatic Convertible • Universal Input Range (85Vac-277Vac) • Constant output current (Peak current ±3%) • Protections • OLP (Open LED Protection) • SLP (Short LED Protection) • TSD (Thermal Shut Down) • Small package outline : 8SOP • Evaluation Board Example: LED L FAN7701 OUT HV EMI filterBD CS GND VCC RT ADIM C1 C2 L1 L2 D1 R1 R2 R3 D2 C3 C4 FLS0116 AC Input 85V-265V 4 3 2 1Vcc 6 7 8 RT HV Gate ADIM N.C 5 F L 7 7 0 1 CS GND 4 3 2 1CS 7 8 ADIM DRAIN Vcc HV 5 F L S 0 1 1 6 RT GND FL7701 – 3W FLS0116– 3W 6 PFC Block Buck PFC PFC Block Boost PFC PFC Block Buck- Boost PFC Input Current Inductor Average Current VLED ILED 0 Π Input Voltage Inductor Current= Input Current Inductor Average Current VLED ILED 0 Π Input Voltage VLED Inductor CurrentILED 0 Π Inductor Average Current Input Voltage VLED ILED 0 Π With Output Capacitor Without Output Capacitor Without Output Capacitor With Output Capacitor VLED ILED 0 Π Without Output CapacitorWith Output Capacitor Without Output Capacitor With Output Capacitor VLED ILED 0 Π Without Output CapacitorWith Output Capacitor Without Output Capacitor With Output Capacitor 4，basic operation （基本工作方式） 4.1PFC Basic Topology in Non-Isolation Topology 7 7 ZCD S R QOSC LEB 9V + - TSD VREF UVLO Ref. Generator N Y Get? DC 45kHz LEB : Leading Edge Blanking AC input LED EMI FILTER D1 D2 D3 D4 FRD FLS0116 VDD AC input LED D1 D2 D3 D4 FRD AC input LED D1 D2 D3 D4 FRD AC input LED D1 D2 D3 D4 FRD AC input LED D1 D2 D3 D4 FRD • Basic BUCK topology • Consist of DC-DC Converter - Input : DC Voltage - Output : DC Voltage • Move the MOFET high side to low side. • Consist of DC-DC Converter - Input : DC Voltage - Output : DC Voltage • Remove the Capacitor. • Consist of DC-DC Converter - Input : DC-pulse Voltage - Output : DC-pulse Voltage FL7701 Application Circuit 4，basic operation （基本工作方式） 4.1PFC Basic Topology in Non-Isolation Topology 8 GND Soft start Counted 7 period RT Gate Driver OUT CS DSG Oscillator HV QR S - + TSD LEB VDD ZCD8V/9V UVLO - + DAC 6bit Digital Leading Edge Blanking Digital Sine-wave Generator Reference Zero Crossing Detection Digital to Analog Converter ADIM N.C JFET AOCP 12uA Vref 1 - + Gain (Peak*2) #. LED current distortion is occur at some condition (high input and light Load) -In FL7701 topology, GATE-duty is proportional to Load(LED count) and, inverse- proportional to input -Min Ton is combination of LEB-time and propagation delay - Can reduce Min. duty by reducing operating frequency (with same Min. Ton & Ind) VBulk T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency t Duty t ILED t Duty Maximum = 50% VBulk T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency t Duty t ILED t Duty Maximum = 50% Duty Minimum = LEB Time+TPDDuty Minimum = LEB Time+TPD Over Current Vcc=1uF 4，basic operation （基本工作方式） 4.2 AOCP function 9 9 GND Soft start Counted 7 period RT Gate Driver OUT CS DSG Oscillator HV QR S - + TSD LEB VDD ZCD8V/9V UVLO - + DAC 6bit Digital Leading Edge Blanking Digital Sine-wave Generator Reference Zero Crossing Detection Digital to Analog Converter ADIM N.C JFET AOCP 12uA Vref 1 - + Gain (Peak*2) S w itc h in g F re q u en c y (k H z) 500 400 300 200 100 0 0 10 20 30 40 Minimum Duty (%) 5025 600 5 15 35 45 23.5% 0.047% 91002132 1 45   . f R kHzopenpinR sw t t S w itc h in g F re q u en c y (k H z) 500 400 300 200 100 0 0 20 40 60 80 RT Resistor (KΩ) 10050 600 10 30 70 90 17.3kHz 2.5kΩ If there is not connected Rt resistance to the operation frequency is 45kHz. FL7701 has been set 50% of the maximum duty in order to prevent sub-harmonic. The minimum duty is determined by the TPD and LEB time. So when increase the switching frequency, minimum duty ratio is increase. 4，basic operation （基本工作方式） 4.3 Frequency operation 10 GND Soft start Counted 7 period RT Gate Driver OUT CS DSG Oscillator HV QR S - + TSD LEB VDD ZCD8V/9V UVLO - + DAC 6bit Digital Leading Edge Blanking Digital Sine-wave Generator Reference Zero Crossing Detection Digital to Analog Converter ADIM N.C JFET AOCP 12uA Vref 1 - + Gain (Peak*2) Operating range of analog dimming pin is 0.5V ~ 3.5V. If there is not inject dc signal to the operation dimming is full. That time adim pin voltage is 3.5V. It’s pin use to 0 to 10 dimming. 4，basic operation （基本工作方式） 4.4 Adim function 11 GND Soft start Counted 7 period RT Gate Driver OUT CS DSG Oscillator HV QR S - + TSD LEB VDD ZCD8V/9V UVLO - + DAC 6bit Digital Leading Edge Blanking Digital Sine-wave Generator Reference Zero Crossing Detection Digital to Analog Converter ADIM N.C JFET AOCP 12uA Vref 1 - + Gain (Peak*2) Vdrain T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency t Vcc t ZCD t Vdrain t ILED t Vdrain t Vcc t ZCD t Vdrain t ILED t T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency Vbridge ILED DAC T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency JFET Voltage Bridge Diode Output Voltage Input Voltage Peak ZCD 32 bit digital step 64 bit digital step LED Current Peak t t t t 15.5V VDD 15.5V Vdd Charging Voltage LED FUSE D1 D2 D3 D4 FRD Lm C VDD HV GND FL7701 Varistor N.CAdimR RT R R CS GATE 4，basic operation （基本工作方式） 4.4 ZCD function 12 12 Step 1: Minimum duty ratio The FL7700 has prefixed internal duty ration range between 1% and 50% and its range will be depended on the input voltage and LED numbers in its string. Where, η is efficiency of system, Vin(max) is maximum input voltage, Vf is forward drop voltage of LED and n is LED number in series connection. Step 2: Maximum duty ratio The FL7700 has 50% maximum duty cycle for prohibiting sub-harmonic problem. Step 3: Inductance Step 4: Average LED current (max)in f min V Vn D     (min)in f max V Vn D     ]H[ if )D(Vn L )D( i TV L V)D( i DT L DVV*)VV( i DT LVV DT i L rips minf m rip so m in rip s m inooin rip s moin s rip m              1 1 1 Average LED Current Current Limit 350mA ton toff Dmin 1-Dmin Average LED Current Current Limit 350mA ton toff Dmin 1-Dmin ∆i ri p ∆i ri p (a) DCM Mode (a) CCM Mode ∆i c o n 2 2 rip )peak(o)rms(o rip)peak(ocon rip con)peak(o i II iIi* i iI       5，Inductor design （电感参数设计） 13 Step 5: Wire of inductor Typically, the inductor wire is used enamel wire. The current density of enamel is 420 and that unit is A/cm2. If the diameter of wire is Φ, area of circle can be defined The diameter of wire(Φ) can be defined Step 6: Diode and Bypass capacitor The duration of the leading edge current spike time can be estimated as: In order to avoid false triggering of the current sense comparator, Cp must be minimized in accordance with the following expression: Where TBLANK(min) is the minimum blanking time of 350ns, and Vin(max) is the maximum instantaneous input voltage. 420 420 2 22 L)peak(o Icm cm I cm A  2 2 22 10 422      cm)mm(wireofArea )mm( IL 2 10420 2     bypassLPCBdrainprr set p(max)in spike CCCCC*t I CV T      (max)in rr(min)BLANKset p V tTI C   LED (14EA/36V) BD FRD Lm C VDD HV GND MB6S 600V 0.5A 4mH 1uF 100nF ES3J 600V3A FL7701 BdimAdimR RT 20k R 1 R 1k CS GATE B y p a s s 5，Inductor design （电感参数设计） 14 When change the input voltage, 1. duty ratio is change. 2. current ripple is change. 3. LED current is change So this grape is calculated LED current change via input voltage change. Input voltage is determined the capacity of the condenser. Minimum duty calculation does not account for the LEB time. So this tool can be calculated less than LEB time. Target LED RMS current Input voltage waveform at 60Hz Duty ratio about switching frequency Efficiency is used to calculate the input current. Number of LED is determined the output voltage Target LED Peak current Switching frequency is used to calculate the inductance. 5，Inductor design （电感参数设计） 15 6,Design tips(设计技巧） 6.1 Flicker : ZCD Err Can see the LED current variation due to changing ZCD detection point. Current swing to the left or right. Drain Voltage LED Current Vcc Voltage Flicker ZCD error occurs due to the input voltage is vibrating. That time, can see the flicker. 1. In buck topology, input current is discontinues. 2. Requires a large size of the EMI filter. 3. Large size of the EMI filter causes vibration of the input voltage. 4. Vibration of the input voltage causes vibration of Vcc voltage. 5. Vibration of Vcc voltage causes ZCD error. Solution : Apply to the Vcc capacitor at least over 2uF. 16 ADIM ILED VCC Vrec 1) Issue - Occur flicker caused by IC-reset under some worst SET condition 2) Root Cause - Occur mis-UVLO signal by negative JFET current-flow - UVLO block is located nearby JFET 3) Solution - Connect series-Resistor or blocking-diode at HV-pint SET-level SET condition 1. HV pin connected high line side. 2. Lower LED voltage ( Lower output voltage ) 3. EMI filter is not optimized LED FUSE D1 D2 D3 D4 FRD Lm C VDD HV GND FL7701 Varistor N.CAdimR RT R R CS GATE 6,Design tips(设计技巧） 6.1 Flicker : Re-set 17 Vbridge Vdrain ILED Vin VLED DAC IFRD IMOSFET Iinput T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency Vdd Charging Voltage Bridge Diode Output Voltage 13V Input Voltage Peak 7V ZCD Π 2Π 3Π 4Π 32 bit digital step 64 bit digital step Input Voltage Peak t t t t t t t t t t ICap t Vbridge Vdrain ILED Vin VLED DAC IFRD IMOSFET Iinput T/2 = 1/(Input Frequency * 2) T = 1/Input Ferquency Vdd Charging Voltage Bridge Diode Output Voltage 13V Input Voltage Peak 7V ZCD Π 2Π 3Π 4Π 32 bit digital step 64 bit digital step Input Voltage Peak Input Voltage Peak t t t t t t t t t t AC input 85Vac~265Vac LED (14EA/36V) FUSE FRD Lm C VDD HV GND MB6S 600V 0.5A 4mH 220nF ES3J 600V3A FL7701 Varistor 250V 1A 7D471 N.C Adim R RT 20k R 2.75 R 1k CS GATE EMI FILTER 100nF 1mH 1mH 22nF R 1k 1N4148 100uF C AC input 85Vac~150Vac LED (14EA/36V) FUSE FRD Lm C VDD HV GND MB6S 600V 0.5A 4mH 470nF ES3J 600V3A FL7701 Varistor 250V 1A 7D471 N.C Adim R RT 20k R 2.75 R 1k CS GATE EMI FILTER 100nF 1mH 1mH 22nF R 1k 1N4148 Without Output Capacitor With Output Capacitor 6,Design tips(设计技巧） 6.3, connect output capacitor 18 0 100 200 300 400 500 18 • 1. Zero Current Zone 66.1V 57.7V 36V LED Voltage Drain Voltage LED Current LED voltage FRD L C VDD DRAIN GND Input voltage(Vin) LFin VVnV  FVn + + We can estimate LED current if we assume LED voltage is constant. (Vin-nVF-VL). Low input condition: High Low, the dead zone ↑. Yellow line : 1. the LED current flow at high input condition. 2. Need a certain voltage difference 3. Same procedure, we can assume at low input condition. 4. The LED current shape change, Not same as high input condition Input voltage time High input Low input GND FVn  Ignore the voltage drop of inductor 2. LED Current Curve 6,Design tips(设计技巧） 6.4 Reduce LED current due to input voltage 19 Performance in 110Vac Performance in 230Vac LED # Power(W) LED # Power(W) AC input 85Vac~150Vac LED (14EA/36V) FUSE FRD Lm C VDD HV GND MB6S 600V 0.5A 4mH 470nF ES3J 600V3A FL7701 Varistor 250V 1A 7D471 N.C Adim R RT 20k R 2.75 R 1k CS GATE EMI FILTER 100nF 1mH 1mH 22nF R 1k 1N4148 7,demo performance (单模板效果） Click to add presentation title Click to edit Master subtitle Click to add date Thank You twitter.com/fairchildSemi www.facebook.com/FairchildSemiconductor www.fairchildsemi.com/engineeringconnections