10-Sliding Modes

Chapter 10 Sliding Modes Domingo Biel and Enric Fossas 10.1 Introduction In 1974, J. R. Wood [26] wrote a report for the National Aerospace and Space Ad- ministration about power conversion in electrical networks. Although there is no reference there to sliding mode control, the author analysed ideal DC–DC power converters using Filippov1 methods [6], hence designing discontinuous control laws and obtaining ideal sliding dynamics. It is worth reproducing here a few sentences: The line x + βx˙ = 0 is called switching line, and we need to consider carefully what happens at this line. . . . However, because of the chattering behaviour along switching lines which is observed in practice, . . . In addition, the designer will want to include either a small fixed delay or a small amount of hysteresis, in order to limit the switching frequency of the power transistor because of efficiency considerations . . . The key concepts of discontinuous analysis and design for DC–DC conversion were already in Wood’s paper, as well as the drawbacks this discontinuous design involves. Among the first papers dealing with DC–DC conversion in a sliding mode frame- work, we must quote [2] and [25]. The English version of the book Sliding Modes and their Application in Variable Structure Systems by Utkin had been published by MIR in 1978 [24] and, from 1983 to 1985, a young Yugoslavian professor, A. Sa- banoviç, visited Caltech when R. Venkataramanan worked on his thesis. In [25], DC–DC converters were explored in the light of sliding mode and equivalent control 1The seminal paper by Filippov had been published by AMS Translations ten years before. D. Biel (�) · E. Fossas Institute of Industrial and Control Engineering, Universitat Politècnica de Catalunya, Avda. Diagonal, 647, pl. 11, 08028 Barcelona, Spain e-mail: biel@eel.upc.edu E. Fossas e-mail: enric.fossas@upc.edu F. Vasca, L. Iannelli (eds.), Dynamics and Control of Switched Electronic Systems, Advances in Industrial Control, DOI 10.1007/978-1-4471-2885-4_10, © Springer-Verlag London Limited 2012 299 300 D. Biel and E. Fossas concepts to arrive at large-signal and small-signal models; and experimental results were presented as well. The paper includes a sliding mode equivalent representa- tion of DC–DC duty ratio controllers that allows an easy and elegant analysis; the ramp generator defining the switching frequency was incorporated as an integrator plus unitary feedback. Linear (buck) and nonlinear elementary converters (boost, buck–boost) were analysed. A switching line based on a proportional–derivative (PD) design in the output-error were synthesised for the buck converter, while for bilinear converters, two nested loops were reported: an inner current sliding mode programmed loop and an outer proportional–integral (PI) to tune the appropriate current reference to regulate the output voltage. Practical considerations were also reported. From this time too there are Hebertt Sira-Ramírez’s papers [17, 18, 20] where DC–DC conversion was reformulated as an application of variable structure theory and sliding regimes to study energy transfers between dynamic storage elements in lossless bilinear networks. In Europe (Genoa and Toulouse), DC–AC conver- sion was analysed in sliding domain at the end of the 1980s by Carpita et al. [5] and Boudjema et al. [3]. The implementation of these designs entails considering two problems already reported by Wood and Venkataramanan et al., namely fixed switching frequency and chattering reduction. Several techniques are reported in the literature to obtain a fixed switching fre- quency. For instance, processing the equivalent control through a pulse-width mod- ulation (PWM) [18] and the addition of a hysteresis cycle to the sliding mode con- trol comparator [2, 4] and [13]. Several approaches [10, 15] consider a variable bandwidth hysteresis cycle, the implementation of which depends on the system pa- rameters and is complex. Other electronic implementations of quasi-sliding controls are reported in [14, 16], where the fixed switching frequency is synchronised by an external signal defined by a periodic bipolar pulse train. Finally, in [7], the duty cy- cle is defined so that the sliding surface average is zero in each commutation period. Readers interested in a more in depth description of these methods are referred to [1] and references therein. Chattering reduction was also considered in [7] and more recently in [9] by V. Utkin and co-workers. They proposed a new challenge in multi-phase converter systems that allows reducing chattering to desired level under any given switching frequency. This can be achieved by providing an appropriate phase shift to imple- ment the so-called “ripple cancellation” or “harmonic cancellation” method. There are several papers dealing with PWM-based SMC [8, 12, 21, 22] and de- serving specific mention. They are based on a result by H. Sira-Ramírez [19] which states that in the limit, i.e. when the switching period tends to zero, the equivalent control is equal to the duty cycle. However, in most of these papers, the switch ref- erence signal appears to be designed in a classic linear control framework and SMC is not used in implementation issues. The remaining part of this chapter is organised as follows: in the next section, the designing of a sliding mode controller for a boost converter [25] is presented, while a design based on the averaging technique is presented in Sect. 10.3. The new chattering reduction method by Utkin is described in Sect. 10.4 and experiments are 10 Sliding Modes 301 Fig. 10.1 Buck converter topology reported as well. The chapter closes by drawing some conclusions from the work presented. 10.2 Sliding Mode Control for DC–DC Power Converters The aim of DC–DC power conversion is to obtain a regulated, continuous voltage (or current) at the load terminals. The power regulator consists of a power stage composed of semiconductors, inductors and capacitors, and a control stage com- monly based on the processing of an error signal (the difference between a refer- ence and an output voltage) and a voltage–time conversion through a PWM. The control objective is to achieve a regulated robust output voltage with good dynamic performance. 10.2.1 Electrical and State Space Models The ideal2 buck, boost and buck–boost topologies feeding a resistive load are de- picted in Figs. 10.1 and 10.2. The converter dynamics is modelled by two state variables, i.e. i, the inductor current, and v, the capacitor voltage3, and by the con- trol input u ∈ {0,1}, which describes the position of a bidirectional switch. The state equations of the converter are listed below, where E is the DC-input voltage, L and C, the inductor and the capacitor value, respectively, and R, the resistive load. Note that, in the case of the buck–boost converter, there exists an output voltage polarity inversion with respect to the input voltage. 2Without semiconductor, capacitor and inductor losses. 3The capacitor voltage coincides with the output voltage because the resistor losses associated to the capacitor are not considered. 302 D. Biel and E. Fossas Fig. 10.2 Boost and buck–boost converter topologies A general model for buck, boost and buck–boost converters can be written as d dt ( Li Cv ) = ( 0 −1 + λu 1 − λu − 1 R )( i v ) + ( E(1 + γ (u − 1)) 0 ) . (10.1) Specific models can be obtained by selecting the parameters λ and γ as fol- lows: λ = 0, γ = 1 for the buck converter, λ = 1, γ = 0 for the boost converter and λ = 1, γ = 1 for the buck–boost converter: Therefore, DC–DC switching converters can be modelled as bilinear systems, and represented as variable structure systems. 10.2.2 Sliding Mode Control Analysis and Design Output voltage regulation is the general control objective in DC–DC power con- version. A naive approach would be to design the action of the switch, the control action, based uniquely on the output voltage error (direct control). This approach will not be successful in general. An indirect approach, based on both the output voltage and the inductor current, is needed to achieve robust regulation. SMC strategies for the DC–DC conversion problem via direct and indirect con- trol will be considered here. Starting from a switching surface, the transversality condition is checked and the equivalent control is derived. The latter is used to ob- tain the ideal sliding dynamics and, when the ideal sliding dynamics are stable, to deduce the sliding domain. For further details on the subject, the reader is referred to [17, 23, 25]. 10 Sliding Modes 303 10.2.2.1 Direct Output Voltage Control The direct output voltage control corresponds to the use of the switching sur- face σv = v − Vref, (10.2) where Vref > 0 is a constant voltage reference. Note that the transversality condition is not fulfilled in the buck converter case (λ = 0). For the other cases, (λ = 1 and i �= 0), the equivalent control and the ideal sliding dynamics are given by ueq = i − Vref R i , (10.3) { v = Vref, d dt i = 1Li (Ei − VrefR (Eγ + Vref)). (10.4) The ideal sliding dynamics has an equilibrium point at (i∗,Vref), with i∗ = (Eγ + Vref)Vref RE . Its stability is analysed by the first linear approximation, namely d dt iˆ = R L E2 Vref(Eγ + Vref) iˆ, (10.5) where iˆ = i − i∗. Since R L E2 Vref(Eγ + Vref) > 0, the equilibrium point is unstable; hence direct voltage regulation results in instability of the inductor current. 10.2.2.2 Indirect Output Voltage Control With the so-called indirect output voltage control, the switching surface is chosen as σi = i − Iref, (10.6) where Iref denotes a constant inductor current reference. 304 D. Biel and E. Fossas Then, the equivalent control and the ideal sliding dynamics are given by ueq = v − E(1 − γ ) Eγ + λv , (10.7){ i = Iref, d dt v = 1C (Iref − λIref( v−E(1−γ )Eγ+λv ) − vR ). (10.8) The geometric locus defined by the equilibrium points is described in coordinates (Iref, v∗) with v∗2 + Eγv∗ − EIrefR = 0 for λ = 1, and v∗ = IrefR for λ = 0. Linearising (10.8) around the equilibrium point (Iref, v∗) yields d dt vˆ = 1 C ( −IrefE ( λ Eγ + λv∗ )2 − 1 R ) vˆ, (10.9) where vˆ = v − v∗. Thus, the indirect control results in a stable ideal sliding dynam- ics. The sliding domain on i = Iref resulting from 0 < ueq < 1, assuming E > 0, gives the following sliding domain converter characteristics: • Buck, i = Iref and 0 < v < E; • Boost, i = Iref and 0 < E < v; • Buck–boost, i = Iref and 0 < v, 0 < E. Finally, the switching strategy is defined so that σ 2i qualifies as a Lyapunov func- tion. From Eq. (10.7), d dt σ 2i = σi d dt σi = σi(λv + Eγ )(u − ueq). (10.10) Then, since 0 < ueq < 1 is assumed, u = { 0 if σi(λv + Eγ ) > 0, 1 if σi(λv + Eγ ) < 0. (10.11) In summary, the indirect output voltage control provides output voltage regula- tion presuming the converter states meet the sliding domain conditions. However, the output voltage depends on the load resistance; therefore, these controllers do not produce systems that are robust with respect to load variations. 10 Sliding Modes 305 Fig. 10.3 Classical two loops DC–DC regulator diagram 10.2.2.3 Robustness Two strategies to robustify indirect output voltage control are given here. The first is a specific method for linear systems of relative degree greater than 1 and the second is a PI-type strategy. As for linear systems, by adding higher derivatives of the error, the relative de- gree decreases. For the buck converter, see [25] and [23], a suitable switching surface to be considered is σvr = e + k ddt e, (10.12) where e = Vref − v. This strategy cannot be applied to the boost or to the buck–boost converters be- cause these systems have relative degree 1 and the derivative of the control input would appear in the expression of the equivalent control. Note, in addition, that the derivative of the output voltage (a discontinuous signal) should be processed in the nonlinear converters case. This makes it impossible for designers to use this switch- ing scheme. To avoid processing discontinuities, a high frequency filtering (averag- ing) is used in [11]. A linearising process can alternatively be used, as in [20]. The switching surface σir = i + kee + kvava, (10.13) where e = Vref − v and va satisfies ddt va = e, is a robust alternative. Both switching surfaces σvr and σir can be represented by the block diagram in Fig. 10.3 which highlights two control loops: a fast inner control loop corresponding to the current dynamics and a slow outer control loop which processes the output voltage error. The Gc block is a P (resp., a PI) controller and iˆ is the capacitor (resp., inductor) current for σvr (resp., for σir ). The analysis of the controlled sys- tems (buck, boost and buck–boost), namely checking the transversality condition, 306 D. Biel and E. Fossas computing the equivalent control, the sliding domain, the equilibrium points and their stability is left to the reader. 10.3 Averaging and Pulse-Width Modulation Based Sliding Modes SMC theory presumes an infinite switching frequency when the system operates in sliding mode, however actual switches cannot commute at infinite frequency. At any rate, higher switching frequencies become harmful in some of the applica- tions (the higher the switching frequency, the higher the losses in the converter). Consequently, actual sliding mode controls operate at high, finite, possibly variable frequency, which results in a chattering around the sliding surface. This problem has been tackled through fixed and variable bandwidth hysteresis comparators, by the addition of an external synchronous signal, by the use of equivalent control as duty cycle and through a zero average dynamics (ZAD) control strategy. Readers interested in SMC implementation in power converters are referred to [1]. Most of the works devoted to PWM based sliding mode controllers take ben- efit from a result by H. Sira-Ramírez [19], proving that in the limit, when the switching period tends to zero, the duty cycle is equal to the equivalent con- trol. As for the ZAD strategy [7], the duty cycle is defined so that the average of the sliding surface is zero in each commutation period; that is to say, the controller guarantees 〈 σ(x) 〉 = 1 T ∫ (k+1)T kT σ ( x(τ) ) dτ = 0. (10.14) The ZAD-based duty-cycle design yields chattering reduction and a fixed switching frequency. The ZAD-based duty cycle is defined according to the sampled values of σ and ddt σ . In particular, consider the case σ(x(tk), tk) ≥ 0. Denoting by {u+, u−} the set of discrete values the switch can take (in the next example, u− = 1 and u+ = 0), we then choose u(tk) = u+, getting the following implications: σ ( x(tk), tk ) + T 2 d dt σ ∣∣∣∣ (k,u+) ≥ 0 ⇒ dk = 1, σ ( x(tk), tk ) + T 2 d dt σ |(k,u+) < 0 ⇒ dk = 1 − √√√√ ∣∣ d dt σ |(k,u+) ∣∣ − 2 |σ(x(tk),tk)| T∣∣ d dt σ |(k,u+) ∣∣ + ∣∣ ddt σ |(k,u−) ∣∣ . 10 Sliding Modes 307 Fig. 10.4 Projection of the three dimensional dynamics on the (i, v)-plane On the other hand, in the case σ(x(tk), tk) ≤ 0, we have u(tk) = u− and the following implications: σ ( x(tk), tk ) + T 2 d dt σ ∣∣∣∣ (k,u−) ≤ 0 ⇒ dk = 1, σ ( x(tk), tk ) + T 2 d dt σ ∣∣∣∣ (k,u+) > 0 ⇒ dk = 1 − √√√√ ∣∣ d dt σ |(k,u−) ∣∣ − 2 |σ(x(tk),tk)| T∣∣ d dt σ |(k,u+) ∣∣ + ∣∣ ddt σ |(k,u−) ∣∣ . This methodology is applied here to a boost converter. In order to guarantee robustness with respect to line and load variations, the dynamics are extended by adding the integral of the voltage error, and a switching surface like σir in (10.13) is designed taking ke = −1.2 and kva = −4500. The converter parameters are E = 50 V, L = 20 µH and C = 100 µF. The load resistance varies from 5 � to 40 � and the output voltage reference is set to 100 V. The projection of the state trajectory on the (i, v)-plane is depicted in Fig. 10.4. The trajectory in red corresponds to the ZAD-based duty cycle with a switching frequency of 100 kHz, while the one in blue corresponds to the ideal sliding con- troller. The initial load value of 40 � changes to 5 � when trajectory reaches the equilibrium point. Note that the average of the dynamics in red results in the dy- namics in blue. Nevertheless, the two trajectories show some differences. Namely, the ZAD-based entails a delay because of the synchrony execution of the algorithm and it shows the chattering typical of switched circuits. The ideal sliding dynamics, i.e. the dynamics on the switching surface, is zoomed in Fig. 10.5, blue trajectory. 308 D. Biel and E. Fossas Fig. 10.5 Ideal sliding and ZAD dynamics 10.4 Multiphase Systems and Interleaving The chattering reduction problem has been recently considered using interleaving, a strategy well known in electronics. V. Utkin and co-workers proposed a new methodology in SCM framework that allows reducing chattering to desired level under any given switching frequency [9]. This can be achieved by providing an ap- propriate phase shift to implement the so-called “ripple cancellation” or “harmonic cancellation” method. In this section, this new challenge is implemented on a four- phases, half-bridge buck converter prototype. 10.4.1 Analogue Interleaving and Chattering Reduction Let us consider a system with an inner loop which is in charge of regulating an inner output y by means of a relay as in Fig. 10.6 where the ‘Phase-1’ block corresponds to a relative degree 1, first order transfer function. Hence, d dt s = d dt yref − ddt y = a − Msign(s) (10.15) Fig. 10.6 Inner loop in a single-phase system 10 Sliding Modes 309 Fig. 10.7 A two-phase master–slave system where a = ddt yref + y/τ and M = k0/τ . Note that there is a sliding motion on s = 0 provided that |a| < M . The chattering reduction method proposed in [9] is based on: • A multiphase inner loop instead of a single-phase one, • Modifying the reference appropriately, i.e. taking as a new reference yref0 = yref/m and • Taking benefit of some properties of the Fourier expansions. Two possible schemes, called an m-phase interconnected system and an m-phase master–slave system, were proposed, and the experiments were performed in a four- phase master–slave DC–DC buck converter. Here we summarise the main results by considering for simplicity a two-phase master–slave model which is shown in Fig. 10.7. As in the single phase case, d dt s1 = a − M sign(s1), (10.16) d dt s∗2 = kM [ sign(s1) − sign ( s∗2 )] , (10.17) where s1 = yref0 − y1, (10.18) 310 D. Biel and E. Fossas Fig. 10.8 Periodic s1 dynamics s∗2 = k ∫ M [ sign(s1) − sign ( s∗2 )] dt, (10.19) presuming that the relay gains and the dynamics in the two phases are identical. In Fig. 10.8, the s1 dynamics close to s1 = 0 are sketched. Computing the period T from the figure yields T = T1 + T2 = Δ M − a + Δ M + a = 2ΔM M2 − a2 . (10.20) It is presumed that ddt yref0 and state variables are practically constant, i.e. the domi- nant term in ddt s1 is Msign(s1). In Fig. 10.9, the (s1, s∗2 )-plane for a > 0 is sketched with the vector field values indicated in the corners. From the figure, the phase shift can be written as Tφ = Δ2kM , (10.21) which is equal to the time from changing s∗2 from point (2) to point (3). Fig. 10.9 Periodic (s1, s∗2 ) dynamics 10 Sliding Modes 311 The scheme sketched in Fig. 10.7 allows implementing a phase shift between phases 1 and 2 while the following inequality holds Δ 2kM ( M + |a|) < Δ, (10.22) which is equivalent to M + |a| < 2kM, (10.23) where Δ is the hysteresis width and k and M are the integral and relay gains, re- spectively; see [9] for details. The ideal sliding dynamics in the interconnected system results in y1 = y2 = yref0 . 10.4.1.1 Selection of Phase Number Suppose that a master–slave m-phase linear system is to be designed so that the period of chattering is the