AD9365规格书

RF Agile Transceiver ADI Confidential AD9365 Rev. Sp0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. FEATURES RF transceiver with integrated 12-bit DACs and ADCs Band: 200 MHz to 2.3 GHz Supports TDD and FDD operation Tunable channel BW: <200 kHz to 10 MHz 3 band receiver: 3 differential or 6 single-ended inputs Superior receiver sensitivity with a noise figure < 2.5 dB RX gain control Real-time monitor and control signals for manual gain Independent automatic gain control (AGC) 2 band differential output transmitter Highly linear broadband transmitter TX EVM: ≤−34 dB TX noise: ≤−157 dBm/Hz noise floor TX monitor: ≥66 dB dynamic range with 1 dB accuracy Integrated fractional-N synthesizers 2.5 Hz maximum local oscillator (LO) step size No TX or RX SAW filters required CMOS digital interface APPLICATIONS 3G femtocell base stations Smart grid power meter transceivers FUNCTIONAL BLOCK DIAGRAM AD9365RX1B_P, RX1B_N P1_[D11:D0] P0_[D11:D0] RADIO SWITCHING NOTES 1. SPI, CTRL, P0_[D11:D0], P1_[D11:D0], AND RADIO SWITCHING CONTAIN MULTIPLE PINS. RX1A_P, RX1A_N RX1C_P, RX1C_N TX_MON D A TA IN TE R FA C E RX LO TX LO TX1A_P, TX1A_N TX1B_P, TX1B_N CTRL AUXDACx XTALNAUXADC CTRL SPI D A C GPO PLLs D A C A D C CLK_OUT DAC ADC 10 49 2- 00 1 Figure 1. GENERAL DESCRIPTION The AD9365 is a high performance, highly integrated RF Agile Transceiver™ designed for use in 3G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9365 operates in the 200 MHz to 2.3 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from <200 kHz to 10 MHz are supported. The direct conversion receiver has state-of-the-art noise figure and linearity. The receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9365 also has flexible manual gain modes that can be externally controlled. Two high dynamic range ADCs digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap FIR filters to produce a 12-bit output signal at the appropriate sample rate. The transmitter uses a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best-in-class TX EVM of <−34 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements. The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. All VCO and loop filter components are integrated. The core of the AD9365 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and three real-time I/O control pins. Comprehensive power-down modes are included to minimize power consumption in normal use. The AD9365 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA). AD9365 ADI Confidential Rev. Sp0 | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Current Consumption Specifications ........................................ 7 Absolute Maximum Ratings ............................................................ 8 Reflow Profile ................................................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 12 800 MHz Frequency Band ......................................................... 12 2.3 GHz Frequency Band .......................................................... 16 Theory of Operation ...................................................................... 19 General......................................................................................... 19 Receiver........................................................................................ 19 Transmitter .................................................................................. 19 Clock Input Options .................................................................. 19 Synthesizers ................................................................................. 19 Digital Data Interface................................................................. 20 Enable State Machine ................................................................. 20 SPI Interface ................................................................................ 21 Control Pins ................................................................................ 21 GPO Pins (GPO_3 to GPO_0) ................................................. 21 Auxiliary Converters .................................................................. 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 1/12—Revision Sp0: Initial Version ADI Confidential AD9365 Rev. Sp0 | Page 3 of 24 SPECIFICATIONS VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, all other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/ Comments RECEIVERS, GENERAL Center Frequency 200 2300 MHz Gain Minimum 0 dB Maximum 74.5 dB At 800 MHz 73.0 dB At 2300 MHz, RX1A 72.0 dB At 2300 MHz, RX1B, RX1C Gain Step 1 dB Received Signal Strength Indicator RSSI Range 100 dB Accuracy ±2 dB RECEIVERS, 800 MHz Noise Figure NF 2 dB Maximum RX gain Third-Order Input Intermod- ulation Intercept Point IIP3 −18 dBm Maximum RX gain Second-Order Input Intermod- ulation Intercept Point IIP2 40 dBm Maximum RX gain Local Oscillator (LO) Leakage −122 dBm At RX front-end input Quadrature Gain Error 0.2 % Quadrature Phase Error 0.2 Degrees Modulation Accuracy (EVM) −34 dB 19.2 MHz reference clock Input S11 −10 dB RECEIVERS, 2.3 GHz Noise Figure NF 3 dB Maximum RX gain Third-Order Input Intermod- ulation Intercept Point IIP3 −14 dBm Maximum RX gain Second-Order Input Intermod- ulation Intercept Point IIP2 45 dBm Maximum RX gain Local Oscillator (LO) Leakage −110 dBm At RX front-end input Quadrature Gain Error 0.2 % Quadrature Phase Error 0.2 Degrees Modulation Accuracy (EVM) −34 dB 40 MHz reference clock Input S11 −10 dB TRANSMITTERS, GENERAL Center Frequency 650 2300 MHz Power Control Range 90 dB Power Control Resolution 0.25 dB TRANSMITTERS, 800 MHz Output S22 −10 dB Maximum Output Power 8 dBm 1 MHz tone into 50 Ω load Modulation Accuracy (EVM) −34 dB 19.2 MHz reference clock Third-Order Output Intermod- ulation Intercept Point OIP3 23 dBm Carrier Leakage −50 dBc 0 dB attenuation −32 dBc 40 dB attenuation Noise Floor −157 dBm/Hz 90 MHz offset AD9365 ADI Confidential Rev. Sp0 | Page 4 of 24 Parameter Symbol Min Typ Max Unit Test Conditions/ Comments TRANSMITTERS, 2.3 GHz Output S22 −10 dB Maximum Output Power 7.5 dBm 1 MHz tone into 50 Ω load Modulation Accuracy (EVM) −34 dB 40 MHz reference clock Third-Order Output Intermod- ulation Intercept Point OIP3 19 dBm Carrier Leakage −50 dBc 0 dB attenuation −32 dBc 40 dB attenuation Noise Floor −156 dBm/Hz 90 MHz offset TX MONITOR INPUT (TX_MON) Maximum Input Level 4 dBm Dynamic Range 66 dB Accuracy 1 dB LO SYNTHESIZER LO Frequency Step 1.2 Hz 2.3 GHz, 40 MHz reference clock Integrated Phase Noise 100 Hz to 100 MHz 800 MHz 0.36 ° rms 30.72 MHz reference clock (doubled internally for RF synthesizer) 2.3 GHz 0.37 ° rms 40 MHz reference clock REFERENCE CLOCK (REF_CLK) REF_CLK is the input to the XTALN pin Input Frequency Range 10 80 MHz External oscillator Input Signal Level 1.3 V p-p AC-coupled external oscillator AUXILIARY ADC Resolution 12 Bits Input Voltage Minimum 0.05 V Maximum VDDA1P3_BB − 0.05 V AUXILIARY DAC Resolution 10 Bits Output Voltage Minimum 0.5 V Maximum VDD_GPO − 0.3 V Output Current 10 mA DIGITAL SPECIFICATIONS (CMOS) Logic Inputs Input Voltage High VDD_INTERFACE × 0.8 VDD_INTERFACE V Input Voltage Low 0 VDD_INTERFACE × 0.2 V Input Current High −10 +10 μA Input Current Low −10 +10 μA Logic Outputs Output Voltage High VDD_INTERFACE × 0.8 V Output Voltage Low VDD_INTERFACE × 0.2 V GENERAL-PURPOSE OUTPUTS Output Voltage High VDD_GPO × 0.8 V Output Voltage Low VDD_GPO × 0.2 V Output Current 10 mA ADI Confidential AD9365 Rev. Sp0 | Page 5 of 24 Parameter Symbol Min Typ Max Unit Test Conditions/ Comments SPI TIMING VDD_INTERFACE = 1.8 V SPI_CLK Period tCP 20 ns Pulse Width tMP 9 ns SPI_ENB Setup to First SPI_CLK Rising Edge tSC 1 ns Last SPI_CLK Falling Edge to SPI_ENB Hold tHC 0 ns SPI_DI Data Input Setup to SPI_CLK tS 2 ns Data Input Hold to SPI_CLK tH 1 ns SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode tCO 3 8 ns 3-Wire Mode tCO 3 8 ns Bus Turnaround Time, Read tHZM tH tCO (max) ns After BBP drives the last address bit tHZS 0 tCO (max) ns After AD9365 drives the last data bit DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK and FB_CLK Pulse Width tMP 45% of tCP 55% of tCP ns TX Data TX_FRAME, P0_D, and P1_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output Delay tDDRX 0 1.5 ns DATA_CLK to RX_FRAME Delay tDDDV 0 1.0 ns ENABLE Pulse Width tENPW tCP ns TXNRX Pulse Width tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time TDD mode Before RX tRPRE 2 × tCP ns After RX tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK and FB_CLK Pulse Width tMP 45% of tCP 55% of tCP ns TX Data TX_FRAME, P0_D, and P1_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output Delay tDDRX 0 1.2 ns DATA_CLK to RX_FRAME Delay tDDDV 0 1.0 ns ENABLE Pulse Width tENPW tCP ns TXNRX Pulse Width tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode AD9365 ADI Confidential Rev. Sp0 | Page 6 of 24 Parameter Symbol Min Typ Max Unit Test Conditions/ Comments Bus Turnaround Time TDD mode Before RX tRPRE 2 × tCP ns After RX tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF SUPPLY CHARACTERISTICS 1.3 V Main Supply 1.267 1.3 1.33 V VDD_INTERFACE Supply 1.2 2.5 V VDD_GPO Supply 1.3 3.3 V When unused, must be set to 1.3 V ADI Confidential AD9365 Rev. Sp0 | Page 7 of 24 CURRENT CONSUMPTION SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions/Comment VDD_GPO 50 μA No load VDD_INTERFACE VDD_INTERFACE = 1.2 V Sleep Mode 45 μA Power applied, device disabled 10 MHz BW, Single Port, DDR 2.9 mA 30.72 MHz data clock 10 MHz BW, Dual Port, DDR 2.7 mA 15.36 MHz data clock VDD_INTERFACE = 1.8 V Sleep Mode 84 μA Power applied, device disabled 10 MHz BW, Single Port, DDR 4.5 mA 30.72 MHz data clock 10 MHz BW, Dual Port, DDR 4.1 mA 15.36 MHz data clock VDD_INTERFACE = 2.5 V Sleep Mode 150 μA Power applied, device disabled 10 MHz BW, Single Port, DDR 6.5 mA 30.72 MHz data clock 10 MHz BW, Dual Port, DDR 6.0 mA 15.36 MHz data clock VDDD1P3_DIG AND VDDAx (ALL OTHER SUPPLIES) Combination of all 1.3 V supply current Sleep Mode 180 μA Power applied, device disabled TDD Mode, 800 MHz, RX 5 MHz BW 180 mA Continuous RX 10 MHz BW 210 mA Continuous RX TDD Mode, 800 MHz, TX 5 MHz BW 7 dBm 340 mA Continuous TX −27 dBm 190 mA Continuous TX 10 MHz BW 7 dBm 360 mA Continuous TX −27 dBm 220 mA Continuous TX TDD Mode, 2300 MHz, RX 5 MHz BW 175 mA Continuous RX 10 MHz BW 200 mA Continuous RX TDD Mode, 2300 MHz, TX 5 MHz BW 7 dBm 350 mA Continuous TX −27 dBm 160 mA Continuous TX 10 MHz BW 7 dBm 380 mA Continuous TX −27 dBm 220 mA Continuous TX FDD Mode, 800 MHz 5 MHz BW 7 dBm 490 mA −27 dBm 345 mA 10 MHz BW 7 dBm 540 mA −27 dBm 395 mA FDD Mode, 2300 MHz 5 MHz BW 7 dBm 500 mA −27 dBm 350 mA 10 MHz BW 7 dBm 540 mA −27 dBm 390 mA AD9365 ADI Confidential Rev. Sp0 | Page 8 of 24 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VDDx to VSSx −0.3 V to +1.4 V VDD_INTERFACE to VSSx −0.3 V to +3.0 V VDD_GPO to VSSx −0.3 V to +3.9 V Logic Inputs and Outputs to VSSx −0.3 V to VDD_INTERFACE Input Current to Any Pin Except Supplies ±10 mA RF Inputs (Peak Power) 2.5 dBm TX Monitor Input Power (Peak Power) 9 dBm Package Power Dissipation (TJMAX − TA)/θJA Maximum Junction Temperature (TJMAX) 110°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REFLOW PROFILE The AD9365 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260°C. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type Airflow Velocity (m/sec) θJA 1, 2 θJC 1, 3 θJB 1, 4 ΨJT 1, 2 Unit 144-Ball CSP_BGA 0 32.3 9.6 20.2 0.27 °C/W 1.0 29.6 0.43 °C/W 2.5 27.8 0.57 °C/W 1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). ESD CAUTION ADI Confidential AD9365 Rev. Sp0 | Page 9 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 49 2- 00 2ANALOG I/O DIGITAL I/O NO CONNECT DC POWER GROUND M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 NC VSSA TX_MON VSSA VDDA1P1_TX_VCO VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_TX_LO VDDA1P3_ TX_VCO_ LDO TX_VCO_ LDO_OUT VSSA VSSA AUXDAC2 TEST/ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VDDA1P3_ RX_RF VDDA1P3_ RX_TX CTRL_IN2 P0_D9 P0_D7 P0_D5 P0_D3 P0_D1 VSSD VDDA1P3_ RX_LO VDDA1P3_ TX_LO_ BUFFER P0_D11 P0_D8 P0_D6 P0_D4 P0_D2 P0_D0 RX1A_P RX1A_N NC VSSA VSSA TX1A_P TX1A_N TX1B_P TX1B_N NC XTALN NC NC NC NC RX1B_P RX1B_N RX1C_P RX1C_N VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSASPI_DO SPI_ENB SPI_CLKSPI_DI AUXADCRBIAS RESETB VSSD VSSD VSSD VSSDVSSD CLK_OUT VSSA ENABLE CTRL_OUT0CTRL_OUT1CTRL_OUT2 NC TXNRX SYNC_IN EN_AGC VDDA1P3_ RX_SYNTH VDDA1P3_ TX_SYNTH VDDA1P3_ BB VDDA1P1_ RX_VCO RX_VCO_ LDO_OUT VDDA1P3_ RX_VCO_ LDO VDDD1P3_ DIG VDD_ INTERFACE P1_D10 P1_D9 P1_D7 P1_D5 P1_D3 P1_D1 P1_D8 P1_D6 P1_D4 P1_D2 P1_D0 DATA_ CLK VSSD FB_CLK TX_ FRAME RX_ FRAME P0_D10 VSSD P1_D11 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P3_ RX_TX Figure 2. Pin Configuration, Top View Table 5. Pin Function Descriptions Pin No. Type1 Mnemonic Description A5 I TX_MON Transmit Channel Power Monitor Input. If this pin is unused, tie it to ground. A7, A8, A9, A10, D3 I VDDA1P3_RX_TX 1.3 V Supply Input. A11 I VDDA1P1_TX_VCO Transmit VCO Supply Input. Connect to B11. B3 O AUXDAC1 Auxiliary DAC 1 Output. B4, B5, B6, B7 O GPO_3 to GPO_0 3.3 V Capable General-Purpose Outputs. B8 I VDD_GPO 2.5 V to 3.3 V Supply Input for the AUXDAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V. B9 I VDDA1P3_TX_LO Transmit LO 1.3 V Supply Input. B10 I VDDA1P3_TX_VCO_LDO Transmit VCO LDO 1.3 V Supply Input. Connect to B9. B11 O TX_VCO_LDO_OUT Transmit VCO LDO Output. Connect to A11 and to a 1 μF bypass capacitor in series with a 1 Ω resistor to ground. C3 O AUXDAC2 Auxiliary DAC 2 Output. C4 I TEST/ENABLE Test Input. Ground this pin for normal operation. C5, C6, D6 I CTRL_IN0 to CTRL_IN2 Control Inputs. Used for manual RX gain and TX attenuation control. D2 I VDDA1P3_RX_RF Receiver 1.3 V Supply Input. Connect to D3. D7 I/O P0_D9 Digital Data Port P0_D9. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. D8 I/O P0_D7 Digital Data Port P0_D7. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. D9 I/O P0_D5 Digital Data Port P0_D5. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. D10 I/O P0_D3 Digital Data Port P0_D3. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. D11 I/O P0_D1 Digital Data Port P0_D1. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. E2 I VDDA1P3_RX_LO Receive LO 1.3 V Supply Input. E3 I VDDA1P3_TX_LO_BUFFER 1.3 V Supply Input. E7 I/O P0_D11 Digital Data Port P0_D11. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. E8 I/O P0_D8 Digital Data Port P0_D8. Part of the 12-bit bidirectional parallel CMOS level Data Port 0. AD9365 ADI Con