controlled_isi_for_beyond_20Gbps_beyene_tadvpack_2008

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 4, NOVEMBER 2008 731 Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps Wendemagegnehu T. Beyene, Senior Member, IEEE, and Amir Amirkhany, Member, IEEE Abstract—This paper presents a new design technique of high- speed interconnects with controlled intersymbol interference (ISI) to create efficient signaling over a band-limited channel. Perfor- mance of high-speed electrical links is limited by conductor loss, di- electric dispersion, and reflections in the board, package, and con- nector. These nonidealities result in significant ISI. In current sys- tems, the effect of ISI is either mitigated through complex equaliza- tion, signal conditioning, and coding techniques, or through costly impedance control and manufacturing processes. In the proposed approach, instead of eliminating ISI, we shape the response of the channel into a set of channel characteristics with controlled ISI using simple passive structures in the board and the package. The resulting controlled ISI is exploited at the transmitter and receiver to simplify the architecture of the system and to achieve high data rates. The techniques to design interconnects with controlled ISI are reasonably simple to implement in conventional interconnect technologies. Simulation examples are given to demonstrate the va- lidity and advantages of the design technique using duobinary and analog multitone (AMT) signaling methods. Index Terms—Analog multitone (AMT) signaling, doubinary signaling, intersymbol interference (ISI), partial response sig- naling. I. INTRODUCTION H IGH-SPEEDdata transmissionover passive interconnectsis required to support the high-bandwidth demand of cur- rent computing and communication systems. The bandwidth of current chip-to-chip and backplane links is limited by the band- widthofthepassivecomponents(package,board,connector),and not by the operating speeds of the active circuitry in the trans- mitter and receiver. The interconnect systems are band-limited due to the loss and dispersive mechanism inherent to the inter- connects and its surroundings. These nonidealities are more pro- nounced in low-cost packaging, printed circuit board (PCB), and connector technologies.Theinsertionlossofvarious lengthchan- nels in conventional interconnect systems are shown in Fig. 1(a). Thereceivedsignalenergyinlongchannelssuchasthoseinlegacy backplanes is very small when the operating frequency exceeds 5 GHz. For medium and short channels, the detectable signal en- ergy is limited to the frequency ranges of up to 10 GHz. In addition to the attenuation, the discontinuities due to vias, connectors, solder balls, and stubs severely limit the bandwidth Manuscript received September 11, 2007; revised February 19, 2008. First published May 16, 2008; current version published November 28, 2008. This work was recommended for publication by Associate Editor P. Franzon upon evaluation of the reviewers comments. The authors are with Rambus Inc., Los Altos, CA 94022 USA (e-mail: wbeyene@rambus.com; amir@rambus.com) Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2008.924224 of a channel. Some of these band-limiting structures are not part of the signal path and they exist merely because of manufac- turing artifacts or mechanical requirements. For example, the via stubs in a conventional backplane and the plating stubs in a wirebond plastic ball grid array (PBGA) package do not serve any electrical purpose [1]. These via and plating stubs signifi- cantly reduce the operating bandwidth of the channel by intro- ducing resonances, as shown in Fig. 1(b). As a result, the traces with long stubs show significant reduction in their bandwidth. The increase in data rate over an interconnect is currently made possible by designing controlled impedance interconnect systems. In addition, the discontinuities created by connectors, solder balls, and stubs have been mitigated so far by careful compensation techniques [2]. However, as the data rate in- creases, the compensation effect diminishes because of the narrow band nature of the techniques and the increase in the overall channel attenuation. Improved packaging, connector, via technologies, and better materials can further improve transmission characteristics of the channel. However, the cost of the channel will increase significantly. Another approach to mitigate the effect of ISI is the use of equalization techniques [3], [4]. Unfortunately, for low-cost in- terconnect technologies with long stubs, the frequency charac- teristics have nulls that can be problematic for simple equal- ization techniques. This requires complex on-chip digital signal processing circuitry. An alternative approach is to use multilevel signaling and pack the data into a small bandwidth [5]. Mul- tilevel signaling, however, sacrifices the signal-to-noise ratio (SNR) and adds to the complexity of the timing recovery cir- cuits and to the power consumption of the system. An alternative to these techniques, which all try to eliminate ISI, is to control ISI and shape it to specific known patterns that can be exploited at the receiver for efficient signal detection [6]. In this alternative approach, the design goal of an interconnect system is to shape the response of the channel using trace and via stubs (contrary to impedance matching), so that the system has the desired characteristics to transmit higher data rates or has simpler transmitter or receiver. Signal transmission technique over controlled ISI channels are well studied in the literature and a number of algorithms exist to choose from [7]–[9]. In Sections II, the state of the art link systems with transmit and receive equalizers are briefly described. Then, two classes of signaling techniques over controlled ISI channel, partial sig- naling, and analog multitone (AMT) signaling are introduced in Section III. Controlled ISI channel engineering is presented in Section IV. In Section V, a design example of a high data rate signaling and system is presented. Implementation details and 1521-3323/$25.00 © 2008 IEEE Authorized licensed use limited to: Texas A M University. Downloaded on June 23, 2009 at 13:07 from IEEE Xplore. Restrictions apply. 732 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 4, NOVEMBER 2008 Fig. 1. Insertion loss of lossy and discontinues conventional low-cost intercon- nects. (a) Insertion loss of typical signal nets with varying length. (b) Insertion loss of wirebond PBGA package nets with 2.6 to 4.5-mm-long plating stubs. comparisons of various signaling techniques including duobi- nary and AMT are discussed. Finally, the conclusion is given in Section VII. II. STATE OF THE ART LINK DESIGN In high-speed link design, equalization and signal processing techniques are used to mitigate the effects of ISI. Equalization can compensate channel frequency-dependent loss and disper- sion of long traces in boards and packages, and dispersion due to device loadings [3]. Fig. 2 shows a block diagram of a state of the art link. Both linear and decision feedback equalizers often exist in current systems. The linear equalizer is a feed-forward equalizer (FFE) that uses linear filters with adjustable param- eters to compensate for channel distortion. This can be imple- mented as transmitter preemphasis and/or receiver equalization as shown in Fig. 3. Although, receiver equalization has many advantages, the simplest and most cost-effective approach for a multigigabits per second parallel bus is transmit preemphasis. Transmit preemphasis compensates for the low-pass nature of the channel by preemphasizing the high-frequency components of the input signal, as shown in the transfer functions of the transmit equalizer of Fig. 3. However, the transmitter uses part of the signal amplitude budget to generate the preshaping sym- bols following the main symbol which leads to reduced SNR. The performance of systems with transmit and receive linear equalization can easily be determined using linear analysis in time or frequency domains. The preemphasis filter can be im- plemented using analog techniques by integrating the filter into each driver module as a parallel transmitter. The decision feedback equalizer (DFE) is a nonlinear equal- izer that employs previous decisions to eliminate ISI caused by previous detected symbols on the current symbol to be detected. The single-bit response (SBR) of a high-speed interconnect with DFE is shown in Fig. 4. The DFE is not able to cancel the pre- cursor ISI as it is causal. Consequently, the DFE often needs to be paired with a FFE. DFE is the most effective way to cancel postcursor ISI because as opposed to a transmit FFE it does not reduce the transmit peak voltage budget and unlike a receive FFE it does not amplify channel noise. However, a major cir- cuit design challenge in the design of the first (few) postcursor DFE taps is closing the timing for feedback loop in one (or few) unit intervals, as shown in Fig. 5(a). This problem is particularly more pronounced for the first DFE tap, as the received signal has to be detected, multiplied by the appropriate weight coeffi- cient, and subtracted from the incoming signal, all in only one unit interval. A unit interval can be as small as 50 ps in 20-Gbps 2-PAM link. As a result the first DFE tap is often not removed in high-speed links, or look-ahead computation is used to unroll the loop and increase the delay in the feedback loop [10]–[12]. In one-tap loop-unrolled DFE, two decisions are made at each cycle. One comparator decides the received signal as if the previous received signal was a one, and the other comparator decides the received signal as if the previous bit was a zero. Once we know the previous bit, the correct comparator output is chosen. A one-tap loop-unroll DFE is shown in 5(b). The loop-unroll DFE makes two decisions on two conditioned eyes using samplers that are offset by the first postcursor ISI tap magnitude [10]. The lower and upper eye diagrams, are shown in Fig. 6(a) and (b), respectively. The two eyes are split by the amount proportional to the first post-cursor ISI tap. The timing constraint in a loop-unrolled DFE is to accommodate a flip-flop and a multiplexer in one unit interval, which could still be a challenge at 20-Gbps. The number of samplers re- quired for loop-unrolling for more than one tap increases as . As a result, loop-unrolling for more than one tap is generally avoided. III. CONTROLLED-ISI LINK DESIGN The equalization techniques described in the previous sec- tion are targeting arbitrary forms of ISI. However, for the cases where the communication channel has a well-defined pattern, more efficient signal processing techniques are developed that lead to simpler transmitter and receiver architectures. In this section, we describe two of these techniques that are particu- larly relevant to the link design approach we present later in this paper. A. Partial Response Signaling Let us assume the ISI pattern in the communication channel is so severe such that the previous bit gets added to the current bit as the signal travels through the channel. In other words, the received signal at time is given by (1) Authorized licensed use limited to: Texas A M University. Downloaded on June 23, 2009 at 13:07 from IEEE Xplore. Restrictions apply. BEYENE AND AMIRKHANY: CONTROLLED INTERSYMBOL INTERFERENCE DESIGN TECHNIQUES 733 Fig. 2. Block diagram of a state of the art link. Fig. 3. Transfer functions of the channel along the transmit and receiver linear equalizers. Fig. 4. Single bit response with 3-tap DFE applied at second, third, and fourth postcursors. Fig. 5. Delay in the feedback loop of DFE. (a) Standard DFE. (b) Loop-unroll DFE. where is the transmitted symbol at time . Then for a 2-PAM system, the received signal can either be 0 or 2 if and Fig. 6. Received conditioned eyes as seen by the upper and lower samplers. (a) Upper eye. (b) Lower eye. are equal, or it is 1 otherwise. Therefore, if we know what is, we can find out what is using regular DFE or loop-unrolled DFE. Alternatively, we may perform the following simple pre- coding at the transmitter before transmitting the signal: (2) Authorized licensed use limited to: Texas A M University. Downloaded on June 23, 2009 at 13:07 from IEEE Xplore. Restrictions apply. 734 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 4, NOVEMBER 2008 TABLE I CHARACTERISTICS OF SOME OF THE PARTIAL-RESPONSE SYSTEMS where represents the XOR operation, and transmit instead of . By doing so, it is easy to verify that levels 2 and 0 at the receiver correspond to , and level 1 corresponds to independent of the value of . Therefore, the en- coding on the transmitter eliminated the need for DFE at the receiver without increasing the transmitter voltage headroom requirements since the transmitted sequence still consists of 1 and 0. This signaling technique is called duobinary signaling and was first proposed by Lender [7]. If channel characteris- tics are not exactly as described above, a linear FFE may pre- cede the channel at the transmitter to equalize the channel to the duobinary ISI pattern. Consequently, in practical systems, duobinary signaling is generally used when channel character- istics are close to a duobinary channel. Duobinary signaling has already been demonstrated at 10 Gbps and beyond over a long FR4 backplane [9]. Other classes of partial-response sig- naling also exist which are specific to other types of channels. The characteristics of the few common partial response systems, duobinary, dicode, modified duobinary, and class 2, are shown in Table I. The frequency responses and impulse responses of duobi- nary, dicode, modified duobinary, and class 2, are also shown in Fig. 7(a) and (b), respectively. The duobinary channel is a low-pass filter with a null frequency at , and the di- code is a high-pass filter with a null frequency at . The modified duobinary is a bandpass filter with null frequencies at both , and . The class 2 system is also a low-pass system with null at a , but with different roll-off shape than that of a duobinary channel. The eye diagrams of the duobinary and the class 2 systems are shown in Fig. 8(a) and (b), respectively. The duobinary and the class 2 systems have three and five levels, respectively. B. Multitone Signaling Partial response methods explained in the previous section mainly exploit the part of channel bandwidth before the first notch in the frequency response of the channel. However, for example, in the case of a duobinary channel with a frequency response of , channel frequency response bounces back to nonzero values after the first notch frequency. In fact, notches in the frequency response happen at equally spaced dis- tances at and additional channel bandwidth ex- ists for signal transmission between every two notches, which is not utilized by duobinary transmission. In these cases, it is pos- sible to transmit a multitone sequence consisting of a duobinary stream centered at dc and a set of passband duobinary streams centered around nonzero carrier frequencies. A new multitone architecture suitable for high-speed links, called analog multitone (AMT), was recently proposed in Fig. 7. Frequency-domain characteristics and impulse responses of a few common partial response systems: duobinary (class 1), dicode, modified-duobi- nary, and class 2. (a) Frequency-domain response. (b) Time-domain response. [13]–[15]. A simplified three-channel AMT system is shown in Fig. 9(a). The input bit stream is parallelized to three streams with each substream running at one-third of the total bit-rate. Each substream is consequently modulated to its respective carrier frequency and the combined signal is sent over the line. Fig. 9(b) symbolically shows the frequency responses of the individual subchannels at the receiver input. In an AMT system, all carrier frequencies are integer multiples of the substream symbol rate. When no ISI exists, the substreams are separated from each other at the receiver using mixers and integrators. In practical systems with ISI, feed-forward equalizers are placed at the transmitter per substream to maintain the orthogonality between the substreams at the receiver input. The mixers at the transmitter are also combined with the transmit equalizers and performed in the digital domain. Similar to a conventional nonreturn-to-zero (NRZ) system, every substream in an AMT system can have a DFE at the receiver, and DFEs can even exist between the substreams to cancel postcursor interchannel interference (ICI). However, the DFE in AMT runs at the substream rate, which is a fraction of the total system bit rate. Therefore, timing constraints are relieved. Over a duobinary channel , if the substream rate is set equal to , the channel delays the combined signal at the transmitter output (and consequently the individual constituent substreams) by a full substream cycle and adds it to itself. However, since all carrier frequencies are integer multiples of , this operation does not affect the orthogonality between the substreams. As a result, after mixing and integration at the receiver, each Authorized licensed use limited to: Texas A M University. Downloaded on June 23, 2009 at 13:07 from IEEE Xplore. Restrictions apply. BEYENE AND AMIRKHANY: CONTROLLED INTERSYMBOL INTERFERENCE DESIGN TECHNIQUES 735 Fig. 8. Eye diagrams of partial response signals at 20 Gbps data rate for (a) duobinary (class 1: three levels) and (b) class 2 (five levels). (a) Doubinary. (b) Class 2. Fig. 9. Three-channel AMT system and the subchannel frequency responses. (a) Three-channel AMT system. (b) Subchannel frequency responses. substream is separated as a duobinary sequence. Consequently, duobinary encoding can be performed per substream at the transmitter to simplify detection per substream. Even though we based the argument in this section on a duobi- nary channel, all the arguments can be extended to all the vari- ations of partial response signaling methods introduced in the previous section. IV. CONTROLLED ISI CHANNEL ENGINEERING High-speed link channels are generally such that eliminating ISI with the aid of equalization techniques leads to fairly com- plex systems and substantial power-consumption. On the other hand, link channels are generally low-pass with sharp rolloffs. Therefore, they are close, but not exactly the same as the low- pass partial response channels in Section III. Even if the channel has a notch similar to duobinary system, the notch frequencies may not correspond to the target signaling rate. Therefore, to create an equivalent partial response channel certain amount of equalization is necessary at the transmitter which leads to in- creased power consumption and reduces SNR. In this paper, we propose an alternative method to create partial response chan- nels out of regular link channels by adding passive waveguide structures to the PCB trace and on the package. Fig. 10(a) shows a simple interconnect system with a single stub to tune its transfer characteristic. The response of the system can be shaped by changing the stub length and impedance. The length of the stub determines the frequency nulls, whereas the impedance of the stub affects the roll-off, as shown in Fig. 10(b) and (c), respectively. The length of the stub and the first null frequency are related by (3) where is the speed of light, is the relative permittivity or dielectric constant of the material, and is the length of the stub. For a low-loss material, the channel magnitude responses are relatively insensitive to the position of the stub. By having multiple stubs, a desired spectral shape can be closely approximated