小研高速电路板图中金属连线的寄生效应仿真方法及其分析

小研高速电路板图中金属连线的寄生效应仿真方法及其 分析 定性数据统计分析pdf销售业绩分析模板建筑结构震害分析销售进度分析表京东商城竞争战略分析 This article is contributed by zju_sning PDF documents may have a poor browsing experience at the WAP end. It is recommended that you choose TXT, or download the source file to the native view. The parasitic effect simulation method and its analysis of the metal wire in the small research high-speed circuit board diagram 1 the introduction Along with the development of integrated circuit technology, the feature size of MOSFET is getting narrow. And the integration to improve at the same time make the chip power consumption increasing, and a variety of negligible in large size circuit originally parasitism, in deep sub-micron circuits is particularly important, sometimes even decisive role, affect the performance of the whole chip. This thesis discusses the problem is to use more concise layout after simulation method to study the series of problems caused by the metal wires, and its solutions. At the current developing trend of integrated circuit chips, low voltage, more performance and low cost will become increasingly important, and then all kinds of additional effects is increasingly apparent. Up the chip speed is not broken, however, in the large size chip was negligible in the circuit of metal wire, will show in every aspect of its decisive influence on circuit. In the article [1], the discussion of the 0.18 um multilayer metal parasitism was considered, and the article [2] also discussed the delay of the metal attachment of 0.18 um technology. And this article focuses on large size, high precision process, more high speed circuit, with the length of the metal attachment generally in more than 10000 um, clock cycles under 0.8 ns. However, high-frequency circuits such as radio frequency circuits are not covered, and the article [3] gives the corresponding RLC connection model. A simulation experiment on the parasitic effects of metal wires To understand the metal wiring system in the actual electrical energy in a figure, we establish a model of all kinds of metal wire, and a simulation tool for plate figure with parasitic parameters of the simulation. To understand the impact of changes in parameters, we modeled a parameter with a change of metal wire and fixed other parameters. 2.1 wire parasitic parasitic parameters of coupling factors wire refers to the capacitor and resistor wire itself, and the wall between the two wire capacitance and the capacitance. Our discussion will also revolve around these coupling factors. 2.2 all models into the research all kinds of basic structure of the metal line parasitic coupling effect, we adopt the basic model is through a driver to drive an active load, and we care about metal wire is connected between the drive and load. Mux drives the static signal that drives the measured, because the direct pin definition is an infinite driver, which is not true. The clock is driven by the inverter, and the load is inverter. At the same time, we need to arrange the disturbance source in the vicinity of the observed metal attachment to seek the degree of anti-interference of the interference source. The diagram below is A basic model of the circuit model, A group of models for the group A, mentioned in the latter. 2.3 for all test has two modes: group A model of signal edge load clock source group B model: the edge of the clock line load clock source for group A model we focus on fixed amplitude was formed under the interference sources interference coupling voltage signal. For group B we look at the delay of the clock signal when it is disturbed. A group model: load clock interferon at the edge of the non-moving signal line to change the length of the wire and the change in L. We can get the following: clear from the figure are the length of the wire and its interference sources bring interference amplitude is proportional to, namely, the longer the wire length, the greater the interference. Also change the width of the wire, the change in W. We can get it. Clear from the figure are the width of the metal wire and its interference sources bring up into a small disturbance amplitude is proportional, interference sources of the interference effect is not as L change obviously. Change the spacing between the wires, the S. We can get the following. Can see clearly from the picture the spacing is instead of interference sources of metal wire is inversely proportional to the amplitude of the interference, interference sources the farther away from the test line, the less the interference effect. Change the driver MOS size, the W/L change in MOS tube. We can get the following. It is obvious from the graph that the driving size of the wire is inversely proportional to the disturbance caused by the disturbance source, and the larger the displacement, the smaller the disturbance effect. For the model of L change, we will do another set of experiments, which will be grounded on the side of the signal line. Available here. It is clear that there is no added shielding line against dry winding. Group B model: the clock line is loaded by the clock line to change the length of the wire, or the change in L. We can get the following. It is evident from the graph that the length of the wire is proportional to the amount of the disturbance, the longer the line length and the greater the disturbance. Change the width of the wire, the change in W. We can get the following. Clear from the figure are the width of the metal wire and its interference sources bring up into a small disturbance amplitude is proportional, interference sources alignment effect is not as L change obviously. Change the spacing between the wires, the S. We can get the following. Can see clearly from the picture the spacing is instead of interference sources of metal wire is inversely proportional to the amplitude of the interference, interference sources the farther away from the test line, the less the interference effect. Change the driver MOS size, the W/L change in MOS tube. We can get the following. Can see clearly from the picture the drive size rather than by interference sources of metal wire is inversely proportional to the amplitude of the interference, the dynamic displacement, the greater the interference effect. The mathematical model of the 2.4 metal wire is based on the actual circuit analysis of the simulation model, and the results are straightforward and easy to understand. And here we're going to do a comprehensive mathematical analysis of these models. From the basic theory, look at how the parasitic effects of metallic attachment affect our circuitry. First, we set some basic parameters. Square resistance of A wire for R, wire line length L, line width of W, the thickness of the metal wire for X, wire from the vertical height of the substrate for H, measured wire with adjacent wire B and C spacing for the S, the size of the drive MOS inverter for n (inverter wide long than W/L). The interference signal on adjacent metal wires is 0.8 ns of square wave of 0-3v. With these parameters in place, we calculate the waveform of the load input in model 1. First we calculate the wire A long L1 space have been the resistance value: r = r * L1 / L, and the metal interconnect capacitance formula can be caused by the following calculating approximate formula is given in paper [4] : from which we can see that the metal interconnect capacitance is mainly divided into capacitance and earth capacitance between metal wire, wire C said wall coupling capacitance between two metal wires, three rational function can be expressed as the sum of the three rational function can be respectively by simulating three flux composition again after A least squares fitting. Article [4] specific calculation formula is given in the right side first characterization of wire side wall flux, with the thickness of the wire into a linear relationship between X and with reduced with the decrease of the H/S (that is, with the increasing of the flux plus), because from the side walls more flux is absorbed. The second gives the chart of the wire in the face of the contribution of flux, it increased with the increase of wire width W, or as the conductor increases with the decrease of the spacing between S, and is independent of the flux. The third term is the flux of the surface under the wire, which is inversely proportional to the flux. In a similar way, GND C can be represented as the sum of three rational functions by simulating the three flux components, and by the least square method. (2) the first item on the right side is the flux of the metal plate to the ground, which is simply the capacitance between the metal plate and the metal plate. The second and third items represent the contribution of the surface of the wire and the wall of the wire to the flux. In these two terms, flux decreases with s, and the reason is that more coupling flux is absorbed by adjacent electrodes a M and c M. We further analysis on one node by the formula of capacitance value, in the case of general technology limited the parameters in the thickness of the metal wire and metal substrate X height H is unable to change, to the back of the operation is convenient, we can assume that H 2, X = 1. And line width W and line spacing S change range can be very big, but when metal wire spacing is too large, craft may fill the auxiliary to king To ensure the quality of technology, the article is devoted to the problem in [5], and when after filling, metal spacing can be smaller. So we take the normal 90 nanometer high scale circuit craft, the value of W and S, the value of the common W and S values: 20 > = W > = 2; > = S > = 2, we simplify the formula: first, the rewrite is as follows: B stands for constant constant. Next type in all the bottom of the power function in parentheses is less than 1 value, considering the former in the face of parameter setting, we can for the one worth forecast: from the above chart can see clearly when the line spacing fixed line width is proportional to the capacitance of growth, and when the line width of fixed capacitor C as the line spacing becomes large and small, but smaller amplitude is not very clear, H = 2 at this moment because this formula, the metal cable capacitance to the ground in occupies a high proportion in the total capacity. But if in some more complex process, between the wire and the substrate Distance may be far greater than 2, then we change the value of H, H = 10 we can get the following. By the figure we can clearly see the value of C and S form of value into index decreased, thus increase the spacing between how important is it to reduce the line capacitance coupling. If two phase coupling, the clock signal if it is just the same as two clock can be entangled, produce superimposed effect, can quickly reach the peaks and troughs, does not have much impact on delay. But if the phase of the two clocks is misaligned, or even the opposite, the interference will act as a stop to the clock's peak. And represented in the formula (5) the capacitance of metal wire is generally recognized as the capacitance, namely earth capacitance and sidewall capacitance between metal lines, and when two adjacent wire has a voltage difference, there will be an additional C QV Δ = Δ, and Q is negative. So for low-voltage signal lines, the greater the voltage difference, the greater the additional capacity, the greater the delay. So in case 2. Two different phase clock signals are in parallel, and light slows the clock signal Time-varying large; Weight destroys the clock waveform, making the clock completely unavailable. Due to the interference of the media is still created by capacitance coupling voltage, so can also be concluded that the delay is proportional to the capacitance of the line length than the spacing and the driven dimensions. 2.5 metal wire parasitic effects caused by the circuit failure In the previous diagram, power supply voltage of 1.8 v, I can see several of the coupling voltage worst case value reached more than 400 mv, if these situations exist: drive small, signal lines long and do not shielded coupling, and walking on the edge of this signal a high frequency of the clock signal, if there is the power of the transient voltage fluctuation. The signal line is likely to be coupled at some point to a high amplitude coupled voltage, and when this noise is more than 900mv. This leads to faulty chip functions. For example the CLK is a fast clock signal, the DATA is requires DATA signals are transmitted, at the same time when they were sent to two different requirements set of latch, due to the CLK and DAT go a long way and in parallel, then the DATA can be CLK clock coupling and then into the risk of wrong DATA. There are many ways to solve the parasitic effects of metal attachment. The main ones are: 1 for long lines of signals that can be graded without affecting speed. Increase the driving power of the long line in the case of power consumption. Increase the line spacing between the line and the surrounding metal line under area permitting, or insert the earth's shielded wire. 4 avoid the clock signal and other signals in parallel, the same way, especially against the clock signal and walk the line, if necessary, must be in shielding grounding wire. 3 the article summary In this paper, by using the method of simulation after layout in the actual circuit of metal wire parasitic parameters analyzed, through the simple simulation, not only can be very intuitive to see the parasitic effect of metal wire, and can be directly from the simulation results it is concluded that the size of the parasitic effect on circuit performance. And the time delay and the size of the coupling voltage can make the similar process chip, both in the landscape design and circuit design as an important reference basis. This approach could also be used to make some of the "DRC" in the design of a chip, further ensuring the working ability of the chip. Master thesis 参考文献 [1] Jacques CLUZELJ, ean-Pierre SCHOELLKOPF，HervC JAOUEN*.Benoit and et al, “New interconnectcapacitance characterization method for multilevel metal CMOS processes”, 1999 IEEE [2] Shien-Yang Wu, Boon-Khim Liew, K.L. Young, C.H. Yu, and et al “Analysis of Interconnect Delay for0.18pm Technology and Beyond” 1999 IEEE [3] Andrew B. Kahng and Sudhakar Muddu “An Analytical Delay Model for RLC Interconnects” IEEETRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 16, NO. 12, DECEMBER 1997 [4] Shyh-Chyi Wong, Gwo-Yann Lee, and Dye-Jyun Ma “Modeling of Interconnect Capacitance, Delay, andCrosstalk in VLSI” IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO.1, FEBRUARY 2000 [5] Andrew B. Kahng ，Kambiz Samadi， Puneet Sharma “Study of Floating Fill Impact on InterconnectCapacitance” Proceedings of the 7th International Symposium on Quality Electronic Design 2006 IEEE one