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首页 16x16点阵-EDA课程设计.doc

16x16点阵-EDA课程设计.doc.doc

16x16点阵-EDA课程设计.doc

蓝色双鱼的秋天
2017-10-18 0人阅读 举报 0 0 暂无简介

简介:本文档为《16x16点阵-EDA课程设计.docdoc》,可适用于考试题库领域

x点阵EDA课程设计doc应用科学学院SOPCEDA综合课程设计报告设计题目:设计者:学号:班级:指导老师:完成时间:设计报告综合测试总评格式内容图表答辩平时()()()()()目录第章总体设计原理及原理框图设计原理顶层文件设计总体仿真图第章单元电路设计时序控制模块设计时序控制模块的源程序及其实体图时序控制模块仿真扫描控制模块设计扫描控制模块源程序及其实体图扫描控制模块仿真显示控制模块源程序及其实体图显示控制模块显示控制模块仿真第章心得体会参考文献第章总体设计原理及原理框图设计原理首先我们设计要正确显示这些字显示屏上的灯的亮暗情况具体应如何。如第一个字‘江’:第一种方案第二种方案如果高电平‘时表示灯是亮的低电平‘’时灯是暗的这样上面的灯呈现在我们眼前的就是‘江’字了。依次类推我们就可以设计出所有要显示的字了。使用FPGA设计一个×的点阵显示的控制器使点阵显示器以两种花样显示“江西理工大学应用科学学院欢迎您”第一种花样是用亮着的灯组合所要显示的字第二种方案是用暗着的灯组成所需要的字。这样这些字就好象是被我们当作了固定模型了。但如何点亮这些灯呢这就要求有一个脉冲循环扫描的电路我们采用列扫描当扫描的和我们先设计好的字模型的高电平相匹配时灯就相应的点亮。由于扫描的速度很快我们人的眼睛并不会感到灯的闪烁所以每扫描完列就会显示在我们眼中一个字了。但要所有的字母就可以依次的显示出来并不停的循环显示就还要再有一个时序控制电路来控制。此时序控制电路象一个计数器有自动清零的功能这样就可以实现循环的效果了。其设计原理图框图如下时序控制显示控制译码输出扫描控制图总体设计框图顶层文件设计顶层文件来实现循环显示各个字的功能。它由时序控制模块扫描模块和字母显示控制模块组成。时序控制模块利用脉冲来控制每个字的显示时间。扫描控制模块利用列扫描脉冲产生列扫描信号。而字显示控制模块用时序控制模块和扫描控制模块所提供的脉冲信号来点亮各个字模型中相应的灯。在时序模块的控制下(此设计中每个字为一个循环)实现了各个字循环显示的功能。要实现显示“江西理工大学应用科学学院欢迎您“结合实际模块LCDLCD,LCD分别实现时序控制模块扫描模块和字母显示控制模块。具体电路的顶层文件设计如下图图顶层电路图lcdlcdINPUTOUTPUTCLKQOclkqhsqoVCCgsinstinstlcdINPUTOUTPUTsoCLKclksoVCCinst总体仿真图图第一个字设计仿真图图中使CLK一直为低电平即第一个字这时从QO输出第一个字“江”的字库第章单元电路设计时序控制模块设计时序控制模块的源程序及其实体图此模块用来控制每个字的显示时间当计满四个脉冲时cnt自动清零即每个字显示四个脉冲的时间。一共有个字(江西理工大学应用科学学院欢迎您)。当tmp=时tmp自动清零此后是这些字显示的下一个循环。如此不停的循环显示各个字。图时序控制模块libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitylcdisport(clk:instdlogicq:outstdlogicvector(downto))endlcdarchitectureoneoflcdisbeginprocess(clk)variablecnt:integervariabletmp:stdlogicvector(downto)beginifclk'eventandclk=''thenifcnt<thencnt:=cntelsecnt:=iftmp=""thentmp:=""elsetmp:=tmpendifendifendifq<=tmpendprocessend时序控制模块仿真图时序控制模块仿真图由图可知:Q输出达到了计数的功能最大计数为即总共为个数。扫描控制模块设计扫描控制模块源程序及其实体图此模块用来实现列扫描控制每扫描完列tmp自动清零这样就提供了一个行循环扫描的功能这样就可以循环的是各个字。图扫描控制模块其程序实现:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitylcdisport(clk:instdlogicso:outstdlogicvector(downto))endlcdarchitectureoneoflcdisbeginprocess(clk)variabletmp:stdlogicvector(downto)beginifclk'eventandclk=''theniftmp=""thentmp:=""elsetmp:=tmpendifendifso<=tmpendprocessend扫描控制模块仿真图扫描控制模块仿真图由图知:SO计数最大为总共个从而控制扫描。显示控制模块源程序及其实体图显示控制模块此模块用来实现显示出相应的字。hs控制字的个数gs控制扫描的行数。使对应列选择信号输出每一列对应的数据点量相应的灯。lcdhsqogs图显示控制模块inst其程序实现:libraryieeeuseieeestdlogicallentitylcdisport(hs:instdlogicvector(downto)gs:instdlogicvector(downto)qo:outstdlogicvector(downto))endlcdarchitectureoneoflcdisbeginprocess(hs,gs)begincasehsiswhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""whenothers=>endcasewhen""=>casegsiswhen""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=>qo<=""when""=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en""=>qo<=""whenothers=>endcasewhenothers=>endcaseendprocessend显示控制模块仿真图显示控制模块仿真图由图知:在GS输入HS输入即第个字时QO输出这一列的相应的数字。第章心得体会每次都有不一样的收获每次都能重新认识自己。这次的课程设计就给了我这么的体会。为期三周的EDA课程设计已经落下帷幕。整过设计过程完成很顺利。从第一天我拿到了老师给我们的课题就开始着手进行设计中间虽然也有不少挫折但不经历挫折怎么见风雨在我四处查看资料请教同学下终于完成。以前学习EDA这门课程时就觉得很难现在到真正的做设计的时候更不知道如何着手只有得从头再慢慢边学边做了。我找了些关于EDA入门和电子设计的书来看。一看就是几天但还是没能构建出整体思路。于是便找来了几个一起做相同课题的同学一起商量顿时豁然开朗。头脑中隐隐看到了思路心里有了底。经过多次的试验终于把程序编写好。通过此次课程设计我从中获益不少不仅弥补了平时理论知识的一些不足还使我们领悟到许多做人处事的道理。比如我们在实验过程中有一些不同的意见而且有些意见完全不在一条线上但经过我们的讨论最后还是得以共识。此外我对自己的专业有了更为详尽而深刻的了解也是对这几年大学里所学知识的巩固与运用。从这次实习中我体会到了实际的工作与书本上的知识是有一定距离的认识到自己的不足。参考文献SOPC综合课程设计指导书潘松黄继业编著EDA技术与VHDL(第版)清华大学出版社杭州康芯电子有限公司GWPK实验系统说明书杭州康芯电子有限公司

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