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PN532_C1_SDS PN532/C1 Near Field Communication (NFC) controller 1. General description The PN532 is a highly integrated transceiver module for contactless communication at 13.56 MHz based on the 80C51 microcontroller core. It supports 6 different operating modes: • ...

PN532_C1_SDS
PN532/C1 Near Field Communication (NFC) controller 1. General description The PN532 is a highly integrated transceiver module for contactless communication at 13.56 MHz based on the 80C51 microcontroller core. It supports 6 different operating modes: • ISO/IEC 14443A/MIFARE Reader/Writer • FeliCa Reader/Writer • ISO/IEC 14443B Reader/Writer • ISO/IEC 14443A/MIFARE Card MIFARE Classic 1K or MIFARE Classic 4K card emulation mode • FeliCa Card emulation • ISO/IEC 18092, ECMA 340 Peer-to-Peer The PN532 implements a demodulator and decoder for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The PN532 handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC). The PN532 supports MIFARE Classic 1K or MIFARE Classic 4K card emulation mode. The PN532 supports contactless communication using MIFARE Higher transfer speeds up to 424 kbit/s in both directions. The PN532 can demodulate and decode FeliCa coded signals. The PN532 handles the FeliCa framing and error detection. The PN532 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The PN532 supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer communication scheme, except anticollision. This must be implemented in firmware as well as upper layers. In card emulation mode, the PN532 is able to answer to a Reader/Writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN532 generates the load modulation signals, either from its transmitter or from the LOADMOD pin driving an external active circuit. A complete secure card functionality is only possible in combination with a secure IC using the NFC-WI/S2C interface. Compliant to ECMA 340 and ISO/IEC 18092 NFCIP-1 Passive and Active communication modes, the PN532 offers the possibility to communicate to another NFCIP-1 compliant device, at transfer speeds up to 424 kbit/s.The PN532 handles the complete NFCIP-1 framing and error detection. The PN532 transceiver can be connected to an external antenna for Reader/Writer or Card/PICC modes, without any additional active component. Rev. 3.2 — 20 September 2012 120132 Product short data sheet COMPANY PUBLIC NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller The PN532 supports the following host interfaces: • SPI • I2C • High Speed UART (HSU) An embedded low-dropout voltage regulator allows the device to be connected directly to a battery. In addition, a power switch is included to supply power to a secure IC. 2. Features and benefits  80C51 microcontroller core with 40 KB ROM and 1 KB RAM  Highly integrated demodulator and decoder  Buffered output drivers to connect an antenna with minimum number of external components  Integrated RF level detector  Integrated data mode detector  Supports ISO/IEC 14443A/MIFARE  Supports ISO/IEC 14443B (Reader/Writer mode only)  Typical operating distance in Reader/Writer mode for communication to ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending on antenna size and tuning  Typical operating distance in NFCIP-1 mode up to 50 mm depending on antenna size, tuning and power supply  Typical operating distance in ISO/IEC 14443A/MIFARE or FeliCa card emulation mode of approximately 100 mm depending on antenna size, tuning and external field strength  Supports MIFARE Classic 1K or MIFARE Classic 4K encryption in Reader/Writer mode and MIFARE higher transfer speed communication at 212 kbit/s and 424 kbit/s  Supports contactless communication according to the FeliCa protocol at 212 kbit/s and 424 kbit/s  Integrated RF interface for NFCIP-1 up to 424 kbit/s  Possibility to communicate on the RF interface above 424 kbit/s using external analog components  Supported host interfaces  SPI interface  I2C interface  High-speed UART  Dedicated host interrupts  Low power modes  Hard-Power-Down mode (1 A typical)  Soft-Power-Down mode (22 A typical)  Automatic wake-up on I2C, HSU and SPI interfaces when device is in Power-down mode  Programmable timers PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 2 of 27  Crystal oscillator  2.7 to 5.5 V power supply operating range NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller  Power switch for external secure companion chip  Dedicated IO ports for external device control  Integrated antenna detector for production tests  ECMA 373 NFC-WI interface to connect an external secure IC 3. Applications  Mobile and portable devices  Consumer applications 4. Quick reference data [1] DVDD, AVDD and TVDD must always be at the same supply voltage. [2] The total current consumption depends on the firmware version (different internal IC clock speed) [3] With an antenna tuned at 50  at 13.56 MHz [4] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account) Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VBAT Battery supply voltage 2.7 5.5 V ICVDD LDO output voltage VBAT > 3.4 V VSS = 0 V [1] 2.7 3 3.4 V PVDD Supply voltage for host interface VSS = 0 V 1.6 - 3.6 V SVDD Output voltage for secure IC interface VSS = 0 V (SVDD Switch Enabled) DVDD -0.5 - DVDD V IHPD Hard-Power-Down current consumption VBAT = 5 V - - 2 A ISPD Soft-Power-Down current consumption VBAT = 5 V, RF level detector on - - 45 A IDVDD Digital supply current VBAT = 5 V, SVDD switch off [1] - 25 - mA ISVDD SVDD load current VBAT = 5 V, SVDD switch on - - 30 mA IAVDD Analog supply current VBAT = 5 V - 6 - mA ITVDD Transmitter supply current During RF transmission, VBAT = 5 V - 60[3] 150[4] mA Ptot Continuous total power dissipation Tamb = -30 to +85 C [2] - - 0.5 W Tamb Operating temperature range -30 - +85 C PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 3 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 5. Ordering information [1] xx refers to the ROM code version. The ROM code functionalities are described in the User-Manual document. Each ROM code has its own User-Manual. [2] This NXP IC is licensed under Innovatron’s ISO/IEC 14443 Type B patent license. [3] This is tested according the joint IPC/JEDEC standard J-STD-020C of July 2004. [4] Purchase of an NXP Semiconductors IC that complies with one of the NFC Standards (ISO/IEC18.092; ISO/IEC21.481) does not convey an implied license under any patent right on that standards. Table 2. Ordering information Type number Package Name Description Version PN5321A3HN/C1xx[1][2][4] HVQFN40 Heatsink Very thin Quad Flat package; 40 pins, plastic, body 6 x 6 x 0.85 mm; leadless; MSL level 2[3]. SOT618-1 PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 4 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 6. Block diagram Fig 1. Block diagram of PN532 VBAT Power Distribution DVDD RAM ROM Power Clock Reset 80C51 Host T V D D AVDD P V D D PN532 S V D D SI G IN S IG O U T P3 4 Contactless Interface Unit controller (PCR) R S T P D _N interfaces R S T O U T _N RX VMID T X 1 T X 2 Oscin Oscout AUX1 AUX2 LoadModI1I0 N S S M O S I M IS O S C K P35 P 30 P 3 1 IR Q (CIU) RAM P 32 P 33 PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 5 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7. Functional description 7.1 Contactless Interface Unit (CIU) The PN532 CIU is a modem for contactless communication at 13.56 MHz. It supports 6 different operating modes • ISO/IEC 14443A/MIFARE Reader/Writer. • FeliCa Reader/Writer. • ISO/IEC 14443B Reader/Writer • ISO/IEC 14443A/MIFARE Card 1K or MIFARE 4K card emulation mode • FeliCa Card emulation • ISO/IEC 18092, ECMA 340 NFCIP-1 Peer-to-Peer The CIU implements a demodulator and decoder for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The CIU handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC). The CIU supports MIFARE Classic 1K or MIFARE Classic 4K card emulation mode. The CIU supports contactless communication using MIFARE Higher transfer speeds up to 424 kbit/s in both directions. The CIU can demodulate and decode FeliCa coded signals. The CIU digital part handles the FeliCa framing and error detection. The CIU supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The CIU supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer communication scheme, except anticollision which must be implemented in firmware as well as upper layers. In card emulation mode, the CIU is able to answer to a Reader/Writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The CIU generates the load modulation signals, either from its transmitter or from the LOADMOD pin driving an external active circuit. A complete secure card functionality is only possible in combination with a secure IC using the NFC-WI/S2C interface. Compliant to ECMA 340 and ISO/IEC 18092 NFCIP-1 Passive and Active communication modes, the CIU offers the possibility to communicate to another NFCIP-1 compliant device, at transfer speeds up to 424 kbit/s.The CIU handles the complete NFCIP-1 framing and error detection. The CIU transceiver can be connected to an external antenna for Reader/Writer or Card/PICC modes, without any additional active component. PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 6 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7.1.1 Feature list • Frequently accessed registers placed in SFR space • Highly integrated analog circuitry to demodulate and decode received data • Buffered transmitter drivers to minimize external components to connect an antenna. • Integrated RF level detector • Integrated data mode detector • Typical operating distance of 50 mm in ISO/IEC 14443A/MIFARE or FeliCa in Reader/Writer mode depending on the antenna size, tuning and power supply • Typical operating distance of 50 mm in NFCIP-1 mode depending on the antenna size, tuning and power supply • Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa card operation mode of about 100 mm depending on the antenna size, tuning and the external field strength • Supports MIFARE Classic 1K or MIFARE Classic 4K encryption in Reader/Writer mode • Supports MIFARE higher data rate at 212 kbit/s and 424 kbit/s • Supports contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s • Support of the NFC-WI/S2C interface • 64 byte send and receive FIFO-buffer • Programmable timer • CRC Co-processor • Internal self test and antenna presence detector • 2 interrupt sources • Adjustable parameters to optimize the transceiver performance according to the antenna characteristics PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 7 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7.1.2 Simplified block diagram The Analog Interface handles the modulation and demodulation of the analog signals according to the Card emulation mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The data mode detector detects a ISO/IEC 14443-A MIFARE, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN532. The NFC-WI/S2C interface supports communication to secure IC. It also supports digital signals for transfer speeds above 424 kbit/s. The CL UART handles the protocol requirements for the communication schemes in co-operation with the appropriate firmware. The FIFO buffer allows a convenient data transfer from the 80C51 to the CIU and vice versa. Fig 2. Simplify Contactless Interface Unit (CIU) block diagram 80C51 FIFO Serial CL UARTData Switch Data RF Mode Detector Level Detector Analog Interface A nt en na PN532 Contactless Interface Unit PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 8 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7.1.3 Reader/Writer modes All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimal performance. 7.1.3.1 ISO/IEC 14443A Reader/Writer The following diagram describes the communication on a physical level, the communication overview in the Table 3 describes the physical parameters. The internal CRC co-processor calculates the CRC value according the data coding and framing defined in the ISO/IEC 14443A part 3, and handles parity generation internally according to the transfer speed. With appropriate firmware, the PN532 can handle the complete ISO/IEC 14443A/MIFARE protocol. Fig 3. ISO/IEC 14443A/MIFARE Reader/Writer communication diagram Table 3. Communication overview for ISO/IEC 14443A/MIFARE Reader/Writer Communication scheme ISO/IEC 14443A MIFARE MIFARE Higher Baud Rate Baud rate 106 kbit/s 212 kbit/s 424 kbit/s Bit length PN532 to PICC/Card Modulation 100% ASK 100% ASK 100% ASK Bit coding Modified Miller coding Modified Miller coding Modified Miller coding PICC/Card to PN532 Modulation Subcarrier load modulation Subcarrier load modulation Subcarrier load modulation Subcarrier frequency 13.56 MHz⁄16 13.56 MHz⁄16 13.56 MHz⁄16 Bit coding Manchester coding BPSK BPSK 1. PCD to PICC 100% ASK, Miller Coded, Transfer speed 106 to 424 kbit/s 2. PICC to PCD, Subcarrier Load modulation, Manchester Coded or BPSK, Transfer speed 106 to 424 kbit/s Reader/Writer PN532 HOST Battery ISO/IEC 14443A Card / PICC 128 13.56MHz -------------------------- 9.44s 6413.56MHz-------------------------- 4.72s 32 13.56MHz -------------------------- 2.36s PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 9 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller Fig 4. Data coding and framing according to ISO/IEC 14443A PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 10 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7.1.3.2 FeliCa Reader/Writer The following diagram describes the communication at the physical level. Table 4 describes the physical parameters. With appropriate firmware, the PN532 can handle the FeliCa protocol. The FeliCa Framing and coding must comply with the following table: To enable the FeliCa communication a 6-byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2-byte SYNC bytes (B2h, 4Dh) are sent to synchronize the receiver. The following LEN byte indicates the length of the sent data bytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first. To transmit data on the RF interface, the 80C51 has to send the LEN and data bytes to the CIU. The Preamble and SYNC bytes are generated by the CIU automatically and must not be written to the FIFO. The CIU performs internally the CRC calculation and adds the result to the frame. The starting value for the CRC Polynomial is 2 null bytes: (00h), (00h) Example of frame: Fig 5. FeliCa Reader/Writer communication diagram Table 4. Communication overview for FeliCa Reader/Writer Communication scheme FeliCa FeliCa higher baud rate Baud rate 212 kbit/s 424 kbit/s Bit length PN532 to PICC/Card Modulation 8 - 30% ASK 8 - 30% ASK Bit coding Manchester coding Manchester coding PICC/Card to PN532 Modulation >12% ASK >12% ASK Bit coding Manchester coding Manchester coding Table 5. FeliCa Framing and Coding Preamble SYNC LEN n-Data CRC 00h 00h 00h 00h 00h 00h B2h 4Dh Table 6. FeliCa framing and coding 1. Reader/Writer to Card 8 - 30% ASK, Manchester Coded, Baud rate 212 to 424 kbit/s 2. Card to Reader/Writer, >12% ASK load modulation, Manchester Coded, Baud rate 212 to 424 kbit/s Reader/Writer PN532 HOST Battery FeliCa Card 64 13.56MHz -------------------------- 4.72s 3213.56MHz-------------------------- 2.36s PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 11 of 27 Preamble SYNC LEN 2 Data Bytes CRC 00 00 00 00 00 00 B2 4D 03 AB CD 90 35 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7.1.3.3 ISO/IEC 14443B Reader/Writer The CIU supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer communication scheme, except anticollision which must be implemented in firmware as well as upper layers. The following diagram describes the communication at the physical level. Table 7 describes the physical parameters. With appropriate firmware, the PN532 can handle the ISO/IEC 14443B protocol. Fig 6. ISO/IEC 14443B Reader/Writer communication diagram Table 7. Communication overview for ISO/IEC 14443B Reader/Writer Communication scheme ISO/IEC 14443B Type B higher baud rate Baud rate 106 kbit/s 212 kbit/s 424 kbit/s Bit length PN532 to PICC/Card Modulation 8 -14% ASK 8 -14% ASK 8 -14% ASK Bit coding NRZ-L NRZ-L NRZ-L PICC/Card to PN532 Modulation Subcarrier load modulation Subcarrier load modulation Subcarrier load modulation Subcarrier frequency 13.56 MHz⁄16 13.56 MHz⁄16 13.56 MHz⁄16 Bit coding BPSK BPSK BPSK 1. PCD to PICC, 8 - 14% ASK, NRZ-L Coded, Transfer speed 106 to 424 kbit/s 2. PICC to PCD, Subcarrier Load modulation, BPSK, Transfer speed 106 to 424kbit/s Reader/Writer PN532 HOST Battery ISO/IEC 14443B Card / PICC 128 13.56MHz -------------------------- 9.44s 6413.56MHz-------------------------- 4.72s 32 13.56MHz -------------------------- 2.36s PN512_C1_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3.2 — 20 September 2012 120132 12 of 27 NXP Semiconductors PN532/C1 Near Field Communication (NFC) controller 7.1.4 ISO/IEC 18092, ECMA 340 NFCIP-1 operating mode A NFCIP-1 communication takes place between 2 devices: • Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication. • Target: responds to initiator command either in a load modulation scheme in Passive Communication mode or using a self generated and self modulated RF field f
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