VHDL闹钟设计

源代码： Alert模块： library ieee; use ieee.std_logic_1164.all; entity alert is port(dip:in std_logic_vector(3 downto 0); h1,h0,m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号 nao_h_h,nao_h_l,nao_m_h,nao_m_l:in std_logic_vector(3 downto 0); clk:in std_logic; q500,qlk,q1khz:out std_logic); end alert; architecture behav of alert is begin process(clk) begin if clk'event and clk='1' then if m1="0101" and m0="1001" and s1="0101" then----当秒高位为 5，低位为 9时且分高位 为 5 if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为 1或 3或 5或 7时 q500<='1';----低频输出为 1 else q500<='0';----否则输出为 0 end if; end if; if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为 5，低位为 9 时且分高位为 5，----分低位为 9时，也就是“59分 59秒”的时候“报时” qlk<='1';-----高频输出为 1 else qlk<='0'; end if; end if; end process; process(h1,h0,m1,m0,nao_h_h,nao_h_l,nao_m_h,nao_m_l) begin if dip(0)='1' and h1=nao_h_h and h0=nao_h_l and m1=nao_m_h and m0=nao_m_l then q1khz<='1'; else q1khz<='0'; end if; end process; end behav; braz模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity braz is port( dip:in std_logic_vector(3 downto 0); q500,qlk,q1khz:in std_logic; f1khz,f500hz:in std_logic; braz:out std_logic); end entity; architecture behave of braz is begin process(q500,qlk,dip) begin if dip="0010" or dip="1110" or dip="1010" or dip="0110" then braz<='1'; end if; if q500='1' then braz<=f500hz; elsif qlk='1' or q1khz='1' then braz<=f1khz; else braz<='1'; end if; end process; end behave ; 秒计数模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity count60 is port(carry:in std_logic; one:out std_logic_vector(3 downto 0); ten:out std_logic_vector(3 downto 0); full: out std_logic); end count60; architecture behave of count60 is begin process (carry) variable ones: std_logic_vector(3 downto 0):="0000"; variable tens: std_logic_vector(3 downto 0):="0000"; begin if rising_edge(carry) then ones:=ones+1; if (tens="0101" and ones="1010")then ones:=(others=>'0');tens:=(others=>'0');full<='1'; elsif (ones="1010") then tens:=tens+1;ones:="0000";full<='0'; end if; end if; one<=ones; ten<=tens; end process; end behave; 显示模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity display is port (clk:in std_logic; a,b,c,d:in std_logic_vector(3 downto 0); mux_out:out std_logic_vector(3 downto 0); wei1,wei2,wei3,wei4:out std_logic); end display; architecture behave of display is signal sel:integer range 0 to 3; begin process(a,b,c,d,clk) begin if rising_edge(clk) then sel<=sel+1; case sel is when 0 =>mux_out<=a; wei4<='0';wei3<='1';wei2<='1';wei1<='1'; when 1 =>mux_out<=b; wei4<='1';wei3<='0';wei2<='1';wei1<='1'; when 2 =>mux_out<=c; wei4<='1';wei3<='1';wei2<='0';wei1<='1'; when 3=>mux_out<=d; wei4<='1';wei3<='1';wei2<='1';wei1<='0'; when others =>mux_out<="1100"; end case; end if; end process; end behave; 消抖模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity debounce is port(key:in std_logic_vector(3 downto 0); clk:in std_logic; key_valid:out std_logic); end debounce; architecture behave of debounce is begin process(clk,key) variable cnt:integer range 0 to 31; begin if (key="0111" or key="1011" or key="1101" or key="1110")then if(clk'event and clk='1') then if cnt=31 then key_valid<='1';--key pressed else key_valid<='0';--no key pressed cnt:=cnt+1;--cnt plus one end if; end if; else cnt:=0;--no key pressed,the conter reset key_valid<='0';--no key pressed end if; end process; end behave; 闹钟模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity naozhong is port( key:in std_logic_vector(3 downto 0); key_valid:in std_logic; nao_h_ten :out std_logic_vector(3 downto 0); nao_h_one :out std_logic_vector(3 downto 0); nao_m_ten :out std_logic_vector(3 downto 0); nao_m_one :out std_logic_vector(3 downto 0)); end naozhong; architecture behave of naozhong is signal nao_h:integer range 0 to 23:=12; signal nao_m:integer range 0 to 59; begin process(key,key_valid) begin if rising_edge(key_valid) then if (key="1110") then if(nao_h>=23) then nao_h<=0; else nao_h<=nao_h+1; end if; end if; end if; end process; process(key,key_valid) begin if rising_edge(key_valid) then if (key="0111") then if(nao_m>=59) then nao_m <=0; else nao_m<=nao_m+1; end if; end if; end if; end process; process(nao_h) begin case nao_h is when 0|10|20 => nao_h_one<="0000"; when 1|11|21 => nao_h_one<="0001"; when 2|12|22 => nao_h_one<="0010"; when 3|13|23=> nao_h_one<="0011"; when 4|14=> nao_h_one<="0100"; when 5|15=> nao_h_one<="0101"; when 6|16=> nao_h_one<="0110"; when 7|17=> nao_h_one<="0111"; when 8|18=> nao_h_one<="1000"; when 9|19=> nao_h_one<="1001"; when others =>nao_h_one<="1110"; end case; case nao_h is when 0|1|2|3|4|5|6|7|8|9 => nao_h_ten<="0000"; when 10|11|12|13|14|15|16|17|18|19 => nao_h_ten<="0001"; when 20|21|22|23=> nao_h_ten<="0010"; when others =>nao_h_ten<="1110"; end case; end process; process(nao_m) begin case nao_m is when 0|10|20|30|40|50 => nao_m_one<="0000"; when 1|11|21|31|41|51 => nao_m_one<="0001"; when 2|12|22|32|42|52 => nao_m_one<="0010"; when 3|13|23|33|43|53 => nao_m_one<="0011"; when 4|14|24|34|44|54 => nao_m_one<="0100"; when 5|15|25|35|45|55 => nao_m_one<="0101"; when 6|16|26|36|46|56 => nao_m_one<="0110"; when 7|17|27|37|47|57 => nao_m_one<="0111"; when 8|18|28|38|48|58 => nao_m_one<="1000"; when 9|19|29|39|49|59 => nao_m_one<="1001"; when others =>nao_m_one<="1110"; end case; case nao_m is when 0|1|2|3|4|5|6|7|8|9 => nao_m_ten<="0000"; when 10|11|12|13|14|15|16|17|18|19 => nao_m_ten<="0001"; when 20|21|22|23|24|25|26|27|28|29 => nao_m_ten<="0010"; when 30|31|32|33|34|35|36|37|38|39 => nao_m_ten<="0011"; when 40|41|42|43|44|45|46|47|48|49 => nao_m_ten<="0100"; when 50|51|52|53|54|55|56|57|58|59 => nao_m_ten<="0101"; when others =>nao_m_ten<="1110"; end case; end process; end behave; 译码输出模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity yima is port(clk:in std_logic; bcd:in std_logic_vector(3 downto 0); eight:out std_logic_vector(7 downto 0)); end yima; architecture behave of yima is begin process (clk) begin case bcd is when "0000"=>eight<="11000000"; when "0001"=>eight<="11111001"; when "0010"=>eight<="10100100"; when "0011"=>eight<="10110000"; when "0100"=>eight<="10011001"; when "0101"=>eight<="10010010"; when "0110"=>eight<="10000010"; when "0111"=>eight<="11111000"; when "1000"=>eight<="10000000"; when "1001"=>eight<="10010000"; when others=>eight<="11111111"; end case; end process; end behave; 分频模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned; entity fenpin is port(clk:in std_logic; f1khz:out std_logic); end fenpin; architecture behav of fenpin is signal mid:std_logic; begin process(clk) variable cnum:integer range 0 to 25000; begin if (clk'event and clk='1') then cnum:=cnum+1; if cnum=25000 then mid <= not mid; cnum:=0; end if; f1khz<=mid; end if; end process; end behav; 1000分频模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity div1000 is port (clk:in std_logic; f1hz:out std_logic); end entity; architecture behav of div1000 is signal count:integer range 0 to 1000; begin process(clk) begin if rising_edge(clk) then count<=count+1; if count=1000 then f1hz<='1'; else f1hz<='0'; end if; end if; end process; end behav; 分计数模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mincount is port(carry:in std_logic; key_valid:in std_logic; key:in std_logic_vector(3 downto 0); ten :out std_logic_vector(3 downto 0); one :out std_logic_vector(3 downto 0); full: out std_logic); end mincount; architecture behave of mincount is signal min:integer range 0 to 59; signal min_temp:integer range 0 to 59; signal min_temp1:integer range 0 to 59; begin process(carry) begin if rising_edge(carry) then min_temp<=min_temp+1; if(min_temp=59) then full<='1'; min_temp<=0; else full<='0'; end if; end if; end process; process(key,key_valid) begin if rising_edge(key_valid) then if (key="1101") then min_temp1<=min_temp1+1; if(min_temp1>=59) then min_temp1 <=0; end if; end if; end if; end process; process(min) begin min<=(min_temp+min_temp1) mod(60); case min is when 0|10|20|30|40|50 => one<="0000"; when 1|11|21|31|41|51 => one<="0001"; when 2|12|22|32|42|52 => one<="0010"; when 3|13|23|33|43|53 => one<="0011"; when 4|14|24|34|44|54 => one<="0100"; when 5|15|25|35|45|55 => one<="0101"; when 6|16|26|36|46|56 => one<="0110"; when 7|17|27|37|47|57 => one<="0111"; when 8|18|28|38|48|58 => one<="1000"; when 9|19|29|39|49|59 => one<="1001"; when others =>one<="1110"; end case; case min is when 0|1|2|3|4|5|6|7|8|9 => ten<="0000"; when 10|11|12|13|14|15|16|17|18|19 => ten<="0001"; when 20|21|22|23|24|25|26|27|28|29 => ten<="0010"; when 30|31|32|33|34|35|36|37|38|39 => ten<="0011"; when 40|41|42|43|44|45|46|47|48|49 => ten<="0100"; when 50|51|52|53|54|55|56|57|58|59 => ten<="0101"; when others =>ten<="1110"; end case; end process; end behave; 小时计数模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity hcount is port( carry:in std_logic; key:in std_logic_vector(3 downto 0); key_valid:in std_logic; ten :out std_logic_vector(3 downto 0); one :out std_logic_vector(3 downto 0)); end hcount; architecture behave of hcount is signal min_temp:integer range 0 to 23; signal min_temp2 :integer range 0 to 23; signal min:integer range 0 to 23; begin process(carry) begin if rising_edge(carry) then min_temp2<=min_temp2+1; if(min_temp2=23) then min_temp2<=0; end if; end if; min<=(min_temp+min_temp2) mod(24); end process; process(key,key_valid) begin if rising_edge(key_valid) then if (key="1011") then if(min_temp>=23) then min_temp <=0; else min_temp<=min_temp+1; end if; end if; end if; end process; process(min) begin case min is when 0|10|20 => one<="0000"; when 1|11|21 => one<="0001"; when 2|12|22 => one<="0010"; when 3|13|23=> one<="0011"; when 4|14=> one<="0100"; when 5|15=> one<="0101"; when 6|16=> one<="0110"; when 7|17=> one<="0111"; when 8|18=> one<="1000"; when 9|19=> one<="1001"; when others =>one<="1110"; end case; case min is when 0|1|2|3|4|5|6|7|8|9 => ten<="0000"; when 10|11|12|13|14|15|16|17|18|19 => ten<="0001"; when 20|21|22|23=> ten<="0010"; when others =>ten<="1110"; end case; end process; end behave; 模式转换模块： library ieee; use ieee.std_logic_1164.all; entity modem is port(dip:in std_logic_vector (3 downto 0); hourH,hourL,minH,minL,secH,secL:in std_logic_vector (3 downto 0); nao_h_h,nao_h_l,nao_m_h,nao_m_l:in std_logic_vector (3 downto 0); out4,out3,out2,out1:out std_logic_vector (3 downto 0)); end modem; architecture behave of modem is signal mode:std_logic; signal mode_nao:std_logic; begin process(dip) begin if dip(2)='0' then mode_nao<='1'; elsif dip(3)='0' then mode<='1'; else mode_nao<='0';mode<='0'; end if; end process; process(mode) begin if (mode_nao='1')then out4<=nao_h_h; out3<=nao_h_l; out2<=nao_m_h; out1<=nao_m_l; elsif mode='1' then out4<=hourH; out3<=hourL; out2<=minH; out1<=minL; else out4<=minH; out3<=minL; out2<=secH; out1<=secL; end if; end process; end behave; 500分频模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity fz500Hz is port (clk:in std_logic; f500hz:out std_logic); end entity; architecture behav of fz500Hz is signal count:integer range 0 to 1; begin process(clk) begin if rising_edge(clk) then count<=count+1; if count=1 then f500hz<='1'; else f500hz<='0'; end if; end if; end process; end behav;