MC100EL1648-D 压控振荡器

© Semiconductor Components Industries, LLC, 2008 August, 2008 − Rev. 8 1 Publication Order Number: MC100EL1648/D MC100EL1648 5 V ECL Voltage Controlled Oscillator Amplifier Description The MC100EL1648 is a voltage controlled oscillator amplifier that requires an external parallel tank circuit consisting of the inductor (L) and capacitor (C). A varactor diode may be incorporated into the tank circuit to provide a voltage variable input for the oscillator (VCO). This device may also be used in many other applications requiring a fixed frequency clock. The MC100EL1648 is ideal in applications requiring a local oscillator, systems that include electronic test equipment, and digital high−speed telecommunications. The MC100EL1648 is based on the VCO circuit topology of the MC1648. The MC100EL1648 uses advanced bipolar process technology which results in a design which can operate at an extended frequency range. The ECL output circuitry of the MC100EL1648 is not a traditional open emitter output structure and instead has an on−chip termination emitter resistor, RE, with a nominal value of 510 �. This facilitates direct ac−coupling of the output signal into a transmission line. Because of this output configuration, an external pull−down resistor is not required to provide the output with a dc current path. This output is intended to drive one ECL load (3.0 pF). If the user needs to fanout the signal, an ECL buffer such as the EL16 (EL11, EL14) type Line Receiver/Driver should be used. Features • Typical Operating Frequency Up to 1100 MHz • Low−Power 19 mA at 5.0 Vdc Power Supply • PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.5 V • Input Capacitance = 6.0 pF (TYP) • Pb−Free Packages are Available NOTE: The MC100EL1648 is NOT useable as a crystal oscillator. VEE VCCVCC VEE OUTPUT AGC BIAS POINT TANK EXTERNAL TANK CIRCUIT Figure 1. Logic Diagram MARKING DIAGRAMS* SOEIAJ−14 M SUFFIX CASE 965 1 14 14 1 *For additional marking information, refer to Application Note AND8002/D. SOIC−8 D SUFFIX CASE 751 TSSOP−8 DT SUFFIX CASE 948R http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ORDERING INFORMATION KEL1648 ALYWG 1648 ALYW� � 1 8 1 8 1 8 K1648 ALYW � 1 8 DFN8 MN SUFFIX CASE 506AA 6 L M � � 1 4 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G or � = Pb−Free Package (Note: Microdot may be in either location) MC100EL1648 http://onsemi.com 2 1314 12 11 10 9 8 21 3 4 5 6 7 VCC NC TANK NC BIAS NC VEE VCC NC OUT NC AGC NC VEE BIAS TANK VEE VCC VCC AGC OUT Figure 2. Pinout Assignments VEE 8 Lead 14 Lead Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. 1 2 3 7 4 568 Table 1. PIN DESCRIPTION Pin No. Symbol Description8 Lead 14 Lead ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 12 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TANK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OSC Input Voltage ÁÁÁÁ ÁÁÁÁ 2, 3 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 1, 14 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VCC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive Supply ÁÁÁÁ ÁÁÁÁ 4 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 3 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ OUT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ECL Output ÁÁÁÁ ÁÁÁÁ 5 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 5 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ AGC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Automatic Gain Control Input ÁÁÁÁ ÁÁÁÁ 6, 7 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 7, 8 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VEE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Negative Output ÁÁÁÁ ÁÁÁÁ 8 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 10 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ BIAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OSC Input Reference Voltage ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 2, 4, 7, 9, 11, 13ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ NC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ No Connect ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Thermal Exposed Pad ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ EP ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave uncon- nected, floating open. Table 2. ATTRIBUTES Characteristic Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 1 kV > 100 V > 1 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg SOIC−8 TSSOP−8 SOEIAJ−14 DFN8 Level 1 Level 1 Level 3 Level 1 Level 1 Level 3 Level 3 Level 1 Flammability Rating Oxygen Index: 23 to 34 UL 94 V−0 @ 0.125 in Transistor Count 11 Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. MC100EL1648 http://onsemi.com 3 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Power Supply PECL Mode VEE = 0 V 7 to 0 V VEE Power Supply NECL Mode VCC = 0 V −7 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V VI � VCC VI � VEE 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C �JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W �JC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W �JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W �JC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W �JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−14 SOIC−14 150 110 °C/W °C/W �JC Thermal Resistance (Junction−to−Case) Standard Board SOIC−14 41 to 44 °C/W �JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder Pb Pb−Free <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C �JC Thermal Resistance (Junction−to−Case) (Note 1) DFN8 35 to 40 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MC100EL1648 http://onsemi.com 4 Table 4. PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V +0.8 / −0.5 V (Note 2) Symbol Characteristic −40°C 25°C 85°C UnitMin Typ Max Min Typ Max Min Typ Max IEE Power Supply Current 13 19 25 13 19 25 13 19 25 mA VOH Output HIGH Voltage (Note 3) 3950 4170 4610 3950 4170 4610 3950 4170 4610 mV VOL Output LOW Voltage (Note 3) 3040 3410 3600 3040 3410 3600 3040 3410 3600 mV AGC Automatic Gain Control Input 1690 1980 1690 1980 1690 1980 mV VBIAS Bias Voltage (Note 4) 1650 1800 1650 1800 1650 1800 mV VIL 1.5 1.35 1.2 V VIH 2.0 1.85 1.7 V IL Input Current −5.0 −5.0 −5.0 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Output parameters vary 1:1 with VCC. 3. 1.0 M� impedance. 4. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point. Table 5. NECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −5.0 V +0.8 / −0.5 V (Note 5) Symbol Characteristic −40°C 25°C 85°C UnitMin Typ Max Min Typ Max Min Typ Max IEE Power Supply Current 13 19 25 13 19 25 13 19 25 mA VOH Output HIGH Voltage (Note 6) −1050 −830 −399 −1050 −830 −399 −1050 −830 −399 mV VOL Output LOW Voltage (Note 6) −1960 −1590 −1400 −1960 −1590 −1400 −1960 −1590 −1400 mV AGC Automatic Gain Control Input −3310 −3020 −3310 −3020 −3310 −3020 mV VBIAS Bias Voltage (Note 7) −3350 −3200 −3350 −3200 −3350 −3200 mV VIL −3.5 −3.65 −3.8 V VIH −3.0 −3.15 −3.3 V IL Input Current −5.0 −5.0 −5.0 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Output parameters vary 1:1 with VCC. 6. 1.0 M� impedance. 7. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point. MC100EL1648 http://onsemi.com 5 GENERIC TEST CIRCUITS: Bypass to Supply Opposite GND Figure 3. Typical Test Circuit with Alternate Tank Circuits 0.1�F CL 8 (10) 1 (12) 4 (3) VCC * Use high impedance probe (>1.0 M� must be used). ** The 1200 � resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be CT−070−50 or equivalent. 3 (1) 2 (14) C L 4 (3) VCC 3 (1) 2 (14) VIN FOUT Tank #1 8 (10) 1 (12) * Note 1 Capacitor for tank may be variable type. (See Tank Circuit #3.) Note 2 Use high impedance probe (> 1 M� ).Test Point FOUT Tank #2 Tank Circuit Option #1, Varactor Diode Tank Circuit Option #2, Fixed LC L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH) C = MMBV609 L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH) C = 3.0−35pF Variable Capacitance (@ 10 pF) 0.1 �F 0.1 �F 0.1 �F 0.1 �F 8 pin (14 pin) Lead Package 8 pin (14 pin) Lead Package ** 5 (5)6 (7) 7 (8) VEE 0.1 �F 0.1 �F0.01 �F100 �F 5 (5)6 (7) 7 (8) VEE 0.1 �F 0.1 �F0.01 �F100 �F 1 K� 50% ta tb VP-P PRF = 1.0MHz Duty Cycle (Vdc) - ta tb Figure 4. Output Waveform MC100EL1648 http://onsemi.com 6 OPERATION THEORY Figure 5 illustrates the simplified circuit schematic for the MC100EL1648. The oscillator incorporates positive feedback by coupling the base of transistor Q6 to the collector of Q7. An automatic gain control (AGC) is incorporated to limit the current through the emitter−coupled pair of transistors (Q7 and Q6) and allow optimum frequency response of the oscillator. In order to maintain the high quality factor (Q) on the oscillator, and provide high spectral purity at the output, transistor Q4 is used to translate the oscillator signal to the output differential pair Q2 and Q3. Figure 16 indicates the high spectral purity of the oscillator output (pin 4 on 8−pin SOIC). Transistors Q2 and Q3, in conjunction with output transistor Q1, provide a highly buffered output that produces a square wave. The typical output waveform can be seen in Figure 4. The bias drive for the oscillator and output buffer is provided by Q9 and Q11 transistors. In order to minimize current, the output circuit is realized as an emitter−follower buffer with an on chip pull−down resistor RE. Figure 5. Circuit Schematic AGCVEETANKBIASVEE VCC VCC Q4 Q3 Q2 Q1 Q5 D1 Q8 Q7 Q6 Q9 Q10Q11 D2 OUTPUT 800 � 1.36 K� 1.6 K� 3.1 K� 660 � 167 � 400 � 330 � 16 K� 82 � 400 � 660 � 510 � 2 (14) 3 (1) 4 (3) 1 (12) 5 (5)8 (10)7 (8) 6 (7) 8 pin (14 pin) Lead Package MC100EL1648 http://onsemi.com 7 Figure 6. Low Frequency Plot Figure 7. High Frequency Plot 0.1�F 1200* CL 8 (10) 1 (12) 4 (3) SIGNAL UNDER TEST 10�F0.1�F 3(1)2 (14) Tank #3 L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH) C = 3.0−35 pF Variable Capacitance (@ 10 pF) * The 1200 � resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be CT−070−50 or equivalent. 0.1�F 1200* CL 8 (10) 1 (12) 4 (3) SIGNAL UNDER TEST 10�F0.1�F 3(1)2 (14) Tank #3 L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH) C = 3.0−35 pF Variable Capacitance (@ 10 pF) * The 1200 � resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be CT−070−50 or equivalent.FR E Q U E N C Y ( M H z) CAPACITANCE (pF) 25 20 15 10 5 0 0 300 500 1000 2000 10000 Measured Frequency (MHz) Calculated Frequency (MHz) F R E Q U E N C Y ( M H Z ) CAPACITANCE (pF) 100 80 60 40 20 0 0 0.2 0.3 300 30 Measured Frequency (MHz) Calculated Frequency (MHz) 8 pin (14 pin) Lead Package 8 pin (14 pin) Lead Package 5 (5)6 (7) 7 (8) VEE 0.1 �F 0.1 �F0.01 �F100 �F 5 (5)6 (7) 7 (8) VEE 0.1 �F 0.1 �F0.01 �F100 �F MC100EL1648 http://onsemi.com 8 FIXED FREQUENCY MODE The MC100EL1648 external tank circuit components are used to determine the desired frequency of operation as shown in Figure 8, tank option #2. The tank circuit components have direct impact on the tuning sensitivity, IEE, and phase noise performance. Fixed frequency of the tank circuit is usually realized by an inductor and capacitor (LC network) that contains a high Quality factor (Q). The plotted curve indicates various fixed frequencies obtained with a single inductor and variable capacitor. The Q of the components in the tank circuit has a direct impact on the resulting phase noise of the oscillator. In general, when the Q is high the oscillator will result in lower phase noise. Figure 8. Fixed Frequency LC Tank F R E Q U E N C Y ( M H z) CAPACITANCE (pF) 470 370 270 170 70 −30 0.3 300 500 1000 2000 10000 Measured Frequency (MHz) Calculated Frequency (MHz) 570 0 0.1 �F CL 8 (10) 1 (12) 4 (3) VCC 3 (1) 2 (14) Test Point FOUT Tank #2 5 (5)6 (7) 7 (8) VEE 0.1 �F 0.1 �F0.01 �F100 �F 0.1 �F 0.1 �F Note 1 Capacitor for tank may be variable type. (See Tank Circuit #3.) Note 2 Use high impedance probe (> 1 M� ). L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH) C = 3.0−35 pF Variable Capacitance (@ 10 pF) 8 pin (14 pin) lead package QL ≥ 100 Only high quality surface−mount RF chip capacitors should be used in the tank circuit at high frequencies. These capacitors should have very low dielectric loss (high−Q). At a minimum, the capacitors selected should be operating at 100 MHz below their series resonance point. As the desired frequency of operation increases, the values of the tank capacitor will decrease since the series resonance point is a function of the capacitance value. Typically, the inductor is realized as a surface−mount chip or a wound coil. In addition, the lead inductance and board inductance and capacitance also have an impact on the final operating point. The following equation will help to choose the appropriate values for your tank circuit design. f0 � 1 2� LT * CT� Where LT = Total Inductance CT = Total Capacitance Figure 9 and Figure 10 represent the ideal curve of inductance/capacitance versus frequency with one known tank component. This helps the designer of the tank circuit to choose desired value of inductor/capacitor component for the wanted frequency. The lead inductance and board inductance and capacitance will also have an impact on the tank component values (inductor and capacitor). Figure 9. Capacitor Value Known (5 pF) Inductance vs. Frequency with 5 pF Cap 5 10 15 20 25 30 35 40 45 50 0 700 1000 1300 160400 FREQUENCY (MHz) IN D U C TA N C E ( nH ) Figure 10. Inductor Value Known (4 nH) Capacitance vs. Frequency with 4 nH Inductance 5 10 15 20 25 30 35 40 45 50 0 700 1000 1300 160400 FREQUENCY (Hz) C A P A C IT A N C E ( F ) MC100EL1648 http://onsemi.com 9 VOLTAGE CONTROLLED MODE The tank circuit configuration presented in Figure 11, Voltage Controlled Varactor Mode, allows the VCO to be tuned across the full operating voltage of the power supply. Deriving from Figure 6, the tank capacitor, C, is replaced with a varactor diode whose capacitance changes with the voltage applied, thus changing the resonant frequency at which the VCO tank operates as shown in Figure 3, tank option #1. The capacitive component in Equation 1 also needs to include the input capacitance of the device and other circuit and parasitic elements. Figure 11. Voltage Controlled Varactor Mode 50 70 90 110 130 150 170 190 0 2 4 6 8 10 F R E Q U E N C Y ( M H z) Vin, INPUT VOLTAGE (V) Figure 12. Plot 1. Dual Varactor MMBV609, VIN vs. Frequency C L 4 (3) VCC 3 (1) 2 (14) VIN FOUT Tank #1 8 (10) 1 (12) * 0.1 �F 0.1 �F 5 (5)6 (7) 7 (8) VEE 0.1 �F 0.1 �F0.01 �F100 �F ** 1 K� *Use high impedance probe (>1.0 Meg� must be used). **The 1200 � resistor and the scope termination imped- ance constitute a 25:1 attenuator probe. Coax shall be CT−070−50 or equivalent. L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH) C = MMBV609 8 pin (14 pin) lead package When operating the oscillator in the voltage controlled mode with Tank Circuit #1 (Figure 3), it should be noted that the cathode of the varactor diode (D), pin 8 (for 8 lead package) or pin 10 (for 14 lead package) should be biased at least 1.4 V above VEE. Typical transfer characteristics employing the capacitance of the varactor diode (plus the input capacitance of the device, about 6.0 pF typical) in the voltage controlled mode is shown in Plot 1, Dual Varactor MMBV609 Vin vs. Frequency. Figure 6, Figure 7, and Figure 8 show the accuracy of the measured frequency with the different variable capacitance values. The 1.0 k� resistor in Figure 11 is used to protect the varactor diode during testing. It is not necessary as long as the dc input voltage does not cause the diode to become forward biased. The tuning range of the oscillator in the voltage controlled mode may be calculated as follows: f max f min � CD(max)� CS� CD(min)� CS� Where f min � 1 2� � L(CD(max)� CS �� Where CS = Shunt Capacitance (input plus external capacitance) CD = Varactor Capacitance as a function of bias voltage Good RF and low−frequency bypassing is necessary on the device power supply pins. Capacitors on the AGC pin and the input varactor trace should be used to bypass the AGC point and the VCO input (varactor diode), guaranteeing only dc levels at these points. For output frequency operation between 1.0 MHz and 50 MHz, a 0.1 �F capacitor is sufficient. At higher frequencies, smaller values of capacitance should be used; at lower frequencies, larger values of capacitance. At high frequencies, the value of bypass capacitors depends directly on the physical layout of the system. All bypassing should be as close to the package pins as possible to minimize unwanted lead inductance. Several different capacitors may be needed to bypass various frequencies. MC100EL1648 http://onsemi.com 10 WAVE−FORM CONDITIONING − SINE OR SQUARE WAVE The peak−to−peak swing of the tank circuit is set internally by the AGC pin. Since the voltage swing of the tank circuit provides the drive for the output buffer, the AGC potential directly affects the output waveform. If it is desired to have a sine wave at the output of the MC100EL1648, a series resistor is tied from the AGC point to the most negative power potential (ground if positive volt supply is used, −5.2 V if a negative supply is used) as shown in Figure 13. At frequencies above 100 MHz typical, it may be desirable to increase the tank circuit peak−to−peak voltage in order to shape the signal into a more square waveform at the output of the MC100EL1648. This is accomplished by tying a series resistor (1.0 k� minimum) from the AGC to the most positive power potential (+5.0 V if a positive volt supply is used, ground if a −5.2 V supply is used). Figure 14 illustrates this principle. Figure 13. Method of Obtaining a Sine−Wave Output 10 12 7 8 3 5 Output +5.0Vdc 1 1