Cyclone_II_EP2C20_原理图

5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of COVER PAGE 1.1A Altera Cyclone II Starter Board B 1 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of COVER PAGE 1.1A Altera Cyclone II Starter Board B 1 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of COVER PAGE 1.1A Altera Cyclone II Starter Board B 1 21Tuesday, October 03, 2006 18 ~ 19 TOP 01 ~ 03 04 ~ 04 21 ~ 21 PAGE 05 ~ 07 13 ~ 17 SCHEMATIC Altera Cyclone II FPGA Starter Board 20 ~ 20 CONTENT COVER PAGE , TOP AUDIO WM8731 DISPLAY VGA , 7SEGMENT ,LED EP2C20 EP2C20 BANK1..BANK8 , POWER , CONFIG 08 ~ 12 INPUT CLOCK , PS2 , RS232 , KEY , SWITCH , CONNECT MEMORY SRAM , DRAM , FLASH , SD CARD POWER POWER BLASTER USB BLASTER 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of PLACEMENT 1.1A Altera Cyclone II Starter Board B 2 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of PLACEMENT 1.1A Altera Cyclone II Starter Board B 2 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of PLACEMENT 1.1A Altera Cyclone II Starter Board B 2 21Tuesday, October 03, 2006 LINE IN LINE OUT MIC IN WM8731 VGA OUTPUT PS2 KEYBORAD RS232 SD CARD 4BIT RGB EP2C20 FLASHSRAMSDRAM G P I O _ 1 G P I O _ 0 EXT CLK L E D 0 L E D 1 L E D 2 L E D 3 L E D 4 L E D 5 L E D 6 L E D 7 L E D 8 L E D 9 S W 0 S W 1 S W 2 S W 3 S W 4 S W 5 S W 6 S W 7 S W 8 S W 9 H E X 0 H E X 1 H E X 2 H E X 3 M3128 EPCS4 FT245 L E D 1 0 L E D 1 1 L E D 1 2 L E D 1 3 L E D 1 4 L E D 1 5 L E D 1 6 L E D 1 7 K E Y 0 K E Y 1 K E Y 2 K E Y 3 USB BLASTER DC 7.5V 5 5 4 4 3 3 2 2 1 1 D D C C B B A A AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK I2C_SCLK AUD_XCK AUD_ADCDAT DATA0 TDO NSTATUS NCSO NCE CONF_DONE TCK NCONFIG TDI TMS ASDO DCLK HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] SW[0..9] KEY[0..3] UART_RXD 50MHZ EXT_CLOCK PS2_DAT PS2_CLK UART_TXD SD_CLK 27MHZ FLASH_OE FLASH_RESET I2C_SCLK EXT_CLOCK KEY[0..3] UART_RXD PS2_DAT SD_CMD FLASH_A[0..21] FLASH_CE SD_DAT3 TDO DATA0 50MHZ SW[0..2] FLASH_WE LINK_D0 LINK_D1 LINK_D2LINK_D3 27MHZ HEX3_D[0..6] VGA_B[0..3] VGA_R[0..3] VGA_G[0..3] LED[0..17] VGA_VSYNC VGA_HSYNC SW[3..6] SW[7..9] GPIO_B[0..71] GPIO_B[0..35] 24MHZ GPIO_B[36..71] FLASH_CE FLASH_OE FLASH_A[0..21] DRAM_A[0..11] SRAM_A[0..17] DRAM_LDQM DRAM_UDQM DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS SRAM_WE SRAM_CE SRAM_OE SRAM_UB SRAM_LB SD_DAT3 SD_CMD SD_CLK FLASH_RESET FLASH_WE FLASH_D[0..7] DRAM_D[0..15] SRAM_D[0..15] SD_DAT I2C_SDAT UART_TXD AUD_ADCLRCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_XCK PS2_CLK NCONFIG TMS TDI CONF_DONE NSTATUS NCE TCK ASDO AUD_ADCDAT I2C_SDAT VGA_HSYNC VGA_VSYNC VGA_R[0..3] VGA_G[0..3] VGA_B[0..3] LED[0..17] LINK_D3 LINK_D0 LINK_D1 NCSO DCLK 24MHZ SD_DAT LINK_D2 SRAM_D[0..15] FLASH_D[0..7] SRAM_CE SRAM_WE SRAM_OE SRAM_UB SRAM_LB DRAM_CS DRAM_BA1 DRAM_CAS DRAM_CLK DRAM_D[0..15] DRAM_LDQM DRAM_UDQM DRAM_BA0 DRAM_RAS DRAM_CKE DRAM_WE SRAM_A[0..17] DRAM_A[0..11] HEX3_D[0..6] HEX2_D[0..6] HEX1_D[0..6] HEX0_D[0..6] Title Size Document Number Rev Date: Sheet of TOP LEVEL 1.1A Altera Cyclone II Starter Board B 3 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of TOP LEVEL 1.1A Altera Cyclone II Starter Board B 3 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of TOP LEVEL 1.1A Altera Cyclone II Starter Board B 3 21Tuesday, October 03, 2006 INPUT IN/OUT PS2_CLK PS2_DAT UART_TXD UART_RXD KEY[0..3] 50MHZ EXT_CLOCK 27MHZ SW[0..9] GPIO_B[0..35] GPIO_B[36..71] USB BLASTER PAGE 21 DATA0 NCSO DCLK ASDO TDO TMS TDI NCONFIG TCK CONF_DONE NCE NSTATUS LINK_D3 LINK_D0 LINK_D1 LINK_D2 24MHZ MEMORY PAGE 18-19 FLASH_RESET FLASH_WE FLASH_A[0..21] FLASH_CE FLASH_OE FLASH_D[0..7] DRAM_A[0..11] DRAM_LDQM DRAM_UDQM DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_D[0..15] DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS SRAM_A[0..17] SRAM_D[0..15] SRAM_WE SRAM_CE SRAM_OE SD_DAT SD_CMD SD_CLK SRAM_UB SRAM_LB SD_DAT3 DISPLAY PAGE 5-6 HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] VGA_B[0..3] VGA_G[0..3] LED[0..17] VGA_VSYNC VGA_HSYNC VGA_R[0..3] AUDIO PAGE 4 AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK AUD_ADCDAT I2C_SDATI2C_SCLK AUD_XCK EP2S35 EP2C20 NCONFIG TDI TMS TDO CONF_DONE NSTATUS TCK NCE ASDO DCLK NCSO DATA0 FLASH_A[0..21] FLASH_D[0..7] SD_DAT SD_CLK SD_CMD KEY[0..3] SRAM_CE SRAM_WE SRAM_A[0..17] SRAM_D[0..15] SRAM_OE FLASH_CE FLASH_OE FLASH_RESET FLASH_WE 27MHZ LINK_D2 SD_DAT3 LINK_D3 AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_ADCLRCK AUD_ADCDAT I2C_SCLK I2C_SDAT UART_RXD UART_TXD PS2_CLK PS2_DAT HEX3_D[0..6] HEX2_D[0..6] HEX1_D[0..6] HEX0_D[0..6] SW[0..2] DRAM_UDQM DRAM_LDQM DRAM_D[0..15] DRAM_BA1 DRAM_CS DRAM_BA0 DRAM_RAS DRAM_CKE DRAM_CAS DRAM_CLK DRAM_WE DRAM_A[0..11] 50MHZ EXT_CLOCK SRAM_UB SRAM_LB LINK_D0 LINK_D1 VGA_B[0..3] VGA_G[0..3] VGA_VSYNC VGA_HSYNC VGA_R[0..3] LED[0..17] SW[3..6] SW[7..9] 24MHZ GPIO_B[0..71] PWR PAGE 20 5 5 4 4 3 3 2 2 1 1 D D C C B B A A I2C_SCLK I2C_SDAT AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK AUD_ADCDAT I2C_SDAT I2C_SCLK AUD_XCK A_VCC33 A_VCC33 A_VCC33 A_VCC33 VCC33 VCC33 AGNDAGND AGND AGNDAGND AGND AGND AGNDAGND AGND AGND AGND Title Size Document Number Rev Date: Sheet of AUDIO 1.1A Altera Cyclone II Starter Board A 4 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of AUDIO 1.1A Altera Cyclone II Starter Board A 4 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of AUDIO 1.1A Altera Cyclone II Starter Board A 4 21Tuesday, October 03, 2006 I2C ADDRESS READ IS 0x34 I2C ADDRESS WRITE IS 0x35 R8 680R8 680 BC3 0.1U BC3 0.1U TC23 100U/6V TC23 100U/6V C1 1U C1 1U TC21 100U/6V TC21 100U/6V C2 1U C2 1U R7 330R7 330 BC4 0.1U BC4 0.1U R11 47K R11 47K C5 1000P C5 1000P L 1 R 2 G N D 3 N C R 4 N C L 5 J1 MICINJ1 MICIN C3 1U C3 1U R12 0R12 0 L 1 R 2 G N D 3 N C R 4 N C L 5 J2 LINEINJ2 LINEIN BC2 0.1U BC2 0.1U TC22 100U/6V TC22 100U/6V R10 47K R10 47K R9 47K R9 47K R6 4.7K R6 4.7K R2 2K R2 2K R5 4.7K R5 4.7K BC1 0.1U BC1 0.1U R3 2K R3 2K BCLK7 H P V D D 1 2 XTO2 DCVDD3 MBIAS 21 M I C I N 2 2 R L I N E I N 2 3 L L I N E I N 2 4 M O D E 2 5 C S B 2 6 S D I N 2 7 S C L K 2 8 ROUT 17 AVDD 18 AGND 19 VMID 20 LOUT 16 HPGND 15 R H P O U T 1 4 L H P O U T 1 3 XTI/MCLK1 DGND4 A D C L R C K 1 1 A D C D A T 1 0 DBVDD5 CLKOUT6 D A C D A T 8 D A C L R C K 9 U1 WM8731 U1 WM8731 R4 4.7KR4 4.7K L 1 R 2 G N D 3 N C R 4 N C L 5 J3 LINEOUTJ3 LINEOUT R1 4.7KR1 4.7K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A VGA_G0 VGA_G2 G VGA_G3 VGA_B2 VGA_B3 VGA_B0 B VGA_R3 VGA_R2 VGA_VSYNC VGA_HSYNCH V VGA_R0 VGA_R1 VGA_G1 VGA_B1 R VGA_G[0..3] VGA_B[0..3] VGA_HSYNC VGA_R[0..3] VGA_VSYNC Title Size Document Number Rev Date: Sheet of VGA 1.1A Altera Cyclone II Starter Board A 5 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of VGA 1.1A Altera Cyclone II Starter Board A 5 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of VGA 1.1A Altera Cyclone II Starter Board A 5 21Tuesday, October 03, 2006 R G B RG BG GG GND GND HS VS R14 120R14 120 R13 120R13 120 1 2 3 45 6 7 8 RN3 2K RN3 2K 1 2 3 4 5 6 7 8 RN2 1K RN2 1K 1 2 3 45 6 7 8 RN1 2K RN1 2K 5 9 4 8 3 7 2 6 1 1 7 1 6 10 11 12 13 14 15 10 11 6 1 515 J4 VGA 10 11 6 1 515 J4 VGA 1 2 3 45 6 7 8 RN5 2K RN5 2K 1 2 3 4 5 6 7 8 RN4 1K RN4 1K 1 2 3 4 5 6 7 8 RN6 1K RN6 1K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A E2 D2 A2 G2 F2 C2 B2 C1 F1 G1 A1 D1 B1 E1 D3 E3 G3 C3 B3 F3 A3 A0 B0 C0 D0 E0 F0 G0 HEX0_D3 HEX0_D2 HEX0_D1 HEX0_D0 HEX0_D4 HEX0_D6 HEX0_D5 HEX1_D0 HEX1_D1 HEX1_D3 HEX1_D2 HEX1_D4 HEX1_D5 HEX1_D6 HEX2_D0 HEX2_D1 HEX2_D2 HEX2_D3 HEX2_D4 HEX2_D5 HEX2_D6 HEX3_D0 HEX3_D2 HEX3_D1 HEX3_D3 HEX3_D5 HEX3_D4 HEX3_D6 A0 B0 C0 D0 E0 F0 G0 A1 B1 C1 D1 E1 F1 G1 A2 B2 C2 D2 E2 F2 G2 A3 B3 C3 D3 E3 F3 G3 HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] HEX0_D[0..6] VCC33 VCC33 VCC33 VCC33 Title Size Document Number Rev Date: Sheet of 7 SEGMENT 1.1A Altera Cyclone II Starter Board A 6 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of 7 SEGMENT 1.1A Altera Cyclone II Starter Board A 6 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of 7 SEGMENT 1.1A Altera Cyclone II Starter Board A 6 21Tuesday, October 03, 2006 1 2 3 4 5 6 7 8 RN8 1KRN8 1K 1 2 3 4 5 6 7 8 RN11 1KRN11 1K 10 9 8 5 4 2 3 7 1 6 A B C D E F G DP HEX2 7Segment Display A B C D E F G DP HEX2 7Segment Display 10 9 8 5 4 2 3 7 1 6 A B C D E F G DP HEX3 7Segment Display A B C D E F G DP HEX3 7Segment Display 1 2 3 4 5 6 7 8 RN12 1KRN12 1K 1 2 3 4 5 6 7 8 RN9 1KRN9 1K 10 9 8 5 4 2 3 7 1 6 A B C D E F G DP HEX1 7Segment Display A B C D E F G DP HEX1 7Segment Display 1 2 3 4 5 6 7 8 RN13 1KRN13 1K 10 9 8 5 4 2 3 7 1 6 A B C D E F G DP HEX0 7Segment Display A B C D E F G DP HEX0 7Segment Display 1 2 3 4 5 6 7 8 RN10 1KRN10 1K 1 2 3 4 5 6 7 8 RN7 1KRN7 1K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A LED8 LED7 LED6 LED4 LED5 LED9 LED0 LED1 LED2 LED3 LED17 LED11 LED12 LED10 LED13 LED14 LED15 LED16 LED[0..17] Title Size Document Number Rev Date: Sheet of LED 1.1A Altera Cyclone II Starter Board A 7 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of LED 1.1A Altera Cyclone II Starter Board A 7 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of LED 1.1A Altera Cyclone II Starter Board A 7 21Tuesday, October 03, 2006 LEDR7 LEDRLEDR7 LEDR LEDR5 LEDRLEDR5 LEDR LEDR9 LEDRLEDR9 LEDR LEDR8 LEDRLEDR8 LEDR 1 2 3 4 5 6 7 8 RN18 330 RN18 330 LEDG0 LEDGLEDG0 LEDG LEDG3 LEDGLEDG3 LEDG 1 2 3 4 5 6 7 8 RN19 330 RN19 330 LEDG2 LEDGLEDG2 LEDG LEDR0 LEDRLEDR0 LEDR 1 2 3 4 5 6 7 8 RN15 330 RN15 330 LEDG5 LEDGLEDG5 LEDG LEDR2 LEDRLEDR2 LEDR LEDG4 LEDGLEDG4 LEDG LEDR1 LEDRLEDR1 LEDR LEDG7 LEDGLEDG7 LEDG LEDR4 LEDRLEDR4 LEDR 1 2 3 4 5 6 7 8 RN16 330 RN16 330 LEDG6 LEDGLEDG6 LEDG LEDR3 LEDRLEDR3 LEDR LEDG1 LEDGLEDG1 LEDG LEDR6 LEDRLEDR6 LEDR 1 2 3 4 5 6 7 8 RN17 330 RN17 330 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SW8 SW7 DRAM_A0 DRAM_A1 DRAM_A2 DRAM_A4 DRAM_A5 DRAM_A6 DRAM_A7 DRAM_A8DRAM_A9 DRAM_A10 DRAM_A11 DRAM_A3 DRAM_D0 DRAM_D1 DRAM_D2 DRAM_D3 DRAM_D4 DRAM_D5 DRAM_D6 DRAM_D7 DRAM_D8 DRAM_D9 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 SW9 HEX0_D0 HEX1_D0 HEX1_D1 HEX1_D2 HEX1_D3 HEX1_D4 HEX1_D5 HEX1_D6 HEX2_D0 HEX3_D0 HEX0_D1 HEX0_D2 HEX0_D3 HEX0_D4 HEX0_D5 HEX0_D6 HEX2_D1 HEX2_D2 HEX2_D3 HEX2_D6 HEX3_D1 HEX3_D2 HEX3_D3 HEX3_D4 HEX3_D5HEX3_D6 HEX2_D5 HEX2_D4 SW[7..9] DRAM_D[0..15] DRAM_A[0..11] DRAM_UDQM DRAM_LDQM DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] 50MHZ Title Size Document Number Rev Date: Sheet of EP2C20 BANK1 AND BANK 2 1.1A Altera Cyclone II Starter Board A 8 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C20 BANK1 AND BANK 2 1.1A Altera Cyclone II Starter Board A 8 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C20 BANK1 AND BANK 2 1.1A Altera Cyclone II Starter Board A 8 21Tuesday, October 03, 2006 CLK2/LVDSCLK1p M1 CLK3/LVDSCLK1n M2 LVDS0nY4 LVDS0pY3 LVDS1nW4 LVDS1pW3 LVDS2nY2 LVDS2pY1 LVDS3nW2 LVDS3pW1 LVDS4nT6 LVDS4pT5 LVDS5nV2 LVDS6nR6 LVDS6pR5 LVDS7nU2 LVDS7pU1 LVDS8nT2 LVDS8pT1 LVDS9nR2 LVDS9pR1 LVDS10nP6 LVDS10pP5 LVDS11nR7 LVDS11pR8 LVDS12pN3 LVDS12nN4 LVDS13nP2 LVDS13pP1 LVDS14nN2 LVDS14pN1 LVDS15nM6 LVDS15pM5 VREFB1N1 U3 VREFB1N0 P3 PLL1_OUTp U4 PLL1_OUTn V4 IO1_2 W5 IO1_1 T3 IO1_0 N6 LVDS5pV1 BANK1 U2A CYCLONE II EP2C20 BANK1 U2A CYCLONE II EP2C20 CLK0/LVDSCLK0p L1 CLK1/LVDSCLK0n L2 LVDS16pJ1 LVDS16nJ2 LVDS17nH2 LVDS17pH1 LVDS18nF2 LVDS18pF1 LVDS19nE2 LVDS19pE1 LVDS20nH6 LVDS20pH5 LVDS21nH4 LVDS21pG3 LVDS22nD2 LVDS22pD1 LVDS23nG5 LVDS23pG6 LVDS24nC2 LVDS24pC1 LVDS25nE4 LVDS25pE3 LVDS26nD4 LVDS26pD3 IO2_0 F3 IO2_1 J4 IO2_2 L8 PLL3_OUTn D6 PLL3_OUTp D5 VREFB2N0 F4 VREFB2N1 H3 BANK2 U2B CYCLONE II EP2C20 BANK2 U2B CYCLONE II EP2C20 5 5 4 4 3 3 2 2 1 1 D D C C B B A A VGA_R0 VGA_R1 VGA_R2 VGA_R3 VGA_G0 VGA_G1VGA_G2 VGA_G3 VGA_B0 VGA_B1 VGA_B2 VGA_B3 GPIO_B49 GPIO_B48 GPIO_B47 GPIO_B46 GPIO_B45 GPIO_B44 GPIO_B43 GPIO_B42 GPIO_B41 GPIO_B40 GPIO_B39 GPIO_B38 GPIO_B13 GPIO_B11 GPIO_B10 GPIO_B9 GPIO_B8 GPIO_B7 GPIO_B6 GPIO_B5 GPIO_B4 GPIO_B3 GPIO_B2 GPIO_B0 GPIO_B12 GPIO_B1 GPIO_B36 GPIO_B15 GPIO_B14 GPIO_B51 GPIO_B50 GPIO_B37 VGA_B[0..3] VGA_R[0..3] VGA_G[0..3] AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_ADCLRCK AUD_ADCDAT I2C_SDAT I2C_SCLK UART_RXD UART_TXD PS2_CLK PS2_DAT LINK_D3 LINK_D0 LINK_D1 LINK_D2 24MHZ GPIO_B[36..51] 27MHZ VGA_HSYNC VGA_VSYNC GPIO_B[0..15] Title Size Document Number Rev Date: Sheet of EP2C35 BANK3 AND BANK 4 1.1A Altera Cyclone II Starter Board A 9 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C35 BANK3 AND BANK 4 1.1A Altera Cyclone II Starter Board A 9 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C35 BANK3 AND BANK 4 1.1A Altera Cyclone II Starter Board A 9 21Tuesday, October 03, 2006 CLK10/LVDSCLK5n D12 CLK11/LVDSCLK5p E12 LVDS27pA3 LVDS28nB4 LVDS28pA4 LVDS29nB5 LVDS29pA5 LVDS30nB6 LVDS30pA6 LVDS31nG7 LVDS31pH7 LVDS32nF8 LVDS32pG8 LVDS33nD8 LVDS33pC9 LVDS34nF9 LVDS34pE8 LVDS35nB7 LVDS35pA7 LVDS36nB8 LVDS36pA8 LVDS37nE9 LVDS37pD9 LVDS38nH10 LVDS38pH9 LVDS39nB9 LVDS39pA9 LVDS40nF11 LVDS40pF10 LVDS41nB10 LVDS41pA10 LVDS42n H11 LVDS42p G11 LVDS43n E11 LVDS43p D11 LVDS44n B11 LVDS44p A11 IO3_0 D7 IO3_1 E7 IO3_2 H8 VREFB3N0 C10 VREFB3N1 C7 LVDS27n/DEV_CLRnB3 BANK3 U2C CYCLONE II EP2C20 BANK3 U2C CYCLONE II EP2C20 CLK8/LVDSCLK4n B12 CLK9/LVDSCLK4p A12 LVDS45nB13 LVDS45pA13 LVDS49pA16 LVDS46nB14 LVDS46pA14 LVDS47nF12 LVDS47pG12 LVDS48nB15 LVDS48pA15 LVDS50nF14 LVDS49nB16 LVDS50pF13 LVDS52nB17 LVDS51nE14 LVDS51pD14 LVDS52pA17 LVDS53nG15 LVDS53pF15 LVDS54nD15 LVDS54pC14 LVDS55nH14 LVDS55pJ14 LVDS56nD16 LVDS56pE15 LVDS57nG16 LVDS57pH15 LVDS58nB18 LVDS58pA18 LVDS59nB19 LVDS59pA19 LVDS60n B20 LVDS60p A20 LVDS61n C18 LVDS61p C17 IO4_0 H12 IO4_1 H13 VREFB4N0 C16 VREFB4N1 C13 BANK4 U2D CYCLONE II EP2C20 BANK4 U2D CYCLONE II EP2C20 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SW0 SW1 GPIO_B16 GPIO_B17 GPIO_B18 GPIO_B19 GPIO_B20 GPIO_B21 GPIO_B22 GPIO_B23 GPIO_B24 GPIO_B25 GPIO_B27 GPIO_B28 GPIO_B29 GPIO_B30 GPIO_B31 GPIO_B35 GPIO_B52 GPIO_B32 GPIO_B26 KEY0 KEY1 KEY3 LED0 KEY2 GPIO_B53 GPIO_B54 GPIO_B55 GPIO_B56 GPIO_B57 GPIO_B59 GPIO_B60 GPIO_B61 GPIO_B62 GPIO_B63 GPIO_B64 GPIO_B65 GPIO_B66 GPIO_B67 GPIO_B68 GPIO_B69 GPIO_B70 GPIO_B71 SW2 GPIO_B34 GPIO_B33 GPIO_B58 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 KEY[0..3] EXT_CLOCK LED[0..17] SW[0..2] SD_DAT SD_CLK SD_CMD SD_DAT3 GPIO_B[16..35] GPIO_B[52..71] Title Size Document Number Rev Date: Sheet of EP2C20 BANK5 AND BANK 6 1.1A Altera Cyclone II Starter Board A 10 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C20 BANK5 AND BANK 6 1.1A Altera Cyclone II Starter Board A 10 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C20 BANK5 AND BANK 6 1.1A Altera Cyclone II Starter Board A 10 21Tuesday, October 03, 2006 CLK4/LVDSCLK2p L22 CLK5/LVDSCLK2n L21 LVDS62nD19 LVDS62pD20 LVDS63nC19 LVDS63pC20 LVDS64nC21 LVDS64pC22 LVDS65nE20 LVDS65pF20 LVDS66nG17 LVDS66pG18 LVDS67nD21 LVDS67pD22 LVDS68nE21 LVDS68pE22 LVDS70nF21 LVDS70pF22 LVDS71nG21 LVDS71pG22 LVDS72nJ17 LVDS72pH16 LVDS73nJ19 LVDS73pJ18 LVDS74nJ20 LVDS74pH19 LVDS75nJ21 LVDS75pJ22 LVDS76nK21 LVDS76pK22 LVDS77n L19 LVDS77p L18 IO5_0 J15 PLL2_OUTn E18 PLL2_OUTp E19 VREFB5N0 G20 VREFB5N1 K20 LVDS69nH18 LVDS69pH17 BANK5 U2E CYCLONE II EP2C20 BANK5 U2E CYCLONE II EP2C20 CLK6/LVDSCLK3p M22 CLK7/LVDSCLK3n M21 LVDS78nM19 LVDS78pM18 LVDS79nN21 LVDS79pN22 LVDS80nP15 LVDS80pN15 LVDS81nR21 LVDS81pR22 LVDS82nT21 LVDS82pT22 LVDS84nR18 LVDS84pR19 LVDS85nU21 LVDS85pU22 LVDS86nV21 LVDS86pV22 LVDS87nY21 LVDS87pY22 LVDS88nW21 LVDS88pW22 LVDS89nU19 LVDS89pV20 LVDS90nY19 LVDS90pY20 LVDS91n/INIT_DONEV19 LVDS91p/nCEOW20 IO6_0 R17 IO6_1 Y18 PLL4_OUTn U18 PLL4_OUTp T18 VREFB6N0 R20 VREFB6N1 U20 LVDS83nP17 LVDS83pP18 BANK6 U2F CYCLONE II EP2C20 BANK6 U2F CYCLONE II EP2C20 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SW3 SW4 FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_D0 SW5 SW6 SRAM_A0 SRAM_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D4 SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_A5 SRAM_A6 SRAM_A7 SRAM_A8 SRAM_A9 SRAM_A10 SRAM_A11 SRAM_A12 SRAM_A13 SRAM_A14 SRAM_A15 SRAM_A16 SRAM_A17 SRAM_D1 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_D8 SRAM_D9 SRAM_D10 SRAM_D11 SRAM_D12 SRAM_D13 SRAM_D14 SRAM_D15 SW[3..6] SRAM_D[0..15] FLASH_CE FLASH_A[0..21] FLASH_OE FLASH_RESET FLASH_WE SRAM_CE SRAM_WE SRAM_A[0..17] SRAM_OE SRAM_UB SRAM_LB FLASH_D[0..7] Title Size Document Number Rev Date: Sheet of EP2C20 BANK7 AND BANK 8 1.1A Altera Cyclone II Starter Board A 11 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C20 BANK7 AND BANK 8 1.1A Altera Cyclone II Starter Board A 11 21Tuesday, October 03, 2006 Title Size Document Number Rev Date: Sheet of EP2C20 BANK7 AND BANK 8 1.1A Altera Cyclone II Starter Board A 11 21Tuesday, October 03, 2006 CLK12/LVDSCLK6n V12 CLK13/LVDSCLK6p W12 LVDS100nT15 LVDS100pU14 LVDS101nAA17 LVDS101pAB17 LVDS102nV14 LVDS102pW14 LVDS103nAA16 LVDS103pAB16 LVDS104nAA15 LVDS104pAB15 LVDS105nAA14 LVDS105pAB14 LVDS106nU13 LVDS106pT12 LVDS107n AA13 LVDS107p AB13 LVDS108n AA12 LVDS108p AB12 LVDS92nAA20 LVDS92pAB20 LVDS93nAA19 LVDS93pAB19 LVDS94nW16 LVDS94pY17 LVDS95nV15 LVDS95pU15 LVDS96nT16 LVDS96pR16 LVDS97nAA18 LVDS97pAB18 LVDS98nR15 LVDS98pR14 LVDS99nW15 LVDS99pY14 IO7_0 R12 IO7_1 R13 VREFB7N0 Y16 VREFB7N1 Y13 BANK7 CYCLONE II EP2C20 U2G BANK7 CYCLONE II EP2C20 U2G CLK14/LVDSCLK7n U12 CLK15/LVDSCLK7p U11 LVDS109nAA11 LVDS109pAB11 LVDS110nAA10 LVDS110pAB10 LVDS111nV11 LVDS111pW11 LVDS112nR11 LVDS112pT11 LVDS113nAA9 LVDS113pAB9 LVDS114nAA8 LVDS114pAB8 LVDS115nR9 LVDS115pR10 LVDS116nU10 LVDS116pU9 LVDS117nW9 LVDS117pY9 LVDS118nAA7 LVDS118pAB7 LVDS119nV9 LVDS119pW8 LVDS120nW7 LVDS120pV8 LVDS121nAA6 LVDS121pAB6 LVDS122nP8 LVDS122pP9 LVDS123nT7 LVDS123pT8 LVDS124n AA5 LVDS124p AB5 LVDS125n Y6 LVDS125p Y5 LVDS126n AA4 LVDS126p AB4 LVDS127n AA3 LVDS127p AB3 IO8_0 U8 VREFB8N0 Y10 VREFB8N1 Y7 BANK8 CYCLONE II EP2C20 U2H BANK8 CYCLONE II EP2C20 U2H 5 5 4