xtp067_sp605_schematics

ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By Disclaimer: THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Linear Regulator 1.8V@500mA max Jack Power Supply12V Linear Regulator 5.0V@1.5A max 1.5V@20A max 3.3V@20A max Sink/Source DDR Regulator Power Controller 1 PWR Switching Module Switching Module Switching Module FMC LPC TDO U1 FPGA TDITSTTDI CFGTDO CFGTDITSTTDO JTAG Chain TDO System ACE CF 3.3V 2.5V U1 SCHEM, ROHS COMPLIANT FMC LPC Expansion Connector GMII Differential Clock Clock Socket SMA Clock LEDs DIP Switches MODE DIP Switch Push Buttons USB UART SSPI Header EEPROM: External Config Other Devices: Parallel Flash USB JTAG ConnectorIIC EEPROM and Header SPI X4 or 0b1010010 0bXXXXX10 Spartan-6 XC6SLX45T PCB P/N: 0431534 SCH P/N: 0381305 ART P/N: 1280473 Test P/N: TSS0123 DDR3 TDIBUFFER PCIe Finger SP605 Block Diagram 10/100/1000 Ethernet U4 J2 Page 9 Page 10 Page 11 Page 14 Page 14 Page 14 Page 14 Page 15 Page 18 Page 15 Page 32 Page 12 Page 18 Page 18 Page 19 U SB H DR J4 J2 J19 U17 VCCINT@10A max Power Controller 2 0b1010100 Linear Regulator 1.2V @ 3A max VCCAUX@10A max Switching Module 2.5V@10A max Switching Module Linear Regulator 3.0V@500mA max System ACE CF Page 20 0.75V VTT / VREF @ 3A max SFP Module Page 12 SP605 EVALUATION PLATFORM IIC Addressing BF 04 1 35 9-25-2009_10:32 D VCC2V5_FPGA ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By IO_L1P_HSWAPEN_0_C3 IO_L1N_VREF_0_D3 IO_L2P_0_D4 IO_L2N_0_D5 IO_L3P_0_B2 IO_L3N_0_A2 IO_L4P_0_E5 IO_L4N_0_E6 IO_L5P_0_B3 IO_L5N_0_A3 IO_L6P_0_C4 IO_L6N_0_A4 IO_L7P_0_F7 IO_L7N_0_F8 IO_L8P_0_C5 IO_L8N_VREF_0_A5 IO_L32P_0_G8 IO_L32N_0_F9 IO_L33P_0_H10 IO_L33N_0_H11 IO_L34P_GCLK19_0_G9 IO_L34N_GCLK18_0_F10 IO_L35P_GCLK17_0_H12 IO_L35N_GCLK16_0_G11 IO_L36P_GCLK15_0_F14 IO_L36N_GCLK14_0_F15 IO_L37P_GCLK13_0_E16 IO_L37N_GCLK12_0_F16 IO_L38P_0_H13 IO_L38N_VREF_0_G13 IO_L49P_0_H14 IO_L49N_0_G15 IO_L50P_0_C17 IO_L50N_0_A17 IO_L51P_0_G16 IO_L51N_0_F17 IO_L62P_0_D18 IO_L62N_VREF_0_D19 IO_L63P_SCP7_0_B18 IO_L63N_SCP6_0_A18 IO_L64P_SCP5_0_C19 IO_L64N_SCP4_0_A19 IO_L65P_SCP3_0_B20 IO_L65N_SCP2_0_A20 IO_L66P_SCP1_0_D17 IO_L66N_SCP0_0_C18 VCCO_0_B19 VCCO_0_B4 VCCO_0_E17 VCCO_0_F6 VCCO_0_G10 VCCO_0_G14 6slx45tfg484 BANK 0 DUT PCB P/N: 0431534 SCH P/N: 0381305 ART P/N: 1280473 Test P/N: TSS0123 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM FPGA Bank 0 FPGA Bank 0 D 2 35 9-18-2009_15:04 04 BF C3 D3 D4 D5 B2 A2 E5 E6 B3 A3 C4 A4 F7 F8 C5 A5 G8 F9 H10 H11 G9 F10 H12 G11 F14 F15 E16 F16 H13 G13 H14 G15 C17 A17 G16 F17 D18 D19 B18 A18 C19 A19 B20 A20 D17 C18 B19 B4 E17 F6 G10 G14 U1 10FMC_LA07_N 10FMC_LA07_P 10FMC_LA05_P 10FMC_LA05_N FMC_LA02_P 10 10FMC_LA02_N FMC_LA10_P 10 FMC_LA10_N 10 10FMC_LA12_P 10FMC_LA12_N FMC_LA11_P 10 10FMC_LA11_N FMC_LA16_P 10 FMC_LA16_N 10 10FMC_LA13_P 10FMC_LA13_N 10FMC_LA15_P 10FMC_LA15_N FMC_LA14_P 10 FMC_LA14_N 10 10FMC_LA03_P 10FMC_LA03_N 10FMC_LA04_N 10FMC_LA04_P FMC_CLK1_M2C_P 10 FMC_CLK1_M2C_N 10 1 2 R125 100 1/16W 5% USER_SMA_GPIO_P 13 USER_SMA_GPIO_N 13 14GPIO_SWITCH_0 14GPIO_LED_0 FMC_LA01_CC_P 10 FMC_LA01_CC_N 10 21,26PMBUS_ALERT FPGA_HSWAPEN 10FMC_LA00_CC_N 10FMC_LA00_CC_P FMC_CLK0_M2C_P 10 FMC_CLK0_M2C_N 10 IIC_SCL_SFP 12 IIC_SDA_SFP 12 10FMC_LA08_P 10FMC_LA08_N FMC_LA09_P 10 FMC_LA09_N 10 FMC_LA06_P 10 FMC_LA06_N 10 VCC2V5_FPGA ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By IO_L1P_A25_1_F18 IO_L1N_A24_VREF_1_F19 IO_L9P_1_H16 IO_L9N_1_H17 IO_L10P_1_B21 IO_L10N_1_B22 IO_L19P_1_J16 IO_L19N_1_J17 IO_L20P_1_C20 IO_L20N_1_C22 IO_L21P_1_L15 IO_L21N_1_K16 IO_L28P_1_D21 IO_L28N_VREF_1_D22 IO_L29P_A23_M1A13_1_G19 IO_L29N_A22_M1A14_1_F20 IO_L30P_A21_M1RESET_1_H18 IO_L30N_A20_M1A11_1_H19 IO_L31P_A19_M1CKE_1_F21 IO_L31N_A18_M1A12_1_F22 IO_L32P_A17_M1A8_1_E20 IO_L32N_A16_M1A9_1_E22 IO_L33P_A15_M1A10_1_J19 IO_L33N_A14_M1A4_1_H20 IO_L34P_A13_M1WE_1_K19 IO_L34N_A12_M1BA2_1_K18 IO_L35P_A11_M1A7_1_G20 IO_L35N_A10_M1A2_1_G22 IO_L36P_A9_M1BA0_1_K17 IO_L36N_A8_M1BA1_1_L17 IO_L37P_A7_M1A0_1_H21 IO_L37N_A6_M1A1_1_H22 IO_L38P_A5_M1CLK_1_K20 IO_L38N_A4_M1CLKN_1_L19 IO_L39P_M1A3_1_J20 IO_L39N_M1ODT_1_J22 IO_L40P_GCLK11_M1A5_1_M20 IO_L40N_GCLK10_M1A6_1_M19 IO_L41P_GCLK9_M1RASN_1_K21 IO_L41N_GCLK8_M1CASN_1_K22 IO_L42P_GCLK7_M1UDM_1_P20 IO_L42N_GCLK6_M1LDM_1_N19 IO_L43P_GCLK5_M1DQ4_1_L20 IO_L43N_GCLK4_M1DQ5_1_L22 IO_L44P_A3_M1DQ6_1_M21 IO_L44N_A2_M1DQ7_1_M22 IO_L45P_A1_M1LDQS_1_N20 IO_L45N_A0_M1LDQSN_1_N22 IO_L46P_FCS_B_M1DQ2_1_P21 IO_L46N_FOE_B_M1DQ3_1_P22 IO_L47P_FWE_B_M1DQ0_1_R20 IO_L47N_LDC_M1DQ1_1_R22 IO_L48P_HDC_M1DQ8_1_T21 IO_L48N_M1DQ9_1_T22 IO_L49P_M1DQ10_1_U20 IO_L49N_M1DQ11_1_U22 IO_L50P_M1UDQS_1_V21 IO_L50N_M1UDQSN_1_V22 IO_L51P_M1DQ12_1_W20 IO_L51N_M1DQ13_1_W22 IO_L52P_M1DQ14_1_Y21 IO_L52N_M1DQ15_1_Y22 IO_L53P_1_P19 IO_L53N_VREF_1_R19 IO_L58P_1_M16 IO_L58N_1_N15 IO_L59P_1_U19 IO_L59N_1_T20 IO_L60P_1_N16 IO_L60N_1_P16 IO_L61P_1_M17 IO_L61N_1_M18 IO_L70P_1_R15 IO_L70N_1_R16 IO_L71P_1_P17 IO_L71N_1_P18 IO_L72P_1_R17 IO_L72N_1_T17 IO_L73P_1_T19 IO_L73N_1_T18 IO_L74P_AWAKE_1_V19 IO_L74N_DOUT_BUSY_1_V20 VCCO_1_C21 VCCO_1_E19 VCCO_1_G21 VCCO_1_J18 VCCO_1_L16 VCCO_1_L21 VCCO_1_N18 VCCO_1_R21 VCCO_1_U18 VCCO_1_W21 6slx45tfg484 BANK 1 DUT Test P/N: TSS0123 ART P/N: 1280473 SCH P/N: 0381305 PCB P/N: 0431534 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM FPGA Bank 1 FPGA Bank 1 04 BF 9-18-2009_15:04 353 D NC CLK_33MHZ_SYSACE 20 F18 F19 H16 H17 B21 B22 J16 J17 C20 C22 L15 K16 D21 D22 G19 F20 H18 H19 F21 F22 E20 E22 J19 H20 K19 K18 G20 G22 K17 L17 H21 H22 K20 L19 J20 J22 M20 M19 K21 K22 P20 N19 L20 L22 M21 M22 N20 N22 P21 P22 R20 R22 T21 T22 U20 U22 V21 V22 W20 W22 Y21 Y22 P19 R19 M16 N15 U19 T20 N16 P16 M17 M18 R15 R16 P17 P18 R17 T17 T19 T18 V19 V20 C21 E19 G21 J18 L16 L21 N18 R21 U18 W21 U1 SFP_LOS 12 PHY_RESET 11 USER_SMA_CLOCK_N 13 USER_SMA_CLOCK_P 13 SYSCLK_P 14 SYSCLK_N 14 PHY_RXCLK 11 14GPIO_LED_2 FLASH_ADV_B 19 FLASH_WAIT 19 DVI_D1 17 11PHY_CRS DVI_D2 17 DVI_D11 17 17DVI_D10 PHY_MDIO 11 17DVI_D6 DVI_D4 17 DVI_H 17 DVI_D0 17 17DVI_XCLK_P 17DVI_RESET_B 21,26PMBUS_CTRL DVI_D7 17 DVI_D8 17 DVI_D3 17 DVI_D5 17 DVI_D9 17 DVI_V 17 DVI_DE 17 17DVI_XCLK_N DVI_GPIO1 17 FLASH_A23 19 FLASH_A22 19 FLASH_A21 19 FLASH_A20 19 FLASH_A19 19 FLASH_A14 19 FLASH_A10 19 FLASH_A9 19 FLASH_A8 19 FLASH_A7 19 FLASH_A6 19 FLASH_A5 19 FLASH_A4 19 PHY_INT 11 FLASH_A3 19 FLASH_A2 19 FLASH_A1 19 FLASH_A0 19 FLASH_CE_B 19 11PHY_COL 18FPGA_AWAKE PHY_MDC 11 PHY_RXD0 11 PHY_RXD1 11 PHY_RXD2 11 PHY_RXD3 11 PHY_RXD4 11 PHY_RXD5 11 PHY_RXD6 11 PHY_RXD7 11 PHY_RXER 11 11PHY_RXCTL_RXDV FLASH_WE_B 19 FLASH_OE_B 19 FLASH_A11 19 FLASH_A12 19 FLASH_A13 19 FLASH_A15 19 FLASH_A16 19 FLASH_A17 19 FLASH_A18 19 15USB_1_TX 15USB_1_RX IIC_SDA_MAIN 10,15 IIC_SCL_MAIN 10,15 USB_1_CTS 15 USB_1_RTS 15 PHY_TXCLK 11 VCC2V5 VCC2V5_FPGA ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By IO_L1P_CCLK_2_Y20 IO_L1N_M0_CMPMISO_2_AA21 IO_L2P_CMPCLK_2_V17 IO_L2N_CMPMOSI_2_W18 IO_L3P_D0_DIN_MISO1_2_AA20 IO_L3N_MOSI_CSI_B_MISO0_2_AB20 IO_L4P_2_U16 IO_L4N_VREF_2_V15 IO_L5P_2_W17 IO_L5N_2_Y18 IO_L6P_2_AA14 IO_L6N_2_AB14 IO_L12P_D1_MISO2_2_R13 IO_L12N_D2_MISO3_2_T14 IO_L13P_M1_2_Y19 IO_L13N_D10_2_AB19 IO_L14P_D11_2_AA18 IO_L14N_D12_2_AB18 IO_L15P_2_Y17 IO_L15N_2_AB17 IO_L16P_2_U14 IO_L16N_VREF_2_U13 IO_L17P_2_Y16 IO_L17N_2_W15 IO_L18P_2_V13 IO_L18N_2_W13 IO_L19P_2_AA16 IO_L19N_2_AB16 IO_L20P_2_W14 IO_L20N_2_Y14 IO_L21P_2_Y15 IO_L21N_2_AB15 IO_L22P_2_R11 IO_L22N_2_T11 IO_L23P_2_T15 IO_L23N_2_U15 IO_L29P_GCLK3_2_T12 IO_L29N_GCLK2_2_U12 IO_L30P_GCLK1_D13_2_Y13 IO_L30N_GCLK0_USERCCLK_2_AB13 IO_L31P_GCLK31_D14_2_AA12 IO_L31N_GCLK30_D15_2_AB12 IO_L32P_GCLK29_2_Y11 IO_L32N_GCLK28_2_AB11 IO_L40P_2_W12 IO_L40N_2_Y12 IO_L41P_2_AA10 IO_L41N_VREF_2_AB10 IO_L42P_2_V11 IO_L42N_2_W11 IO_L43P_2_Y9 IO_L43N_2_AB9 IO_L44P_2_W10 IO_L44N_2_Y10 IO_L45P_2_AA8 IO_L45N_2_AB8 IO_L46P_2_T10 IO_L46N_2_U10 IO_L47P_2_Y7 IO_L47N_2_AB7 IO_L48P_D7_2_W9 IO_L48N_RDWR_B_VREF_2_Y8 IO_L49P_D3_2_AA6 IO_L49N_D4_2_AB6 IO_L50P_2_U9 IO_L50N_2_V9 IO_L57P_2_T8 IO_L57N_2_U8 IO_L58P_2_V7 IO_L58N_2_W8 IO_L59P_2_R9 IO_L59N_2_R8 IO_L60P_2_W6 IO_L60N_2_Y6 IO_L62P_D5_2_Y5 IO_L62N_D6_2_AB5 IO_L63P_2_AA4 IO_L63N_2_AB4 IO_L64P_D8_2_T7 IO_L64N_D9_2_U6 IO_L65P_INIT_B_2_Y4 IO_L65N_CSO_B_2_AA3 VCCO_2_AA11 VCCO_2_AA15 VCCO_2_AA19 VCCO_2_AA7 VCCO_2_AB3 VCCO_2_T13 VCCO_2_T9 VCCO_2_V12 VCCO_2_V16 VCCO_2_V8 VCCO_2_W5 6slx45tfg484 BANK 2 DUT PCB P/N: 0431534 SCH P/N: 0381305 ART P/N: 1280473 Test P/N: TSS0123 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM FPGA Bank 2 FPGA Bank 2 BF D 4 35 9-18-2009_15:04 04 PHY_TXC_GTXCLK 11 Y20 AA21 V17 W18 AA20 AB20 U16 V15 W17 Y18 AA14 AB14 R13 T14 Y19 AB19 AA18 AB18 Y17 AB17 U14 U13 Y16 W15 V13 W13 AA16 AB16 W14 Y14 Y15 AB15 R11 T11 T15 U15 T12 U12 Y13 AB13 AA12 AB12 Y11 AB11 W12 Y12 AA10 AB10 V11 W11 Y9 AB9 W10 Y10 AA8 AB8 T10 U10 Y7 AB7 W9 Y8 AA6 AB6 U9 V9 T8 U8 V7 W8 R9 R8 W6 Y6 Y5 AB5 AA4 AB4 T7 U6 Y4 AA3 AA11 AA15 AA19 AA7 AB3 T13 T9 V12 V16 V8 W5 U1 FPGA_CMP_MOSI 18 FPGA_CMP_CLK 18 FMC_LA30_P 10 FMC_LA30_N 10 10FMC_LA25_P 10FMC_LA25_N 10FMC_LA29_P 10FMC_LA29_N FMC_LA28_P 10 FMC_LA28_N 10 10FMC_LA33_N 10FMC_LA33_P FMC_LA32_N 10 FMC_LA32_P 10 10FMC_LA27_P 10FMC_LA27_N FMC_LA21_P 10 FMC_LA21_N 10 FMC_LA22_P 10 FMC_LA22_N 10 10FMC_LA19_N 10FMC_LA19_P 10FMC_LA20_N 10FMC_LA20_P PMBUS_CLK 21,26 21,26PMBUS_DATA 2 1 C260 120PF 50V NPO 1 2 R285 140 1/16W 1% 1 2 R10 4.7K 1/16W 5% 19FLASH_D8 14GPIO_SWITCH_2 GPIO_LED_3 14 10FMC_LA17_CC_P 10FMC_LA17_CC_N 12SFP_TX_DISABLE_FPGA 16,17IIC_SCL_DVI USER_CLOCK 14 18,19FPGA_D0_DIN_MISO_MISO1 18,19FPGA_D1_MISO2 18,19FPGA_D2_MISO3 19FLASH_D10 19FLASH_D11 19FLASH_D12 19FLASH_D13 19FLASH_D15 19FLASH_D14 FLASH_D7 19 FLASH_D3 19 FLASH_D4 19 FLASH_D5 19 FLASH_D6 19 19FLASH_D9 PHY_TXCTL_TXEN 11 PHY_TXER 11 16,17IIC_SDA_DVI SPI_CS_B 18 FPGA_INIT_B 14,20 PHY_TXD0 11 PHY_TXD1 11 PHY_TXD2 11 PHY_TXD3 11 PHY_TXD4 11 PHY_TXD5 11 PHY_TXD6 11 11PHY_TXD7 7,10,19FMC_PWR_GOOD_FLASH_RST_B FPGA_M1 18 FPGA_MOSI_CSI_B_MISO0 18 18FPGA_M0_CMP_MISO FMC_PRSNT_M2C_L 10 18FPGA_CCLK 14GPIO_SWITCH_1 14GPIO_LED_1 10FMC_LA18_CC_P 10FMC_LA18_CC_N FMC_LA24_N 10 FMC_LA24_P 10 10FMC_LA26_P 10FMC_LA26_N 10FMC_LA31_P 10FMC_LA31_N 10FMC_LA23_P 10FMC_LA23_N NC VTTVREF VCC1V5_FPGA ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By IO_L1P_3_R7 IO_L1N_VREF_3_P8 IO_L2P_3_W4 IO_L2N_3_Y3 IO_L7P_3_T6 IO_L7N_3_T5 IO_L8P_3_V5 IO_L8N_3_V3 IO_L9P_3_P5 IO_L9N_3_P4 IO_L10P_3_AA2 IO_L10N_3_AA1 IO_L23P_3_N6 IO_L23N_3_N7 IO_L24P_3_U4 IO_L24N_3_T4 IO_L25P_3_P6 IO_L25N_3_P7 IO_L26P_3_T3 IO_L26N_3_R4 IO_L31P_3_M7 IO_L31N_VREF_3_M8 IO_L32P_M3DQ14_3_Y2 IO_L32N_M3DQ15_3_Y1 IO_L33P_M3DQ12_3_W3 IO_L33N_M3DQ13_3_W1 IO_L34P_M3UDQS_3_V2 IO_L34N_M3UDQSN_3_V1 IO_L35P_M3DQ10_3_U3 IO_L35N_M3DQ11_3_U1 IO_L36P_M3DQ8_3_T2 IO_L36N_M3DQ9_3_T1 IO_L37P_M3DQ0_3_R3 IO_L37N_M3DQ1_3_R1 IO_L38P_M3DQ2_3_P2 IO_L38N_M3DQ3_3_P1 IO_L39P_M3LDQS_3_N3 IO_L39N_M3LDQSN_3_N1 IO_L40P_M3DQ6_3_M2 IO_L40N_M3DQ7_3_M1 IO_L41P_GCLK27_M3DQ4_3_L3 IO_L41N_GCLK26_M3DQ5_3_L1 IO_L42P_GCLK25_M3UDM_3_P3 IO_L42N_GCLK24_M3LDM_3_N4 IO_L43P_GCLK23_M3RASN_3_M5 IO_L43N_GCLK22_M3CASN_3_M4 IO_L44P_GCLK21_M3A5_3_M3 IO_L44N_GCLK20_M3A6_3_L4 IO_L45P_M3A3_3_M6 IO_L45N_M3ODT_3_L6 IO_L46P_M3CLK_3_K4 IO_L46N_M3CLKN_3_K3 IO_L47P_M3A0_3_K2 IO_L47N_M3A1_3_K1 IO_L48P_M3BA0_3_J3 IO_L48N_M3BA1_3_J1 IO_L49P_M3A7_3_K6 IO_L49N_M3A2_3_K5 IO_L50P_M3WE_3_H2 IO_L50N_M3BA2_3_H1 IO_L51P_M3A10_3_J4 IO_L51N_M3A4_3_H3 IO_L52P_M3A8_3_G3 IO_L52N_M3A9_3_G1 IO_L53P_M3CKE_3_F2 IO_L53N_M3A12_3_F1 IO_L54P_M3RESET_3_E3 IO_L54N_M3A11_3_E1 IO_L55P_M3A13_3_J6 IO_L55N_M3A14_3_H5 IO_L57P_3_K7 IO_L57N_VREF_3_K8 IO_L58P_3_H4 IO_L58N_3_G4 IO_L59P_3_D2 IO_L59N_3_D1 IO_L60P_3_F3 IO_L60N_3_E4 IO_L80P_3_H6 IO_L80N_3_G7 IO_L81P_3_J7 IO_L81N_3_H8 IO_L82P_3_F5 IO_L82N_3_G6 IO_L83P_3_C1 IO_L83N_VREF_3_B1 VCCO_3_C2 VCCO_3_F4 VCCO_3_G2 VCCO_3_J5 VCCO_3_L2 VCCO_3_L7 VCCO_3_N5 VCCO_3_R2 VCCO_3_U5 VCCO_3_W2 6slx45tfg484 BANK 3 DUT Test P/N: TSS0123 ART P/N: 1280473 SCH P/N: 0381305 PCB P/N: 0431534 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM FPGA Bank 3 FPGA Bank 3 04 BF 9-18-2009_15:04 355 D 2 1 1% 1/16W DNP R124 R7 P8 W4 Y3 T6 T5 V5 V3 P5 P4 AA2 AA1 N6 N7 U4 T4 P6 P7 T3 R4 M7 M8 Y2 Y1 W3 W1 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1 N3 N1 M2 M1 L3 L1 P3 N4 M5 M4 M3 L4 M6 L6 K4 K3 K2 K1 J3 J1 K6 K5 H2 H1 J4 H3 G3 G1 F2 F1 E3 E1 J6 H5 K7 K8 H4 G4 D2 D1 F3 E4 H6 G7 J7 H8 F5 G6 C1 B1 C2 F4 G2 J5 L2 L7 N5 R2 U5 W2 U1 35GPIO_HEADER_3_LS 2 1 R207 150 1/16W 5% 1 2 R126 100 1/16W 5% 1 2 X 5R 10 V 0. 1U F C1 VCC1V5 FPGA_ONCHIP_TERM2 FPGA_ONCHIP_TERM1 FPGA_VTEMP 14GPIO_BUTTON3 14GPIO_BUTTON1 14GPIO_BUTTON2 14CPU_RESET PCIE_PERST_B_LS 35 35GPIO_HEADER_0_LS GPIO_HEADER_1_LS 35 GPIO_SWITCH_3 14 GPIO_BUTTON0 14 35GPIO_HEADER_2_LS SYSACE_MPA06_LS 35 SYSACE_MPA05_LS 35 SYSACE_MPA04_LS 35 MEM1_A14 9 MEM1_A13 9 MEM1_A11 9 MEM1_RESET_B 9 MEM1_A12 9 MEM1_CKE 9 MEM1_A9 9 MEM1_A8 9 MEM1_A4 9 MEM1_A10 9 MEM1_BA2 9 MEM1_WE_B 9 MEM1_A2 9 MEM1_A7 9 MEM1_BA1 9 MEM1_BA0 9 MEM1_A1 9 MEM1_A0 9 MEM1_CLK_N 9 MEM1_CLK_P 9 MEM1_ODT 9 MEM1_A3 9 MEM1_A6 9 MEM1_A5 9 MEM1_CAS_B 9 MEM1_RAS_B 9 MEM1_LDM 9 MEM1_UDM 9 MEM1_DQ5 9 MEM1_DQ4 9 MEM1_DQ7 9 MEM1_DQ6 9 MEM1_LDQS_N 9 MEM1_LDQS_P 9 MEM1_DQ3 9 MEM1_DQ2 9 MEM1_DQ1 9 MEM1_DQ0 9 MEM1_DQ9 9 MEM1_DQ8 9 MEM1_DQ11 9 MEM1_DQ10 9 MEM1_UDQS_N 9 MEM1_UDQS_P 9 MEM1_DQ13 9 MEM1_DQ12 9 MEM1_DQ15 9 MEM1_DQ14 9 SYSACE_D7_LS 35 SYSACE_D6_LS 35 SYSACE_D5_LS 35 SYSACE_D4_LS 35 SYSACE_D3_LS 35 SYSACE_D2_LS 35 SYSACE_D1_LS 35 SYSACE_D0_LS 35 SYSACE_MPBRDY_LS 35 SYSACE_MPIRQ_LS 35 SYSACE_MPA03_LS 35 SYSACE_MPA02_LS 35 SYSACE_MPA01_LS 35 SYSACE_MPA00_LS 35 SYSACE_MPWE_LS 35 SYSACE_MPOE_LS 35 SYSACE_MPCE_LS 35 ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By MGTAVTTRX_123_D14 MGTAVTTTX_123_A15 MGTAVCC_123_E10 MGTAVCCPLL1_123_E13 MGTAVCCPLL0_123_B13 MGTREFCLK1N_123_F12 MGTREFCLK1P_123_E12 MGTREFCLK0N_123_B12 MGTREFCLK0P_123_A12 MGTRXN1_123_C15 MGTRXP1_123_D15 MGTTXN1_123_A16 MGTTXP1_123_B16 MGTRXN0_123_C13 MGTRXP0_123_D13 MGTTXN0_123_A14 MGTTXP0_123_B14 6slx45tfg484 BANK 123 DUT MGTAVTTRX_101_D8 MGTAVTTTX_101_A7 MGTAVCC_101_C10 MGTAVCCPLL1_101_D12 MGTAVCCPLL0_101_B9 MGTREFCLK1N_101_D11 MGTREFCLK1P_101_C11 MGTREFCLK0N_101_B10 MGTREFCLK0P_101_A10 MGTRXN1_101_C9 MGTRXP1_101_D9 MGTTXN1_101_A8 MGTTXP1_101_B8 MGTRXN0_101_C7 MGTRXP0_101_D7 MGTTXN0_101_A6 MGTTXP0_101_B6 6slx45tfg484 BANK 101 DUT Test P/N: TSS0123 ART P/N: 1280473 SCH P/N: 0381305 PCB P/N: 0431534 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM MGT Banks MGT Banks D 6 35 9-18-2009_15:04 BF 04FMC_GBTCLK0_M2C_C_N 6 FMC_GBTCLK0_M2C_C_P 6 FMC_GBTCLK0_M2C_C_P 6 FMC_GBTCLK0_M2C_C_N 6 10 FMC_GBTCLK0_M2C_P 10 FMC_GBTCLK0_M2C_N 1 2 X 5R 10 V 0. 1U FC401 D8 A7 C10 D12 B9 D11 C11 B10 A10 C9 D9 A8 B8 C7 D7 A6 B6 U1 D14 A15 E10 E13 B13 F12 E12 B12 A12 C15 D15 A16 B16 C13 D13 A14 B14 U1 1 2 X5R 10V 4.7UF C329 2 1 C328 4.7UF 10V X5R 1 2 X5R 10V 4.7UF C327 MGT_AVCC 2 1 C307 0.22UF 10V X7R MGT_AVCC SFPCLK_QO_P 28 SFPCLK_QO_N 28 PCIE_250M_P 28 PCIE_250M_N 28 13SMA_RX_N PCIE_TX0_P 12 SFP_TX_P 12 SFP_TX_N 12 SFP_RX_P 12 SFP_RX_N 12 10FMC_DP0_C2M_P FMC_DP0_C2M_N 10 10FMC_DP0_M2C_P FMC_DP0_M2C_N 10 PCIE_TX0_N 12 12PCIE_RX0_P PCIE_RX0_N 12 SMA_TX_P 13 SMA_TX_N 13 13SMA_RX_P 13SMA_REFCLK_P 13SMA_REFCLK_N MGT_AVCC 1 2 X7R 10V 0.22UF C308 2 1 C309 0.22UF 10V X7R 1 2 X7R 10V 0.22UF C310 2 1 C311 0.22UF 10V X7R 1 2 X7R 10V 0.22UF C316 2 1 C315 0.22UF 10V X7R 1 2 X7R 10V 0.22UF C314 2 1 C313 0.22UF 10V X7R 1 2 X7R 10V 0.22UF C312 2 1 C326 4.7UF 10V X5R 21 C400 0. 1U F 10 V X 5R Y8 Y1 Y3 Y4 Y5 Y6 Y7 Y2 OE1_N A1 A3 A4 A2 A5 A8 A7 A6 GND SN74LV541APWR OE2_N VCC VCCINT_FPGA VCCAUX VCC2V5 ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By VCCAUX VCCINT_J10 VCCINT_J12 VCCINT_J14 VCCINT_J8 VCCINT_K11 VCCINT_K13 VCCINT_K9 VCCINT_L10 VCCINT_L12 VCCINT_L14 VCCINT_M11 VCCINT_M13 VCCINT_M9 VCCINT_N10 VCCINT_N12 VCCINT_N14 VCCINT_P11 VCCINT_P13 VCCINT_P9 VCCINT_R14 6slx45tfg484 BANK VCCINT DUT TCK_A21 TDI_E18 TMS_D20 TDO_G17 SUSPEND_AA22 CMPCS_B_2_V18 DONE_2_AB21 PROGRAM_B_2_AB2 MGTRREF_101_E9 MGTAVTTRCAL_101_E8 NC_U17 NC_T16 NC_P15 6slx45tfg484 BANK DED DUT VCCAUX_F11 VCCAUX_G12 VCCAUX_H15 VCCAUX_H9 VCCAUX_K15 VCCAUX_L8 VCCAUX_M15 VCCAUX_N8 VCCAUX_R10 VCCAUX_R12 VCCAUX_R6 VCCAUX_U11 VCCAUX_V6 6slx45tfg484 BANK VCCAUX DUT GND_A1 GND_A11 GND_A13 GND_A22 GND_A9 GND_AA13 GND_AA17 GND_AA5 GND_AA9 GND_AB1 GND_AB22 GND_B11 GND_B15 GND_B17 GND_B5 GND_B7 GND_C12 GND_C14 GND_C16 GND_C6 GND_C8 GND_D10 GND_D16 GND_D6 GND_E11 GND_E14 GND_E15 GND_E2 GND_E21 GND_E7 GND_F13 GND_G18 GND_G5 GND_H7 GND_J11 GND_J13 GND_J15 GND_J2 GND_J21 GND_J9 GND_K10 GND_K12 GND_K14 GND_L11 GND_L13 GND_L18 GND_L5 GND_L9 GND_M10 GND_M12 GND_M14 GND_N11 GND_N13 GND_N17 GND_N2 GND_N21 GND_N9 GND_P10 GND_P12 GND_P14 GND_R18 GND_R5 GND_U2 GND_U21 GND_U7 GND_V10 GND_V14 GND_V4 GND_W16 GND_W19 GND_W7 6slx45tfg484 BANK GND DUT PCB P/N: 0431534 SCH P/N: 0381305 ART P/N: 1280473 Test P/N: TSS0123 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Trace length from the resistor pins to the FPGA pins MGTRREF and MGTVTTRCAL must be equal in length. Power, GND, and Dedicated Banks Power, GND, and Dedicated Banks Pins not connected in LX45T BF 04 9-24-2009_14:59 357 D A1 A11 A13 A22 A9 AA13 AA17 AA5 AA9 AB1 AB22 B11 B15 B17 B5 B7 C12 C14 C16 C6 C8 D10 D16 D6 E11 E14 E15 E2 E21 E7 F13 G18 G5 H7 J11 J13 J15 J2 J21 J9 K10 K12 K14 L11 L13 L18 L5 L9 M10 M12 M14 N11 N13 N17 N2 N21 N9 P10 P12 P14 R18 R5 U2 U21 U7 V10 V14 V4 W16 W19 W7 U1 F11 G12 H15 H9 K15 L8 M15 N8 R10 R12 R6 U11 V6 U1 A21 E18 D20 G17 AA22 V18 AB21 AB2 E9 E8 U17 T16 P15 U1 J10 J12 J14 J8 K11 K13 K9 L10 L12 L14 M11 M13 M9 N10 N12 N14 P11 P13 P9 R14 U1 1 2 R 28 8 D N P 1/ 16 W 1% 1 2 J 59 D N P 2 1 H - 1X 2 J 58 4,10,19 FMC_PWR_GOOD_FLASH_RST_B 2 1 1% 1/16W DNP R260 2 1 1% 1/16W 49.9 R127 2 1 5% 1/16W 4.7K R11 14,18,20FPGA_PROG_B FPGA_DONE 14 18FPGA_CMP_CS_B FPGA_SUSPEND 18 SYSACE_CFGTDI 20 20FPGA_TMS 20FPGA_TCK 20FPGA_TDI MGT_AVCC NCNC JTAG_TCK32 FMC_TCK_BUF 10 20SYSACE_TCK_BUF JTAG_TDI32 10FMC_TMS_BUF NC NC JTAG_TMS32 VCC3V3 VCC3V3 2 1 C2 0.1UF 10V X5R 1 2 R172 10K 1/16W 5% NC NC 20SYSACE_TMS_BUF FMC_TDI_BUF 10 11 18 16 15 14 13 12 17 1 2 4 5 3 6 9 8 7 10 19 20 U8 15FPGA_VBATT VCCAUX VCCINT_FPGA VCC1V5_FPGA VCC2V5_FPGA ofSheet Date: Title: Ver: A B C D 1234 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By Test P/N: TSS0123 ART P/N: 1280473 SCH P/N: 0381305 PCB P/N: 0431534 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM VCCO Bank 3 1.5V VCCO 2.5V VCCINT 1.2V