Cyclone IV Device Family Pin Connection Guidelines

Cyclone ® IV Device Family Pin Connection Guidelines PCG-01008- 1.4 © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. 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Disclaimer Page 1 of 14 Cyclone GX IV Devices Pin Name Cyclone IV E Devices Pin Name Pin Type (1st, 2nd, and 3rd Function) Pin Description Connection Guidelines CLK[5, 7, 9, 11, 12, 14, 17, 19, 20, 22], DIFFCLK_[0..9]p (Note 9) REFCLK[0..5]p (Note 22), (Note 24) CLK[0,2,4,6,9,11,13,15], DIFFCLK_[1..7]p (Note 9) Clock, Input Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins. In Cyclone IV GX devices, some of these pins are optional high speed differential reference clock positive input. Connect unused CLK or DIFFCLK pins to GND. See Note 12. In Cyclone IV GX devices, the pin should be AC-coupled if used as optional high speed differential reference clock input. Connect all unused pins either individually to GND through a 10-KΩ resistor or tie all unused pins together through a single 10-KΩ resistor. Ensure that the trace from the pins to the resistor(s) is as short as possible. CLK[4, 6, 8, 10, 13, 15, 16, 18, 21, 23], DIFFCLK_[0..9]n (Note 9) REFCLK[0..5]n (Note 22), (Note 24) CLK[1,3,5,7,8,10,12,14], DIFFCLK_[1..7]n (Note 9) Clock, Input Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. In Cyclone IV GX devices, some of these pins are optional high speed differential reference clock complement input. Connect unused CLK or DIFFCLK pins to GND. See Note 12. In Cyclone IV GX devices, the pin should be AC-coupled if used as optional high speed differential reference clock input. Connect all unused pins either individually to GND through a 10-KΩ resistor or tie all unused pins together through a single 10-KΩ resistor. Ensure that the trace from the pins to the resistor(s) is as short as possible. PLL[1,2,3,4,5,8]_CLKOUTp (Note 10) PLL[1..4]_CLKOUTp (Note 10) I/O, Output Optional positive terminal for external clock outputs from PLL [1..8] in Cyclone IV GX devices. Optional positive terminal for external clock outputs from PLL [1..4] in Cyclone IV E devices. Each pin can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output. When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II software. See Note 12. PLL[1,2,3,4,5,8]_CLKOUTn (Note 10) PLL[1..4]_CLKOUTn (Note 10) I/O, Output Optional negative terminal for external clock outputs from PLL [1..8] in Cyclone IV GX devices. Optional negative terminal for external clock outputs from PLL [1..4] in Cyclone IV E devices. Each pin can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output. When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II software. See Note 12. MSEL[0..3] MSEL[0..3] Input Configuration input pins that set the Cyclone IV device configuration scheme. The smaller Cyclone IV GX devices like EP4CGX15, EP4CGX22, and EP4CGX30 (except F484 package) do not have the MSEL[3] pin. Some of the smaller Cyclone IV E devices or package options do not support AP configuration scheme and do not have the MSEL[3] pin. These pins are internally connected through a 9-KΩ resistor to GND. Do not leave these pins floating. When these pins are unused, connect them to GND. Depending on the configuration scheme used, these pins should be tied to VCCA or GND. Refer to the "Configuration and Remote System Upgrades in Cyclone IV Devices" chapter in the Cyclone IV Handbook. If only JTAG configuration is used, connect these pins to GND. nCE nCE Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. In a multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In single device configuration and JTAG programming, nCE should be connected to GND. nCONFIG nCONFIG Input Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. If you are using PS configuration scheme with a download cable, connect this pin through a 10-KΩ resistor to VCCA. For other configuration schemes, if this pin is not used, this pin must be connected directly or through a 10-KΩ resistor to VCCIO. CONF_DONE CONF_DONE Bidirectional (open-drain) This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. This pin is not available as a user I/O pin. CONF_DONE should be pulled high by an external 10-KΩ pull-up resistor. nCEO (Note 24) nCEO I/O, Output (open-drain) Output that drives low when device configuration is complete. This pin can be used as a regular I/O if not used for device configuration. When not using this pin, you can leave it unconnected. During multi-device configuration, this pin feeds the nCE pin of a subsequent device. In this case, tie the 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain which satisfies the input voltage of the receiving device. During single device configuration, this pin can be used as a regular I/O. nSTATUS nSTATUS Bidirectional (open-drain) This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. This pin is not available as a user I/O pin. nSTATUS should be pulled high by an external 10-KΩ pull-up resistor. TCK TCK Input Dedicated JTAG test clock input pin. Connect this pin to a 1-KΩ pull-down resistor to GND. To disable the JTAG circuitry connect TCK to GND. TMS TMS Input Dedicated JTAG test mode select input pin. Connect this pin to a 1-KΩ to 10-KΩ pull-up resistor to VCCA. (Note 13) To disable the JTAG circuitry connect TMS to VCCA.TDI TDI Input Dedicated JTAG test data input pin. Connect this pin to a 1-KΩ to 10-KΩ pull-up resistor to VCCA. (Note 13) To disable the JTAG circuitry connect TDI to VCCA.TDO TDO Output Dedicated JTAG test data output pin. If the TDO pin is not used, leave this pin unconnected. nCSO (Note 24) FLASH_nCE, nCSO I/O, Output (AS, AP Note 18) This pin functions as FLASH_nCE in AP (Note 18) mode, and nCSO in AS mode. nCSO: Output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device. FLASH_nCE: Output control signal from the FPGA to the parallel flash in AP mode that enables the flash device. When not programming the device in AS mode, nCSO is not used. When not programming the device in AP mode, FLASH_nCE is not used. If the pin is not used as an I/O, you should leave the pin unconnected. DATA1, ASDO (Note 24) DATA1, ASDO Input (FPP) Output (AS) Bidirectional open-drain (AP Note 18) This pin functions as DATA1 in PS and FPP modes, and as ASDO in AS mode. DATA1: Data input in non-AS mode. Byte-wide configuration data is presented to the target device on DATA[0..7]. In PS configuration scheme, DATA1 functions as user I/O pin during configuration, which means it is tri-stated. After FPP configuration, DATA1 is available as a user I/O pin and the state of this pin depends on the Dual- Purpose Pin settings. ASDO: Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data. When not programming the device in AS mode, this pin is available as a user I/O pin. If the pin is not used as an I/O, then you should leave the pin unconnected. DATA[2..7] DATA[2..7] Input (FPP) Bidirectional (AP Note 18) Data inputs. Byte-wide or word-wide configuration data is presented to the target device on DATA[0..7] or DATA[0..15] respectively. In AS or PS configuration scheme, they function as user I/O pins during configuration, which means they are tri-stated. After FPP configuration, DATA [2..7] are available as user I/O pins and the state of these pins depends on the Dual- Purpose Pin settings. When not programming the device in AP mode, these pins are available as a user I/O pins. If the pin is not used as an I/O you should leave the pin unconnected. NA DATA[8..15] Bidirectional (AP Note 18) In the PS, FPP, or AS configuration scheme, they function as user I/O pins during configuration, which means they are tri-stated. After AP configuration, DATA[8..15] are dedicated bidirectional pins with optional user control. When not programming the device in AP mode, these pins are available as user I/O pins. If these pins are not used as I/Os, then it is recommended to leave the pin unconnected. NA PADD[0..23] Output (AP Note 18) 24-bit address bus from the Cyclone IV E device to the parallel flash in AP mode. When not programming the device in AP mode, these pins are available as user I/O pins. If these pins are not used as I/Os, then it is recommended to leave the pin unconnected. Cyclone ® IV Device Family Pin Connection Guidelines PCG-01008- 1.4 Clock and PLL Pins Create a Quartus ® II design, enter your device I/O assignments and compile the design. The Quartus II software will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook. Configuration/ JTAG Pins PCG-01008-1.4 Copyright © 2011 Altera Corp. Pin Connection Guidelines Page 2 of 14 Cyclone GX IV Devices Pin Name Cyclone IV E Devices Pin Name Pin Type (1st, 2nd, and 3rd Function) Pin Description Connection Guidelines Cyclone ® IV Device Family Pin Connection Guidelines PCG-01008- 1.4 Create a Quartus ® II design, enter your device I/O assignments and compile the design. The Quartus II software will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook. NA nRESET Output (AP Note 18) Active-low reset output. Driving the nRESET pin low resets the parallel flash. When not programming the device in AP mode, nRESET is not used and is available as a user I/O pin. If the pin is not used as an I/O then it is recommended to leave the pin unconnected. NA nAVD Output (AP Note 18) Active-low address valid output. Driving the nAVD pin low during read or write operation indicates to the parallel flash that valid address is present on the PADD[0..23] address bus. When not programming the device in AP mode, nAVD is not used and is available as a user I/O pin. If the pin is not used as an I/O then it is recommended to leave the pin unconnected. NA nOE Output (AP Note 18) Active-low output enable to the parallel flash. Driving the nOE pin low during read operation enables the parallel flash outputs (DATA[0..15] and RDY). When not programming the device in AP mode, nOE is not used and is available as a user I/O pin. If the pin is not used as an I/O then it is recommended to leave the pin unconnected. NA nWE Output (AP Note 18) Active-low write enable to the parallel flash. Driving the nWE pin low during write operation indicates to the parallel flash that data on the DATA[0..15] bus is valid. When not programming the device in AP mode, nWE is not used and is available as a user I/O pin. If the pin is not used as an I/O then it is recommended to leave the pin unconnected. DCLK DCLK Input (PS, FPP) Output (AS, AP Note 18) Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS and AP (Note 18) modes, DCLK is an output from the FPGA that provides timing for the configuration interface. Do not leave this pin floating. Drive this pin either high or low. CRC_ERROR (Note 24) CRC_ERROR (Note 19 and 21) I/O, Output Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. This pin can be used as regular I/O if not used for CRC error detection. The CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain output in the Device & Pin option dialog box in the Quartus II software. When using this pin, connect it to an external 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain that satisfies the input voltage of the receiving device. When not using this pin, it can be left floating. DEV_CLRn DEV_CLRn I/O (when option off), Input (when option on) Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II software. When the dedicated input DEV_CLRn is not used and this pin is not used as an I/O, tie this pin to GND. DEV_OE DEV_OE I/O (when option off), Input (when option on) Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. This pin is enabled by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II software. When the dedicated input DEV_OE is not used and this pin is not used as an I/O, then you should tie this pin to GND. DATA0 (Note 24) DATA0 Input (PS, FPP, AS) Bidirectional open-drain (AP Note 18) Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is received through this pin. After AS configuration, DATA0 is a dedicated input pin with optional user control. After PS or FPP configuration, DATA0 is available as a user I/O pin and the state of this pin depends on the Dual-Purpose Pin settings. After AP (Note 18) configuration, DATA0 is a dedicated bidirectional pin with optional user control. If you are using a serial configuration device in AS configuration mode, you must connect a 25-Ω series resistor at the near end of the serial configuration device for the DATA0. When the dedicated input for DATA0 is not used and this pin is not used as an I/O, then you should to leave this pin unconnected. INIT_DONE (Note 24) INIT_DONE I/O, Output (open-drain) This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be use