HMC5843(3轴罗盘)

3-Axis Digital Compass IC HMC5843 The Honeywell HMC5843 is a surface mount multi-chip module designed for low field magnetic sensing with a digital interface for applications such as low cost compassing and magnetometry. The HMC5843 includes our state of the art 1043 series magneto-resistive sensors plus Honeywell developed ASIC containing amplification, strap drivers, offset cancellation, 12-bit ADC and an I2C serial bus interface. The HMC5843 is in a 4.0 by 4.0 by 1.3mm surface mount leadless chip carrier (LCC). Applications for the HMC5843 include Consumer Electronics, Auto Navigation Systems, Personal Navigation Devices, and Magnetometers. The HMC5843 utilizes Honeywell’s Anisotropic Magnetoresistive (AMR) technology that provides advantages over other magnetic sensor technologies. The sensors feature precision in-axis sensitivity and linearity, solid-state construction with very low cross-axis sensitivity designed to measure both direction and magnitude of Earth’s magnetic fields, from tens of micro-gauss to 6 gauss. Honeywell’s Magnetic Sensors are among the most sensitive and reliable low-field sensors in the industry. Honeywell continues to maintain product excellence and performance by introducing innovative solid-state magnetic sensor solutions. These are highly reliable, top performance products that are delivered when promised. Honeywell’s magnetic sensor solutions provide real solutions you can count on. FEATURES BENEFITS 4 3-Axis Magnetoresistive Sensors and ASIC in a Single Package 4 Small Size for Highly Integrated Products. Just Add a Micro- Controller Interface, Plus Two External SMT Capacitors 4 Low Cost 4 Designed for High Volume, Cost Sensitive OEM Designs 4 4.0 x 4.0 x 1.3mm Low Height Profile LCC Surface Mount Package 4 Easy to Assemble & Compatible with High Speed SMT Assembly 4 Low Voltage Operations (2.5 to 3.3V) 4 Compatible for Battery Powered Applications 4 Built-In Strap Drive Circuits 4 Set/Reset and Offset Strap Drivers for Degaussing, Self Test, and Offset Compensation 4 I 2C Digital Interface 4 Popular Two-Wire Serial Data Interface for Consumer Electronics 4 Lead Free Package Construction 4 Complies with Current Environmental Standards 4 Wide Magnetic Field Range (+/-6 Oe) 4 Sensors Can Be Used in Strong Magnetic Field Environments 4 Available in Tape & Reel Packaging 4 High Volume OEM Assembly HMC5843 2 www.honeywell.com SPECIFICATIONS (* Tested at 25°C except stated otherwise.) Characteristics Conditions* Min Typ Max Units Power Supply Supply Voltage AVDD Referenced to AGND DVDD Referenced to DGND 2.5 1.6 1.8 3.3 2.0 Volts Volts Current Draw Sleep Mode (dual supplies) Idle Mode (dual supplies) Measurement Mode AVDD = 2.5 volts, DVDD = 1.8 volts Sleep Mode (single supply) Idle Mode (single supply) Measurement Mode AVDD = 2.5 volts - - - - - - 2.5 240 0.8 110 340 0.9 - - - - - - uA uA mA uA uA mA Performance Field Range Full scale (FS) – total applied field -4 +4 gauss Cross-Axis Sensitivity Cross field = 0.5 gauss, Happlied = ±3 gauss ±0.2% %FS/gauss Disturbing Field Sensitivity starts to degrade. Use S/R pulse to restore sensitivity. 20 gauss Max. Exposed Field No perming effect on zero reading 10000 gauss Measurement Period Output Rate = 50Hz (10Hz typ.) - 10 msec I2C Address 7-bit address 8-bit read address 8-bit write address 0x1E 0x3D 0x3C hex hex hex I2C Rate Controlled by I2C Master -10 +10 % I2C bus pull-up Internal passive resistors 50 kilo-ohms I2C Hysteresis Hysteresis of Schmitt trigger inputs on SCL and SDA - Fall (DVDD=1.8V) Rise (DVDD=1.8V) 0.603 1.108 Volts Volts Self Test Positive and Negative Bias Mode ±0.55 gauss Mag Dynamic Range 3-bit gain control ±0.7 ±1.0 ±4.0 gauss Linearity Full scale input range 0.1 ±% FS Gain Tolerance All gain/dynamic range settings ±5 % Bandwidth -3dB point 10 kHz Resolution AVDD=3.0V, GN 7 milli-gauss Signal-to Noise Ratio 70 dB Turn-on Time 200 us General ESD Voltage 700 V Operating Temperature Ambient -30 85 °C Storage Temperature Ambient, unbiased -40 125 °C Weight Nominal 50 milli-grams HMC5843 www.honeywell.com 3 PIN CONFIGURATIONS (Arrow indicates direction of applied field that generates a positive output voltage after a SET pulse.) Pin Name Description 1 SCL Serial Clock – I2C Master/Slave Clock 2 SDAP Serial Data Pull-up Resistor – 50k-ohm to VDD 3 SCLP Serial Clock Pull-up Resistor – 50k-ohm to VDD 4 NC No Connection 5 NC No Connection 6 OFFP Offset Strap Positive 7 OFFN Offset Strap Negative 8 NC No Connection 9 SETP Set/Reset Strap Positive – S/R Capacitor (C2) Connection 10 SETN Set/Reset Strap Negative – Test Point 11 SVDD Sensor Supply – Test Point 12 DGND Digital Supply Ground/Return 13 C1 Reservoir Capacitor (C1) Connection 14 SETC S/R Capacitor (C2) Connection – Driver Side 15 DVDD Digital Positive Supply 16 VREN Voltage Regulator Enable, (GND = Dual Supply, AVDD = Single Supply) 17 AGND Analog Supply Ground/Return 18 AVDD Analog Positive Supply 19 DRDY Data Ready – Test Point 20 SDA Serial Data – I2C Master/Slave Data Table 1: Pin Configurations 1 2 3 4 5 6 7 8 9 10 1112131415 16 17 18 19 20 HMC5843 – bottom view S C L S D A P S C LP TP 1 TP 0 OFFP OFFN NC SETP SETN S V D D D G N D C 1 S E T C D V D D VREN AGND AVDD DRDY SDA X Y Z 1 2 3 4 5 6 7 8 9 10 1112131415 16 17 18 19 20 HMC5843 – bottom view S C L S D A P S C LP TP 1 TP 0 OFFP OFFN NC SETP SETN S V D D D G N D C 1 S E T C D V D D VREN AGND AVDD DRDY SDA X Y Z HMC5843 4 www.honeywell.com PACKAGE OUTLINES PACKAGE DRAWING HMC5843 (20-PIN LPCC, dimensions in millimeters) MOUNTING CONSIDERATIONS The following is the recommend printed circuit board (PCB) footprint for the HMC5843. PCB Pad Definition and Traces The HMC5843 is a fine pitch LCC package with a 0.50mm pin pitch (spacing), with the pin pads defined as 0.40mm by 0.25mm in size. PCB pads are recommended to be oversized by 0.025mm from each pad for a short dimension oversize of 0.05mm. The interior PCB pad is recommended to be 0.05mm oversized per pin with an exterior oversize of 0.20mm for proper package centering and to permit test probing. Size the traces between the HMC5843 and the external capacitors (C1 and C2) to handle the 1 ampere peak current pulses with low voltage drop on the traces. Stencil Design and Solder Paste A 4 mil stencil and 100% paste coverage is recommended for the electrical contact pads. Pick and Place Placement is machine dependant and no restrictions are recommended, and have been tested with mechanical centering. Placement force should be equivalent 1206 SMT resistors and enough force should be used to squeeze the paste out from the package/contact pad overlap and to keep the package pin contacts vertical. Reflow and Rework No special profile is required for the HMC5843 and compatible with lead eutectic and lead-free solder paste reflow profiles. Honeywell recommends the adherence to solder paste manufacturer’s guidelines. The HMC5843 may be reworked with soldering irons, but extreme care must be taken not to overheat the copper pads from the part’s fiberglass substrate. Irons with a tip temperature no greater than 315°C should be used. Excessive rework risks the copper pads pulling away into the molten solder. Sym Min Nom Max A 1.20 - 1.46 D 4.0 BSC D2 2.25 D3 0.25 x 20 pins E 4.0 BSC E2 2.25 e 0.50 Basic L 0.40 x 20 pins Pin 1 HMC5843 – bottom view E D E2 D2 A D3 L e HMC5843 www.honeywell.com 5 INTERNAL SCHEMATIC DIAGRAM HMC5843 DUAL SUPPLY REFERENCE DESIGN HMC5843 6 www.honeywell.com SINGLE SUPPLY REFERENCE DESIGN BASIC DEVICE OPERATION Anisotropic Magneto-Resistive Sensors The Honeywell HMC5843 magnetoresistive sensor circuit is a trio of sensors and application specific support circuits to measure magnetic fields. With power supply applied, the sensor converts any incident magnetic field in the sensitive axis directions to a differential voltage output. The magnetoresistive sensors are made of a nickel-iron (Permalloy) thin-film and patterned as a resistive strip element. In the presence of a magnetic field, a change in the bridge resistive elements causes a corresponding change in voltage across the bridge outputs. These resistive elements are aligned together to have a common sensitive axis (indicated by arrows on the pinouts) that will provide positive voltage change with magnetic fields increasing in the sensitive direction. Because the output only is in proportion to the one-dimensional axis (the principle of anisotropy) and its magnitude, additional sensor bridges placed at orthogonal directions permit accurate measurement of arbitrary field direction. Self Test An offset strap is designed for self test function. The offset strap measures nominally 13 ohms, and requires 10mA for each gauss of induced field. The straps will easily handle currents to buck or boost fields through the ±4 gauss linear measurement range, but designers should note the extreme thermal heating on the sensor die when doing so. HMC5843 www.honeywell.com 7 Power Management This device is capable of operating with a single supply (AVDD) or dual supplies (AVDD and DVDD). Pin VREN makes this selection by enabling the internal digital supply voltage regulator. When VREN is tied to AVDD, the device is in single supply operation; this device is powered from AVDD; and the internal voltage regulator is enabled. When VREN is tied to AGND this devices operates with both AVDD and DVDD as supplies. The table below shows the modes available at the various power supply conditions. Table 2: Operational Modes and Supply States Note the continuous current draw versus data update rate in micro-amperes shown in the graph below. Under 10Hz, the current stays below 1mA. DVDD AVDD Pin VREN Modes Supported Description High High AGND All, except Off Internal voltage regulator: Disabled. Digital I/O pins: Range from DGND to DVDD. Device fully functional. Digital logic blocks are powered from DVDD supply, including all on- board clocks. High Low AGND Idle Internal voltage regulator: Disabled. Digital I/O pins: Range from DGND to DVDD. Device Measurement functionality not supported. Device I2C bus and register access supported. Internally regulated High AVDD All, except Off Internal voltage regulator: Enabled Digital I/O pins: Range from AGND to AVDD Device fully functional. Digital logic blocks are powered through on-board regulator. Low Low -- Off Device in off mode. HMC5843 8 www.honeywell.com Voltage Regulator This ASIC has an internal voltage regulator which, depending on the application needs, may be used instead of supplying voltage to pin DVDD. If DVDD pin is used, the internal voltage regulator is not engaged. When both supplies are used, DVDD is typically high before AVDD, but no latch-up conditions will exist if DVDD is brought high after AVDD. Power on Reset Power on reset (POR) circuit shall return the device to the power-on default state. All registers shall be returned to their default values. Circuitry shall return to it default state, such as, but not limited to: MUX channel, ADC state machine, and bias current. I2C Interface Control of this device is carried out via the I2C bus. This device will be connected to this bus as a slave device under the control of a master device, such as the processor. This device shall be compliant with I2C-Bus Specification, document number: 9398 393 40011. As an I2C compatible device, this device has a 7-bit serial address and supports I2C protocols. This device shall support standard and fast modes, 100kHz and 400kHz respectively, but cannot support the high speed mode (Hs). External pull-up resistors are required to support these standard and fast speed modes. Depending on the application, the internal pull-ups may be used to support slower data speeds than specified by I2C standards. This device does not contain 50nsec spike suppression as required by fast mode operation in the I2C-Bus Specification, “Table 4 Characteristics of the SDA and SCL I/O stages for F/S-mode I2C-bus devices”. Activities required by the master (register read and write) have priority over internal activities, such as the measurement. The purpose of this priority is to not keep the master waiting and the I2C bus engaged for longer than necessary. I2C Pull-up Resistors Pull-up resistors are placed on the two I2C bus lines. Typically these resistors are off-chip, but, to conserve board space in specific low clock speed applications, they are internal to this device. Internal Clock The device has an internal clock for internal digital logic functions and timing management. H-Bridge for Set/Reset Strap Drive The ASIC contains large switching FETs capable of delivering a large but brief pulse to the Set / Reset strap of the sensor. This strap is largely a resistive load. HMC5843 www.honeywell.com 9 Charge Current Limit The current that reservoir capacitor (C1) can draw when charging is limited. When using dual supplies this device shall limit the current drawn from DVDD source to charge this capacitor. When only a single supply is used, Pin DVDD is externally tied to pin C1. In this configuration, current is still limited. For example, the internal voltage regulator will limit this current draw. Bias Current Generator The bias current generator is used to apply a bias current to the offset strap of the magneto-resistive sensor, which creates an artificial magnetic field bias on the sensor. This function is enabled and the polarity is set by bits MS[n] in the configuration register. The bias current generator generates dc current supplied from the AVDD supply. MODES OF OPERATION This device has several modes whose primary purpose is power management. This section describes these modes. Continuous-Measurement Mode During continuous-measurement mode, the device continuously makes measurements and places measured data in data output registers. Settings in the configuration register affect the data output rate (bits DO[n]), the measurement configuration (bits MS[n]), and the gain (bits GN[n]) when in continuous-measurement mode. To conserve current between measurements, the device is placed in a state similar to idle mode, but the mode is not changed to idle mode. That is, MD[n] bits are unchanged. Data can be re-read from the data output registers if necessary; however, if the master does not ensure that the data register is accessed before the completion of the next measurement, the new measurement may be lost. All registers maintain values while in continuous-measurement mode. The I2C bus is enabled for use by other devices on the network in while continuous-measurement mode. Single-Measurement Mode This is the default single supply power-up mode. In dual supply configuration this is the default mode when AVDD goes high. During single-measurement mode, the device makes a single measurement and places the measured data in data output registers. Settings in the configuration register affect the measurement configuration (bits MS[n]), and the gain (bits GN[n]) when in single-measurement mode. After the measurement is complete and output data registers are updated, the device is placed sleep mode, and the mode register is changed to sleep mode by setting MD[n] bits. All registers maintain values while in single-measurement mode. The I2C bus is enabled for use by other devices on the network while in single-measurement mode. Idle Mode During this mode the device is accessible through the I2C bus, but major sources of power consumption are disabled, such as, but not limited to, the ADC, the amplifier, the SVDD pin, and the sensor bias current. All registers maintain values while in idle mode. The I2C bus is enabled for use by other devices on the network while in idle mode. Sleep Mode This is the default dual supply power-up mode when only DVDD goes high and AVDD remains low. During sleep mode the device functionality is limited to listening to the I2C bus. The internal clock is not running and register values are not maintained while in sleep mode. The only functionality that exists during this mode is the device is able to recognize and execute any instructions specific to this device but does not change from sleep mode due to other traffic on the I2C bus. The I2C bus is enabled for use by other devices on the network while in sleep mode. This mode has two practical differences from idle mode. First this state will create less noise on system since the clock is disabled, and secondly this state is a lower current consuming state since the clock is disabled. Off Mode During off mode device is off. No device functionality exists. Both AVDD and DVDD are low. The I2C bus is enabled for use by other devices on the network in off mode. In this mode the I2C pins shall be in a high imped