74VHC373sj

© 2005 Fairchild Semiconductor Corporation DS011555 www.fairchildsemi.com February 1993 Revised April 2005 74VHC373 O ctal D -Type Latch w ith 3-STATE O utputs 74VHC373 Octal D-Type Latch with 3-STATE Outputs General Description The VHC373 is an advanced high speed CMOS octal D- type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintain- ing the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an out- put enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is LATCHED. When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features � High Speed: tPD 5.0 ns (typ) @ VCC 5V � High Noise Immunity: VNIH VNIL 28% VCC (Min) � Power Down Protection is provided on all inputs � Low Noise: VOLP 0.6V (typ) � Low Power Dissipation: ICC 4 PA (Max) @ TA 25qC � Pin and Function Compatible with 74HC373 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol IEEE/IEC Connection Diagram Order Number Package Number Package Description 74VHC373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC373SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide www.fairchildsemi.com 2 74 VH C3 73 Pin Descriptions Truth Table H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial O0 Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The VHC373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this con- dition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran- sition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Outputs Inputs Outputs LE OE Dn On X H X Z H L L L H L H H L L X O0 3 www.fairchildsemi.com 74VHC373 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. Fairchild does not recommend operation outside databook specifica- tions. Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Noise Characteristics Note 3: Parameter guaranteed by design. Supply Voltage (VCC) �0.5V to � 7.0V DC Input Voltage (VIN) �0.5V to � 7.0V DC Output Voltage (VOUT) �0.5V to VCC � 0.5V Input Diode Current (IIK) �20 mA Output Diode Current r20 mA DC Output Current (IOUT) r25 mA DC VCC/GND Current (ICC) r75 mA Storage Temperature (TSTG) �65qC to �150qC Lead Temperature (TL) (Soldering, 10 seconds) 260qC Supply Voltage (VCC) 2.0V to � 5.5V Input Voltage (VIN) 0V to � 5.5V Output Voltage (VOUT) 0V to VCC Operating Temperature (TOPR) �40qC to �85qC Input Rise and Fall Time (tr, tf) VCC 3.3V r 0.3V 0 a 100 ns/V VCC 5.0 r 0.5V 0 a 20 ns/V Symbol Parameter VCC TA �25qC TA �40qC to �85qC Units Conditions(V) Min Typ Max Min Max VIH HIGH Level 2.0 1.50 1.50 V Input Voltage 3.0 � 5.5 0.7 VCC 0.7 VCC VIL LOW Level 2.0 0.50 0.50 V Input Voltage 3.0 � 5.5 0.3 VCC 0.3 VCC VOH HIGH Level 2.0 1.9 2.0 1.9 VIN VIH IOH �50 PA Output Voltage 3.0 2.9 3.0 2.9 V or VIL 4.5 4.4 4.5 4.4 3.0 2.58 2.48 V IOH �4 mA 4.5 3.94 3.80 IOH �8 mA VOL LOW Level 2.0 0.0 0.1 0.1 VIN VIH IOL 50 PA Output Voltage 3.0 0.0 0.1 0.1 V or VIL 4.5 0.0 0.1 0.1 3.0 0.36 0.44 V IOL 4 mA 4.5 0.36 0.44 IOL 8 mA IOZ 3-STATE Output 5.5 r0.25 r2.5 PA VIN VIH or VIL Off-State Current VOUT VCC or GND IIN Input Leakage Current 0 � 5.5 r0.1 r1.0 PA VIN 5.5 or GND ICC Quiescent Supply Current 5.5 4.0 40.0 PA VIN VCC or GND Symbol Parameter VCC TA �25qC Units Conditions(V) Typ Limits VOLP(Note 3) Quiet Output Maximum Dynamic VOL 5.0 0.6 0.9 V CL 50 pF VOLV(Note 3) Quiet Output Minimum Dynamic VOL 5.0 �0.6 �0.9 V CL 50 pF VIHD(Note 3) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL 50 pF VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF www.fairchildsemi.com 4 74 VH C3 73 AC Electrical Characteristics Note 4: Parameter guaranteed by design. tOSLH |tPLH max � tPLH min |; tOSHL |tPHL max � tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD • VCC • fIN � ICC/8 (per Latch). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) 14 � 13n. AC Operating Requirements Symbol Parameter VCC TA �25qC TA �40qC to �85qC Units Conditions(V) Min Typ Max Min Max tPLH Propagation Delay 3.3 r 0.3 7.0 11.0 1.0 13.0 ns CL 15 pF tPHL Time (LE to On) 9.5 14.5 1.0 16.5 CL 50 pF 5.0 r 0.5 4.9 7.2 1.0 8.5 ns CL 15 pF 6.4 9.2 1.0 10.5 CL 50 pF tPLH Propagation Delay 3.3 r 0.3 7.3 11.4 1.0 13.5 ns CL 15 pF tPHL Time (D to On) 9.8 14.9 1.0 17.0 CL 50 pF 5.0 r 0.5 5.0 7.2 1.0 8.5 CL 15 pF 6.5 9.2 1.0 10.5 CL 50 pF tPZL 3-STATE 3.3 r 0.3 7.3 11.4 1.0 13.5 ns RL 1 k: CL 15 pF tPZH Output 9.8 14.9 1.0 17.0 CL 50 pF Enable Time 5.0 r 0.5 5.5 8.1 1.0 9.5 ns CL 15 pF 7.0 10.1 1.0 11.5 CL 50 pF tPLZ 3-STATE Output 3.3 r 0.3 9.5 13.2 1.0 15.0 ns RL 1 k: CL 50 pF tPHZ Disable Time 5.0 r 0.5 6.5 9.2 1.0 10.5 CL 50 pF tOSLH Output to 3.3 r 0.3 1.5 1.5 ns (Note 4) CL 50 pF tOSHL Output Skew 5.0 r 0.5 1.0 1.0 CL 50 pF CIN Input Capacitance 4 10 10 pF VCC Open COUT Output Capacitance 6 pF VCC 5.0V CPD Power Dissipation 27 pF (Note 5) Capacitance Symbol Parameter VCC TA �25qC TA �40qC to �85qC Units(V) Min Typ Max Min Max tW(H) Minimum Pulse Width (LE) 3.3 r 0.3 5.0 5.0 ns 5.0 r 0.5 5.0 5.0 tS Minimum Set-Up Time 3.3 r 0.3 4.0 4.0 ns 5.0 r 0.5 4.0 4.0 tH Minimum Hold Time 3.3 r 0.3 1.0 1.0 ns 5.0 r 0.5 1.0 1.0 5 www.fairchildsemi.com 74VHC373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74 VH C3 73 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74VHC373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 8 74 VH C3 73 O ct a l D - Ty pe L at ch w ith 3- ST AT E O ut pu ts Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com