LVDS与TMDS得比较

nullA comparison of LVDS vs. TMDS for LCD Monitor Applications A comparison of LVDS vs. TMDS for LCD Monitor Applications February 1999 Interface ApplicationsLDI LVDS Display Interface (Low Voltage Differential Signaling) offered by National Semiconductor Corp. PanelLink™ / TMDS ™ Transition Minimized Differential Signaling offered by Silicon Image Inc.LDI LVDS Display Interface (Low Voltage Differential Signaling) offered by National Semiconductor Corp. PanelLink™ / TMDS ™ Transition Minimized Differential Signaling offered by Silicon Image Inc.Goals of a Monitor InterfaceGoals of a Monitor InterfaceSupports a wide range of panels Drive long, low cost cables Low EMI High noise rejection Open Standard Multiple sources (ICs, Cables, Connectors) Low CostLDI Block DiagramLDI Block DiagramRED 1GRN 1BLUE 1FPLINEFPFRAMEFPSHIFT IN 32.5 - 112 MHz (170 MHz SPM)DRDYControlCMOS/TTL InputsLVDS CLOCK (32.5 to 112 MHz)LVDS DATA DS90C387RED 2GRN 2BLUE 2DC BALANCEPLLDS90CF388DC BALANCE DECODE & DESKEWPLLRED 1GRN 1BLUE 1FPLINEFPFRAMEFPSHIFT OUT 32.5 - 112 MHzDRDYRED 2GRN 2BLUE 2CMOS/TTL Inputs5.376 GbpsControlTMDS Block DiagramTMDS Block DiagramRED 1GRN 1BLUE 1ControlDETIC 25 - 112MHzControlCMOS/TTL InputsTMDS CLOCK (25 to 112MHz)TMDS DATA SiI1x0RED 2GRN 2BLUE 2Data CaptureSERIALIZER888888PLLSiI1x1TMDS DECODERPLLRED 1GRN 1BLUE 1ControlDECLOCK 25 - 112MHzRED 2GRN 2BLUE 2888888CMOS/TTL Inputs2.68 GbpsTMDE DC-Balanced ENCODERBUFFERDE-SERIALIZER55Panel I/F Bandwidth DemandsPanel I/F Bandwidth DemandsPanelXGASXGASXGAWUXGAHDTVUXGAWResolution1024 X 7681280 X 10241600 X 10241600 X 12001920 X10801900 X 1200QXGA2048 X 1536CLK (MHz)6593115133143158211RGB8888888Bandwidth (Gbps)1.562.232.763.293.433.795.06@ 60 Hz refresh / reduced blanking5 Gbps is the need!The OpenLDI Advantage!The OpenLDI Advantage!Bandwidth for today’s (SXGA) and tomorrow’s (UXGA/HDTV/QXGA) high-resolution displays Open Standard: Physical layer defined in ANSI/TIA/EIA-644 Low cost, multiple suppliers of cable & connectors Multiple suppliers of LVDS silicon today No Licenses required Compatible with today’s de-facto Notebook standard digital interface (FPD-Link) LDI vs. TMDSLDI vs. TMDSLDITMDSArchitecture7X10XData Pairs8 (or 4)3Clock Pairs11EncodingNOYESDC BalanceYESYESLVDS StandardYESNO# of Shields in cable1 5Pre-emphasisYESNODeskew (pair-pair)1bit1bit1Intra-pair Skew (+ to -)300ps5%tbit2Note 1: Per VESA P&D Standard, deskew is +/- 1bit time, PanelLink can deskew pair-to-pair skew up to 1 clock cycle. Note 2: Per VESA P&D Standard, Intra-pair skew is 5% maximum of a bit time, SiI datasheet states 10% maximum.only 31ps for UXGAArchitecture Impact - UXGA Architecture Impact - UXGA Cable Clock Freq. (MHz) 162 MHz81 MHzChannel Speed (bps)1.62 Gbps567 MbpsChipset Throughput (bps) 4.860 Gbps4.536 GbpsInformation Rate (bps) 3.888 Gbps3.888 GbpsBit Time (s) 617 ps1.764 nsLDITMDSIntra-pair Skew (ps) 31 or 62ps300psTiming Parameter ComparisonTiming Parameter ComparisonXGAyesterday65MHzSXGAtoday112MHzUXGAtomorrow162MHzHDTVsoon143MHzQXGAfuture211MHz0.6501.9501.5381.1203.3600.8921.6214.8600.6171.4304.2900.6992.1106.3300.4740.2271.8204.3960.3923.1362.5510.5674.5361.7640.5004.0041.9980.7385.9081.354 LDI supports SVGA to QXGA today! LDI keeps line speed under 1Gbps LDI bit time is greater than 1ns LDI total bandwidth (BW) is lower since more efficient Panel SpecificationsPanelLinkLDIPanelClockLine Speed GbpsTotal BW GbpsBit Time nsLine Speed GbpsTotal BW GbpsBit Time nsData Payload ComparisonData Payload ComparisonBit 0Bit 1Bit 2Bit 3Bit 4Bit 5DCENBit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7DCLDI 7 bits per clock 86% efficient No Encoding DC Balanced TMDS 10 bits per clock 80% efficient Encoded DC Balanced CLKDataCLKDataCLK Period7 is Better than 107 is Better than 10Bit widths are larger -> better cable transmission Maximum bandwidth is higher -> supports higher resolution panels today Timing margins are larger -> better data recovery Inter-pair skew tolerance is larger (equal to a bit time) Intra-pair skew tolerance is larger (% of a bit time) Lower frequency circuitry on chip: promotes integration less high frequency EMI Efficiency Comparison Efficiency Comparison LDI 7 bit payload 6 Pixel Data bits 1 DC Balance Bit TMDS 10 bit (TM Encoded) payload 8 Pixel Data bits 1 encoding bit 1 DC Balance bit86%80%LVDS6 78 10LDI TransmissionLDI TransmissionPixel Data 7 bit frame (6 data) DC Balanced 86% Efficient Divide by 7: Larger sub symbols Maximizes Sampling Margins Increases Intra-pair skew toleranceControl Data Minimum Transitions (2 maximum)Active DataBlankingDETMDS TransmissionTMDS TransmissionPixel Data 10 bit frame (8 data) DC Balanced Encoded (22% less transitions) 80% Efficient Divide by 10: decreases F maximum decreases intra-pair skew toleranceControl Data Maximum Transitions (8 transitions per pair) DC BalancedActive DataBlankingDETransition MinimizedT’ MaximizedSXGA Application Transition ComparisonSXGA Application Transition ComparisonACTIVE DATA 72.5%BLANKING 27.5%3.5 transitions X 4 Pairs = 142 transitions X 4 Pairs = 83.12* transitions X 3 Pairs = 9.368 transitions X 3 Pairs = 24TOTAL (100%)12.3513.39SXGA application w/ 112 MHz, 60Hz refresh: LDI in Single Pixel Mode (4 Data Pairs + Clock) PanelLink (3 Data Pairs + Clock), *3.12 = 4-22%LDITMDSTransition ComparisonTransition ComparisonOpen LDI has LESS transitions than TMDS! LDI minimizes transitions during blanking LDI has no encoding overhead TMDS only “minimizes” transitions during active data TMDS maximizes transitions during blankingData Bit Width vs. FrequencyData Bit Width vs. Frequency<1ns Bit WidthDanger Zone!TMDSLDILDI Single Pixel ModeLarger Bit Widths mean:Larger Bit Widths mean:Built in Bandwidth for tomorrow’s high-resolution panels More timing margin Standard cables Lower frequency signaling - lowers EMIUXGA ExampleUXGA ExampleLDI 162 MHz Clock 82 MHz cable clock Bit time is 1.764 ns Intra-pair skew limit is 300psTMDS 162 MHz Clock 162 MHz cable clock Bit time is 617 ps Intra-pair skew limit is 62ps (10% tbit D/S Spec) LDI data bit width is 285% larger than TMDS Divide by 7 vs by 10 Dual Pixel Interface (8 pairs) vs 3 pairs LDI Intra-pair skew tolerance is 4.8X TMDSLDI ConfigurationsLDI ConfigurationsTX ‘387RX ‘388Single / Dual / Dual Mode4 Data4 DataClockGraphics ControllerTo TCTX ‘387RX ‘388Dual / Dual / Dual Mode4 Data4 DataClockTo TCGraphics ControllerOther LDI ConfigurationsOther LDI ConfigurationsTX ‘387RX ‘388Single / Single / Single Mode4 DataClockV G ATo TCTX ‘387RXSingle(or Dual) / Dual / Dual Mode4 Data4 DataClockV G ATo TCRXClockPanel-Link ConfigurationsPanel-Link ConfigurationsTXRX3 DataClockV G ATo TCTXRX3 DataClockV G ATo TCTXRX3 DataClockV G ATo TCSingle / Single / Dual ModeDual / Single / Dual ModeSingle / Single / Single ModeStandard Twisted Pair Cables for LDIStandard Twisted Pair Cables for LDI 8 Data Pairs 1 CLK Pair 1 GND PairSingle Overall ShieldSimple Twisted PairShielded Twin-ax Cables for PanelLinkShielded Twin-ax Cables for PanelLink 3 Data Pairs 1 CLK Pair 1 GND Pair & 6 Shields!Overall ShieldShielded Twin-ax Pair (not twisted)Pair ShieldDrain Wire / Pair (AGND)Cable Loading EffectsCable Loading EffectsTMDSLVDSAll cables are low pass filers TMDS bits are smaller and are prone to ISI distortion LVDS bits are 285% larger, and pre-emphasis eliminates ISI distortion on long cables (10 meters)INOUTTMDS Driver & ReceiverTMDS Driver & ReceiverON/OFF Driver - sink onlyREXT sets VODREXT sets terminationAC Coupled I/F per VESA P&D Standard 2 Caps per pair 2-4 Resistors per pairLVDS Driver & ReceiverLVDS Driver & ReceiverTxRxCurrent returns within the pair (small loop area)Driver sets the common mode voltageReceiver support +/-1V VCM rangeDC Coupled, Single resistor terminationorPush Pull Current Mode DriverSilicon SourcesSilicon SourcesLVDS Sources TX & RX (FPD-Link) National Semiconductor Texas Instruments Thine others in development VGA+TX ATI Technologies others in development RX+TCON National Semiconductor othersTMDS Sources Silicon Image (Licensed by SiI) ATI (VGA+TX) others?Business IssuesBusiness IssuesTMDS - proprietary - encoding license required TX fee?? vs RX fee?? LVDS is an established Open Standard and is defined in: ANSI/TIA/EIA-644-1995 LDI - Not Encoded - No License required LDI is DC Balanced - Rules are Free Many suppliers offer LVDS technology todayLDI PinoutLDI Pinout18 Pair Cable 36 MDR Connector LDI (9 pairs) DDC (control) USB (optional) 2 grades of cable specified (twp)SummarySummarySupports QXGA (>5Gbps)Long, Low Cost CablesCompatible with NotebooksOpen Standard - No LicensesLDIYesYesYesYesTMDSNoNoNoNo