DS12B887

�Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS12B887 Real Time Clock DS12B887 080895 1/16 FEATURES • Drop-in replacement for IBM AT computer clock/cal- endar • Pin compatible with the MC146818B and DS1287 • Totally nonvolatile with over 10 years of operation in the absence of power • Self-contained subsystem includes lithium, quartz, and support circuitry • Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year com- pensation • Binary or BCD representation of time, calendar, and alarm • 12- or 24-hour clock with AM and PM in 12-hour mode • Daylight Savings Time option • Multiplex bus for pin efficiency • Interfaced with software as 128 RAM locations – 14 bytes of clock and control registers – 114 bytes of general purpose RAM • Programmable square wave output signal • Bus-compatible interrupt signals (IRQ) • Three interrupts are separately software-maskable and testable – Time-of-day alarm once/second to once/day – Periodic rates from 122 µs to 500 ms – End of clock update cycle PIN ASSIGNMENT 24 PIN ENCAPSULATED PACKAGE VCC SQW NC RCLR NC IRQ NC DS NC R/W AS CS NC NC NC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PIN DESCRIPTION AD0-AD7 – Multiplexed Address/Data Bus NC – No Connection CS – Chip Select AS – Address Strobe R/W – Read/Write Input DS – Data Strobe IRQ – Interrupt Request Output SQW – Square Wave Output VCC – +5 Volt Supply GND – Ground RCLR – RAM Clear DESCRIPTION The DS12B887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287A or DS12887A. The DS12B887 is identical in form, fit, and function to the DS1287A or DS12887A, with the excep- tion of RCLR, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. A lithium energy source, quartz crystal, and write-protection circuitry are contained within a 24-pin dual in-line package. As such, the DS12B887 is a complete subsystem replacing 16 components in a typical application. The functions include a nonvolatile time-of-day clock, an alarm, a one- hundred-year calendar, programmable interrupt, square wave generator, and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time-of-day and memory are maintained even in the absence of power. DS12B887 080895 2/16 OPERATION The block diagram in Figure 1 shows the pin connec- tions with the major internal functions of the DS12B887. The following paragraphs describe the function of each pin. BLOCK DIAGRAM DS12B887 Figure 1 USER RAM 114 BYTES CLOCK, CALENDAR, AND ALARM RAM REGISTERS A,B,C,D SQUARE WAVE OUT PERIODIC INTERRUPT/SQUARE WAVE SELECTOR OSC. POWER SWITCH AND WRITE PROTECT BUS INTERFACE CLOCK/ CALENDAR UPDATE BCD/ BINARY INCREMENT SQW IRQ DOUBLE BUFFERED ADO– AD7 AS DS R/W CS CS VCC POK VCC VBAT �8 �64 �64 RAM CLEAR LOGIC RCLR POWER-DOWN/POWER-UP CONSIDERATIONS The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS12B887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the system to stabilize after power is applied. When VCC falls below 4.25 volts, the chip select input is inter- nally forced to an inactive level regardless of the value of CS at the input pin. The DS12B887 is, therefore, write- protected. When the DS12B887 is in a write-protected state, all inputs are ignored and all outputs are in a high impedance state. When VCC falls below a level of approximately 3 volts, the external VCC supply is switched off and an internal lithium energy source sup- plies power to the Real Time Clock and the RAM memory. DS12B887 080895 3/16 SIGNAL DESCRIPTIONS GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts are applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to an inter- nal lithium energy source. The timekeeping function maintains an accuracy of ±1 minute per month at 25oC regardless of the voltage input on the VCC pin. SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts typical. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A tPI PERIODIC SQW OUTPUT RS3 RS2 RS1 RS0 tPI PERIODIC INTERRUPT RATE SQW OUTPUT FREQUENCY 0 0 0 0 None None 0 0 0 1 3.90625 ms 256 Hz 0 0 1 0 7.8125 ms 128 Hz 0 0 1 1 122.070 �s 8.192 kHz 0 1 0 0 244.141 �s 4.096 kHz 0 1 0 1 488.281 �s 2.048 kHz 0 1 1 0 976.5625 �s 1.024 kHz 0 1 1 1 1.953125 ms 512 Hz 1 0 0 0 3.90625 ms 256 Hz 1 0 0 1 7.8125 ms 128 Hz 1 0 1 0 15.625 ms 64 Hz 1 0 1 1 31.25 ms 32 Hz 1 1 0 0 62.5 ms 16 Hz 1 1 0 1 125 ms 8 Hz 1 1 1 0 250 ms 4 Hz 1 1 1 1 500 ms 2 Hz DS12B887 080895 4/16 AD0-AD7 (Multiplexed Bidirectional Address/Data Bus) - Multiplexed buses save pins because address information and data information time share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS12B887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ ALE, at which time the DS12B887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS12B887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high. AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS12B887. DS (Data Strobe or Read Input) - The DS pin is called Read(RD). RD identifies the time period when the DS12B887 drives the bus with read data. The RD signal is the same definition as the Output Enable (OE) signal on a typical memory. R/W (Read/Write Input)-The R/W signal is an active low signal called WR. In this mode the R/W pin has the same meaning as the Write Enable signal (WE) on generic RAMs. CS (Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the DS12B887 to be accessed. CS must be kept in the active state during RD and WR. Bus cycles which take place without asserting CS will latch addresses but no access will occur. When VCC is below 4.25 volts, the DS12B887 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outages. IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS12B887 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is pres- ent and the corresponding interrupt-enable bit is set. To clear the IRQ pin the processor program normally reads the C register. When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pull-up resistor. RCLR (RAM Clear) - The RCLR pin is used to clear (set to logic 1) all 114 bytes of general-purpose RAM but does not affect the RAM associated with the real time clock. In order to clear the RAM, RCLR must be forced to an input logic of (-0.3 to +0.8 volts) when VCC is ap- plied. The RCLR function is designed to be used via hu- man interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is in- ternally pulled up. Do not use an external pull-up resistor on this pin. ADDRESS MAP The address map of the DS12B887 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and four bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Registers C and D are read-only. 2. Bit 7 of Register A is read-only. 3. The high order bit of the seconds byte is read-only. The contents of four registers (A,B,C, and D) are described in the “Registers” section. DS12B887 080895 5/16 ADDRESS MAP DS12B887 Figure 2 0 00 13 14 0D 0E 14 BYTES 127 7F 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SECONDS SECONDS ALARM MINUTES MINUTES ALARM HOURS HOURS ALARM DAY OF THE WEEK DAY OF THE MONTH MONTH YEAR REGISTER A REGISTER B REGISTER C REGISTER D BI N AR Y O R BC D IN PU TS TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by read- ing the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten time, calendar, and alarm bytes can be either Binary or Binary-Coded Deci- mal (BCD) format. Before writing the internal time, cal- endar, and alarm registers, the SET bit in Register B should be written to a logic one to prevent updates from occurring while access is being attempted. In addition to writing the ten time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All ten time, calendar, and alarm bytes must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the ten data bytes. Table 2 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The 24-12 bit can- not be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar, and alarm bytes are always acces- sible because they are double buffered. Once per second the ten bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm inter- rupt is initiated at the specified time each day if the alarm enable bit is high . The second use condition is to insert a “don’t care” state in one or more of the three alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is gener- ated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three alarm bytes create an interrupt every second. DS12B887 080895 6/16 TIME, CALENDAR AND ALARM DATA MODES Table 2 ADDRESS FUNCTION DECIMAL RANGEADDRESS LOCATION FUNCTION DECIMAL RANGE BINARY DATA MODE BCD DATA MODE 0 Seconds 0-59 00-3B 00-59 1 Seconds Alarm 0-59 00-3B 00-59 2 Minutes 0-59 00-3B 00-59 3 Minutes Alarm 0-59 00-3B 00-59 4 Hours-12-hr Mode 1-12 01-0C AM, 81-8C PM 01-12AM,81-92PM Hours-24-hr Mode 0-23 00-17 00-23 5 Hours Alarm-12-hr 1-12 01-0C AM, 81-8C PM 01-12AM,81-92PM Hours Alarm-24-hr 0-23 00-17 00-23 6 Day of the Week Sunday = 1 1-7 01-07 01-07 7 Date of the Month 1-31 01-1F 01-31 8 Month 1-12 01-0C 01-12 9 Year 0-99 00-63 00-99 NONVOLATILE RAM The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the DS12B887. They can be used by the processor program as nonvol- atile memory and are fully available during the update cycle. INTERRUPTS The RTC plus RAM includes three separate, fully auto- matic sources of interrupt for a processor. The alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic interrupt can be selected for rates from 500 ms to 122 µs. The update-ended interrupt can be used to indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is described in greater detail in other sections of this text. The processor program can select which interrupts, if any, are going to be used. Three bits in Register B enable the interrupts. Writing a logic 1 to an interrupt- enable bit permits that interrupt to be initiated when the event occurs. A zero in an interrupt-enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set at an active level, although the interrupt initiating the event may have occurred much earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set inde- pendent of the state of the corresponding enable bit in Register B. The flag bit can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which software can interrogate as necessary. When a flag is set, an indica- tion is given to software that an interrupt event has occurred since the flag bit was last read; however, care should be taken when using the flag bits as they are cleared each time Register C is read. Double latching is included with Register C so that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no inter- rupts a re lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corre- sponding interrupt enable bit is also set, the IRQ pin is DS12B887 080895 7/16 asserted low. IRQ is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a one whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the DS12B887. The act of reading Register C clears all active flag bits and the IRQF bit. OSCILLATOR CONTROL BITS When the DS12B887 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium energy cell from being used until it is installed in a system. A pattern of 010 in bits 4 through 6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4 through 6 keep the oscilla- tor off. SQUARE WAVE OUTPUT SELECTION Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of Fig- ure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the SQW pin. The RS0-RS3 bits in Register A establish the square wave output frequency. These frequencies are listed in Table 1. The SQW frequency selection shares its 1-of-15 selector with the periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on and off under program control with the square wave enable bit (SQWE). PERIODIC INTERRUPT SELECTION The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once every 122 µs. This function is separate from the alarm inter- rupt which can be output from once per second to once per day. The periodic interrupt rate is selected using the same Register A bits which select the square wave fre- quency (see Table 1). Changing the Register A bits affects both the square wave frequency and the periodic interrupt output. However, each function has a separate enable bit in Register B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE bit in Register B. The periodic inter- rupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function. UPDATE CYCLE The DS12B887 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. How- ever, the time countdown chain continues to update the internal copy of the buffer. This feature allows time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar information is consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three positions. There are three methods that can handle access of the real time clock that avoid any possibility of accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an inter- rupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date information. If this interrupt is used, the IRQF bit in Reg- ister C should be cleared before leaving the interrupt routine. A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in prog- ress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244 µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will be changed. Therefore, the user should avoid interrupt service rou- tines that would cause the time needed to read valid time/calendar data to exceed 244 µs. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A i