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首页 数字集成电路设计

数字集成电路设计.doc

数字集成电路设计

曹鸿儒 2017-09-17 评分 0 浏览量 0 0 0 0 暂无简介 简介 举报

简介:本文档为《数字集成电路设计doc》,可适用于工程科技领域,主题内容包含数字集成电路设计IntroductionDesigningefficient,reliable,robustdigitalcircuitsrequi符等。

数字集成电路设计IntroductionDesigningefficient,reliable,robustdigitalcircuitsrequiresadherencetotheprinciplesofgooddesignpracticeForthemostparttheseareapplicableregardlessofwhethertheimplementationisdiscreteorcustomisedBadlydesigneddigitalcircuitryhasatendencytogeneratetiminghazardssuchasspikesandglitchesWhilstadesignmayexhibitcorrectfunctionalitymanyoftheproblemsassociatedwithpoorreliabilityareattributedtothewayinwhichthesehazardsarehandledItisvitallyimportantthatdesignsintendedforimplementationonASICsmustconformtoalltheacceptedrulesofbestpracticefordigitaldesignFailuretodosocanresultindesignsthatareunsafe,difficulttotestandwhoseoperationcannotbeguaranteedMaskprogrammabledevicesinparticulararehighriskwhenattemptingtoachievearightfirsttimedesignForthisreasonthesiliconfoundrywillinsistthatthedesignercompletesasignoffformindicatingcompliancewithallthefoundrydefinedrecommendationsIncaseswherenoncomplianceoccursthesemustbediscussedwiththefoundrydesigncentreandappropriateauthorisationobtainedbeforiseffectbycalculatingtheoverallpropagationdelayofacomponentwithreferencetoadditionaldelaydataasintheexamplebelowUnloadedTrackTotalLoadDelayUnitCellTypeTransitionDelayLoadsDelayDelayValueLoad(ns)(ns)(ns)(ns)INVERTERlowhighhighlowThesimulatorperformsthefollowingcalculation:TotalDelay(lowhigh)=Unloadeddelay(UnitLoadsxDelayUnitLoadsxLoads)TrackDelay=ns(xnsx)ns=nsTotalDelay(highlow)=ns(xnsx)ns=nsTheLoadValueindicatestheloadingeffectacomponentinputexertsontheoutputofanothercomponentfromwhichitisbeingdrivenTypicallyaninvertercircuitistakenasthereferencesinceitcomprisestheminimumnumberoftransistors(PMOSandNMOS)withtheinputsignalconnectedtothegatesofbothdevicesMorecomplexfunctionswillhavehigherloadvaluesForexampleanEXCLUSIVEORcomponentimplementingthefunctionA'BAB'asacomplexgatewillhavealoadvalueof,eachinputfeedingPMOSandNMOStransistorintheANDORstructureplusPMOSandNMOStransistorconfiguredasainvertertoprovidetheNOTfunctionThusintheexampleaninverterfeedssimilarcomponentssotheloadingisxIfitwerefeedingEXCLUSIVEORgatestheloadingwouldbexTheDelayUnitLoadisavalueprovidedbythesiliconfoundry,usuallyobtainedfromparametrictestingofcircuitsamplesTheLoadsfigureisobtainedfromtheschematicTheTrackDelayisobtainedafterlayouthasbeencompletedsowillnotbepresentindesignsimulationsbutwillbeincorporatedintoafinalpostlayoutsimulationThesimulatorwillindicatetheeffectofsignalloadingSomeCADsystemsimposealimitonthenumberofloadsthatcanbeconnectedtoasignalandcheckforthisduringthedesignprocessOthersleaveittothedesignerAgoodruleofthumbistolimitthenumberofloadstoNotonlywillthisminimisetiminghazardsbutwillalsoassisttherouterduringthelayoutprocesssinceashortlengthofinterconnectiseasiertoroutethanalongonebacktotopBufferingStrategiesToeliminateorminimisetheeffectsofsignalloading,designersshouldconsideranappropriatesignalbufferingstrategybothtoequalisetheloadandprovideincreaseddrivecapabilityNonRecommendedBufferingShownherearetwoexamplesofnonrecommendedbufferingInthelefthandexamplesomeclocklinesarebuffered,othersarenotClocksignalstravellingthroughthebufferedlineswillbedelayedrelativetothosethatarenotConsequentlysomeofthelogicelementsbeingfedfromthecircuitwillreceivetheclockbeforeothers,aneffectknownas'clockskew'IntherighthandexampleunequalloadinginthebufferingcircuitwillagainproducedifferentialdelaysintheclocklinesresultinginclockskewFigureNonRecommendedBufferingRecommendedBufferingAcorrectlydesignedbufferingcircuitwillprovidethesamedepthofbufferingineachlineandthesamefanoutonallbuffersThisisknownasBalancedTreeBufferingMoreover,inordertokeepsignaledgessharpbuffersmustbelightlyloadedThisarrangementisreferredtoasGeometricTreeBufferingNote,however,thatevenwhentheseprincipleshavebeenappliedatthecircuitdesignstage,thelayoutprocesscanproducedifferingtrackingcapacitanceswhichwillintroduceimbalanceintothefanoutForthisreasonisitessentialthatafinalpostlayoutsimulationthatincludestheseadditionaldelaysisperformedandthedesigntimingcheckedThecircuitbelowshowsanexampleofBalancedTreeBufferinginwhichallclocklinesareequallyloadedFigureRecommendedBufferingbacktotopSystemResetsDesignsimplementedonASICsarerequiredtobebroughttoaknownstatewithinagivennumberofclockcyclesThisisnecessarybothfornormaloperationwhereacircuithastobeinitialisedtoagivenstartingconditionandalsoduringtestingbeforeasequenceoftestpatternscanbeappliedTherecommendedmethodofachievingthisistoapplyanasynchronoussystemresettoallsequentialelementsinthecircuitRecommendedSystemResetHereanexternalsystemresetisappliedviaaninputpintotheresetinputsofallsequentialelementssothattheentirecircuitcanbeinitialisedsimultaneouslyTheresetsignalcanbeprovidedbyanexternalpoweroncircuitorresetbuttonorbothAlternativelysomeASICtopologiesprovideapoweronresetperipheralpadspecificallyforthispurposeWhenthisfacilityisusedaseparateresetmustalsobeincorporatedfortestpurposessinceitisusuallynecessarytoreinitialisethecircuitseveraltimesduringatestrunFigureRecommendedSystemResetbacktotopLocalResetsSynchronousdesignsarealwaysrecommendedforimplementationonASICsAnyasynchronousoperationimmediatelyincreasesthepotentialfortiminghazardsandmakestestingdifficultInsituationswheresectionsofsequentiallogicrequirealocalresetthisshouldalwaysbedonesynchronouslyNonRecommendedLocalResetThecircuitbelowdetailsacommontechniqueemployedtoasynchronouslyresetsequentialelementssuchascountersThecircuitviolatestherulesofsynchronousdesignThesecondflipflopcanchangestateatatimeotherthantheactiveclockedgeThereisalsoapotentialraceconditionbetweentheclockandtheresetofthisflipflopFigureNonRecommendedLocalResetNonRecommendedLocalResetSimilarproblemsoccurwhencombinationallogicisusedtogeneratearesetAcommonapplicationofthisdesignstyleistheuseofdecodinglogicontheoutputsofacounterTypicallyANDORgateswillbeusedtodetectarequiredstateinthecountingsequenceandprovideanasynchronousresetbacktothecounterresetinputsFigureNonRecommendedLocalResetRecommendedLocalResetTherecommendedalternativetoprovidingasynchronousresetstothesetypeofcircuitsistoclocktheflipfloptotherequiredzerostateThiseffectivelyproducesasynchronousresetInthiscircuitallflipflopsaresynchronisedtotheclockAresetrequiredonthesecondflipflopasaresultofsignalrgoingactivewillnowoccuronthenextrisingedgeoftheclockFigureRecommendedLocalResetbacktotopSystemClocksGreatcarehastobetakenwhenhandlingclocksinsequentialdesignsUnwantedspikes,glitches,clippedpulsewidthsandadditionalclockpulsesallprovidepotentialforcircuitfailureFeedingclocksintocombinationallogicforfurtherprocessingcausesnoendoftiminghazardsHerearetwoexamplesofthistechniqueNonRecommendedGatedClocksInthelefthandcircuittheintentionwasprobablytoinhibitenabletheclockTheensignal,however,arriveslateattheANDgateinputandtheresultisanunwantedglitchIntherighthandcircuittheintentionwastoswitchbetweenckandckThectrlsignaloccurringasitdoesclipsthebeginningofbothclocksresultingintwounwantedglitchesFigureNonRecommendedGatedClocksTherearemanymoreeffectsthatcanoccurdependingonthestateandtimingofthesignalsinvolvedFurthermoretheinclusionofcombinationalprocessinglogicaddsdelaytotheresultantsignalsresultinginvariableamountsofclockskewNowwehaveasituationwherethesequentialelementsinthecircuitarebeingclockedatdifferingtimesrelativetotheinitialmasterclockRecommendedGatedClocksIncircumstanceswhereclockshavetobegatedwithenablesignalstheuseofasequentialelementwithabuiltinenableinputisrecommendedIfthisisnotavailablethecircuitoppositeachievesthesamefunctionalityInthisarrangementthegatingfunctionpreviouslyprovidedbytheANDgateisnowimplementedbythemultiplexorThecircuit,however,isnowcompletelysynchronouswiththemasterclockfeedingdirectlyintotheflipflopWiththeenablesignalensetlowthecurrentstateoftheflipflopisretainedonarisingclockedgewithensethighnewdataisloadedFigureRecommendedGatedClocksbacktotopLocalClocksAswithresetsitispossibletogenerateasynchronousclocksignalsfromsectionsofsequentiallogicandthesecanviolatetheprinciplesofsynchronousdesignNonRecommendedLocalClocksAcommontechniqueincounterdesignistogenerateaclockfromtheoutputtransitionofanothersequentialelementThefollowingripplecounterprovidesanexampleinwhichageneratedclockfromonestageimplementsatogglefunctioninthenextThesecondflipflopisclockedonlywhenthefirstflipflopchangesfromalogictoalogicTherearetwoproblemswiththisarrangementThegeneratedclocktothesecondflipflopisskewedbytheclocktoqpropagationdelayofthefirstflipflopandalsothesecondflipflopcannotbeclockedoneveryedgeofthemasterclockAgainthiswillcauseproblemswithtestingmethodologiesFigureNonRecommendedLocalClocksRecommendedLocalClocksThecircuitbelowprovidestheequivalentfunctionAgainthecircuitisfullysynchronousWhenthetoggleinputislowtheflipflopretainsitscurrentstatewhenthetoggleinputishightheflipflopassumesitsoppositestateIncounterdesignthetoggleinputcanbeprovidedfromtheqoutputofthepreviousstageflipflopFigureNonRecommendedLocalClocksbacktotopClockingStrategiesWhenspeediscriticalinadigitalsystem,designersoftenresorttodubiousclockingstrategiesinanefforttomaximiseperformanceAnapparentlyattractivetechniqueforincreasingtherateofdatathroughputinacircuitisthatofDoubleEdgedClockinginwhichflipflopsinacircuitcanbeclockedoneithertherisingorfallingedgeoftheclockNonRecommendedStrategyThecircuitbelowshowsafirstflipflopactivatedbythetrueversionoftheclockwhilstaninverterfeedsasecondflipflopelsewhereinthecircuitwithaninvertedversionBothdevicesaresensitivetorisingclockedgesbuttheoveralleffectistoclockthefirstflipflopatthebeginningoftheclockpulseandthesecondattheendFigureNonRecommendedStrategyTheproblemswithemployingthiskindoftechniquerelatetosynchronousresetting,setupandholdtimeviolations,determinationofcriticalpathsandimplementationoftestmethodologiesSynchronousresetting(iewhereflipflopsareresetonthecoincidentoccurrenceofaclockedgeandaresetsignal)isimpossiblesincenotalldevicesareclockedonthesameedgeSetuptimes(iethetimebeforeaclockedgethatdatahastobepresent)andholdtimes(iethetimeafteraclockedgethatdatahastoremain)areindangerofbeingviolatedastimingbecomesfinelytunedCriticaldelaypathsthroughthecircuitaredifficulttoassesswithmultipletimingregimespresentTestmethodologiessuchasscanpathinwhichpatternsareinsertedintoacircuitviaitsflipflopelementsareimpossibleagainbecauseallflipflopshavetobeclockedatthesametimeIngeneralthistechniquerarelyworkswellinadesignAttemptsto'borrowtime'inonepartofacircuitoftenresultincomplicationsoccurringsomewhereelseAbettersolutionistouseasingleedgedclockingschemewithahigherclockfrequencyNonRecommendedStrategySimilarproblemsoccurwhendoubleedgedclockingtechniquesareusedinmoreformaldesignarrangementsThiscircuitdetailsapipelinedstructureinwhichdatafromafirststoragelevelisprocessedbycombinationallogicforsubsequenttransmissiontoasecondstoragelevelThearrangementsuggestsadesignthatisvery'edgy'Anyincrease,forexampleinthepropagationdelaysofthecombinationallogic,couldresultincircuitfailureFigureNonRecommendedStrategyRecommendedStrategyAgainabettersolutionistorevertbacktoasingleedgedclockingschemeasshownoppositeThecircuitisclockedattwicethefrequencyofthedoubleedgedversiontoachievethesamethroughputFigureRecommendedStrategybacktotopDelayCircuitsDigitaldesignersoftenutiliselogiccomponentssuchasinvertersandbufferstoachievesomerequireddelayandassumethatthiscanbedoneonASICsExamplesincludetheaddingofdelaysincombinationalcircuitrytoequalisepropagationdelaysandremoveglitchesorthedelayingofaclockedgetoaflipflopinordertoallowmoretimeforthedatainputtosettleItisalsotemptingtotryandreproducethefunctionalityofpulsegenerators,monostablesandmultivibratorsonsiliconusingdelayelementsThesepracticesarenotgenerallyrecommendedThedelayofanylogiccomponentonanASICcannotbeguaranteedItwillvarywithtemperature,powersupplyvoltageanddifferentfabricationrunsLogicsimulatorsenabletheeffectsofthesevariationstobeobservedbyallowingthesimulationtobeimplementedatminimum,typicalandmaximumoperatingconditionsTypicalreferstonominaloperatingtemperatureandpowersupplyvoltageMinimumwillmultiplyallthecomponentdelaysonthechipbyascalingfactorofaroundtodefinetheshortestcircuitdelayswhilstmaximumwilluseafactorofaroundtodefinethelongestdelaysInthiswaythedesignercantolerancethecircuitovertheentireoperatingrangeofthefabricationprocessAgooddesignwillbestablethroughoutAbaddesignthatpassedasimulationundertypicalconditionsislikelytofailatthispointwhenthevariabledelaysmovetiminghazardsintocontentionNonRecommendedPulseGeneratorThecircuitbelowusesinverterstoimplementadelayontheInputTriggersignalThesettledstatewiththissignalsetlowproducesalogiconthetopinputtotheANDgate,alogiconthebottominputandalogiconthePulseoutputWhentheInputTriggergoeshighbothinputstotheANDgatewillbemomentarilyhigh,producingalogiconthePulseoutputAfteratimeequaltothepropagationdelayofthedelaylinethetopinputoftheANDgatewillgolowandthepulseisterminatedThemainproblemwiththiscircuitisthatvariationsintheinverterdelayspreviouslydescribedwillaffectthewidthoftheoutputpulseandthiscannotnowbeconsistentlyguaranteedFigureNonRecommendedPulseGeneratorNonRecommendedPulseGeneratorHerethedelaycomponentsareusedinthefeedbackpathofaflipfloptocontrolanactivelowresetinputInthestablestatetheflipflopwillberesetandthePulsesignalwillbesetlowUpontheapplicationofapositivegoingclockedgetheqoutputoftheflipflopwillassumethelogicstate,settingthePulsesignalhighTheqboutputwillassumethelogicstateThiswillultimatelypropagatethroughtheinvertersresettingtheflipflopandproducingapulseontheqoutputequalinwidthtothedelaythroughthedelaycomponentsAsinthepreviouscircuittheproblemwiththiskindofarrangementisthedifficultyinmaintainingaconsistentpulsewidthwithvaryingcomponentdelaysFigureNonRecommendedPulseGeneratorTherearealsofundamentaldesigndeficiencieswiththecircuitThereisnoindependentexternalresettotheflipflopsotheinitialstateoftheoutputatswitchonisunpredictableItcouldbealogicoritcouldbealogicThecircuitcanneitherbesimulatedduringthedesignphasenortestedduringmanufactureThesimulatorwillnotbeabletopredictthestateoftheoutputattimet=(ieatpoweron)andwilldisplaythisasindeterminateThisconditionwillbepropagatedthroughouttheentiresimulationsincethesimulatorrequiresaknowninitialstatetopredictallsubsequentstatesLikewiseatesterwillrequireallflipflopstobesettoaknowninitialstatebeforethetestpatternsareappliedsothatthecomparisonbetweenexpectedandcapturedoutputvaluesisvalidAdesignsignoffatthefoundrycannotthereforetakeplaceInpractice,however,thecircuitwillassumeastablestateonpoweronShouldthePulseoutputbealogictheqboutputoftheflipflopwillbealogic,theresetfeedbacksignalrwillbeaninactivelogicandtheflipflopwillremaininitspresentstateIfontheotherhandthePulseoutputisalogiconpowerup,rwillultimatelysettletoalogicaftertheqbhaspropagatedthroughthedelayline,theflipflopwillresetandthePulseoutputwillassumealogicTwoeffectsrelatingtotheoperationofthecircuitshouldbenotedFirstly,ifthepoweronconditionisthissecondcase(thePulseoutputisalogiconpowerup)anegativegoingedgewillbegeneratedonthePulseoutputThiscouldbeseriousifthissignalisbeingusedasaclocktosomeothersequentiallogicSecondlysincethecircuithasnoresetthatcouldbeappliedexternallyfromapinonthechip(egfromasystemresetbuttonorpowerupcircuit)thereisnowayofreinitialisingthedesignshouldithangupduringoperationNonRecommendedMultivibratorThiscircuitusesadelaylinetoproduceaseriesofpulsescontrolledbyatriggerinputThestablestateiswhentheTriggersignalislow,thetopinputtotheANDgateishighandtheoutputisalogicWhentheTriggerinputgoeshightheoutputwillgomomentarilytoalogicuntilthisvalueworksitswaythroughthedelaylinetoproducealogiconthetopinputoftheANDgateandthepulseterminatesThewholecyclerepeatsitselfforaslongastheTriggersignalisactiveAgaintheproblemwiththiscircuitisthewidthofthemonostablepulsesandtheirproportionalitytotheinverterdelaysFigureNonRecommendedMultivibratorRecommendedPulseGeneratorThefollowingcircuitutilisessynchronoustechniquestoensureaconsistentpulsewidthsynchronisedtotheclockperiodAssumingthataresethasoccurred,theqoutputofthefirstflipwillbelogicwhilsttheqboutputofthesecondflipflopwillbelogicandthepulseoutputfromtheANDgatewillbelowWhenthetriggerinputishighandarisingedgeoccursontheclockinputck,thefirstflipflopwillgohighwhilstthesecondwilltakeonthestateofthefirstbeforetheclockedgeoccurrediealogicHenceitsqboutputwillbelogicandwithbothinputsoftheANDgateatthisvalueitspulseoutputwillgohighOnthenextrisingedgeoftheclockifthetriginputisnowlowthefirstflipwillgolow,thesecondwillsethighwithitsqboutputlowandthepulseoutputoftheANDgatereturnstologicFigureRecommendedPulseGeneratorbacktotopSpikesandGlitchesManydesignersviewingsimulationoutputresultsforthefirsttimearehorrifiedtoseespikesandglitchesinwaveformsEvenafteradherencetotheprinciplesofbestpracticetherewillstillbemanyoccasionswhenthesehazardsoccurEachtimealogiccircuitisclocked,anewstateisdefinedandthiswillrequiretimetosettleasthevariouspropagationdelaysthroughthelogicexpireDuringthisunstableperiodtherecouldbeallmannerofhazardsTheprinciplesofsynchronousdesignaredevisedsuchthatnoneofthisactivityiscoincidentwithaclockedgeandcannotthereforeaffecttheintendedoperationofthecircuitFigureSpikesandGlitchesCircuitInstabilityApositivegoingedgeonaclocksignalcausesachangeinthevalueofacountsignalsomewhereinthecircuitAfteraninitialdelaytwhenthecircuitdpropagationdelaysstarttotakeeffectthissignalwillbegintochangeTherethenfollowsaperiodofinstabilityuntilallpropagationdelayshaveexpiredNoneofthisinstabilitycaneffecttheoperationofthecircuitsinceitoccursaftertheclockedgeThesignalremainsinastablestateforaperiodoftimetuntilthenextclockedge,afterwhichanotherchangeofstateoccurssTwoconditionsarerelevanttothesuccessfuloperationofthisarrangement)AsignalbeingfedtothedatainputofaflipflopmustbesettledbeforetheSetupTimeoftheflipflopAnychangeafterthistimecanstoreanincorrectvalue)AsignalbeingfedbackfromtheoutputofaflipflopdirectlyorthroughlogictoitsinputmustnotchangestatewithintheHoldTimeoftheflipflopIfthisoccursthenewvaluewilloverwritethecurrentvaluebacktotopLevelandEdgeTriggeredDevicesHazardsindigitalcircuitscanalsobegeneratedandpropagatedbythewrongchoiceofflipflopsInmostcasesthisrelatestotheuseofleveltriggeredratherthanedgetriggereddevicesInaleveltriggeredflipflopthestateofthedatainputiscapturedthroughoutthewholetimetheclockisactiveFigureLevelandEdgeTriggeredDevicesGeneratedHazardThecircuitbelowdetailsaleveltriggereddeviceutilisedinafeedbackloopThisisacommonarrangementinprocessordesignwhere,forexample,aregistermayfeedintoanadderandbacktoitselfWhentheclockinputgoesactivethecombinationallogicprocessesthestateoftheflipflopoutputandfeedsbackanewvaluetothedatainputIfthisnewvalueisdifferentfromtheoldvaluetheflipflopchangesstate,presentingthisnewvaluetothecombinationallogicforfurtherprocessingThewholeactivityrepeatsitselfcontinuallyuntiltheclockinputgoesinactive,generatinganoscillatingsignalknownasaRaceConditionFigureGeneratedHazardPropagatedHazardInthiscircuitaleveltriggereddeviceisusedtocapturedatafromtheoutputofcombinationallogicwhichhasgeneratedhazardsduetovaryingpropagationdelaysinitscircuitryWhentheclockinputgoesactivethecurrentstateoftheflipflopdatainputiscapturedandpresentedtotheoutputSometimelaterthedatainputchangestoanewvalueandagainthisistransmittedtotheoutputDuringthetimethattheclockisactivetheflipflopisperformingthefunctionofaTransparentLatchwherebyanychangeininputvalueisimmediatelytransferredtotheoutputInthiswayanunstableinputsignalpresentedtotheflipflopwillbepropagatedtoothercircuitryfedbyitsoutputBothofthesetypesofhazardcanbeeliminatedbyreplacingtheleveltriggereddeviceswithedgetriggereddevicesNowtheinputdatawillbecapturedonlyonaclockedgesoanyvariationinthedatainputofthedevicewillnotbetransmittedtotheoutputAsageneralruleitisalwayswisesttouseedgetriggereddevicesinsynchronousdesignsTypicallyleveltriggeredschematicsymbolsarecharacterisedbyhavingaboxadjacenttotheclockpinwhilstedgetriggereddevicesemployachevronbacktotopSummaryThefollowingsummarisestherulesofbestpracticefordigitaldesign,Keepdesignssynchronous,Useedgetriggereddevices,Tieoffallunusedinputs,Avoidtheuseofcomponentsasdelays,Avoidgatingclocks,Avoiddoubleedgeclockingstrategies,Alwaysprovideasystemreset,Powerupheavilyloadedandcriticalsignals,Simulaterigorouslybeforeandafterlayout,AdheretotheASICfoundry'srecommendation
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