D触发器波形仿真

D触发器波形仿真 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity shiyan3 is Port ( d : in  STD_LOGIC; cp : in  STD_LOGIC; q : out  STD_LOGIC; qb : out  STD_LOGIC); end shiyan3; architecture shiyan3 of shiyan3 is begin process(cp,d) begin if cp='0' and cp'event then q<=d; qb<=not d; end if; end process; end shiyan3; r RS触发器仿真波形 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY  shiyan32  IS PORT  (r,s,en:    IN BIT ;  q,qb:    BUFFER BIT); END  shiyan32; ARCHITECTURE  shiyan32 OF  shiyan32  IS SIGNAL s1,r1:  BIT; BEGIN s1<=s  NAND en; r1<= r  NAND en; qb<=r1 NAND q; q<=s1 NAND qb; END shiyan32; 8线—3线编码器仿真波形 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity vhdlthree is port (A0,A1,A2,A3,A4,A5,A6,A7,EN:in std_logic; Y0,Y1,Y2,G1,G2:out std_logic ); end; architecture vhdlthree of vhdlthree is begin Y0<=NOT(((NOT EN)AND(NOT A7))OR((NOT EN)AND A6 AND(NOT A5))OR((NOT EN)AND A6 AND A4 AND(NOT A3))OR((NOT EN)AND A6 AND A4 AND A2 AND(NOT A1))); Y1<=NOT(((NOT EN)AND(NOT A7))OR((NOT EN)AND(NOT A6))OR((NOT EN)AND A5 AND A4 AND(NOT A3))OR((NOT EN)AND A5 AND A4 AND(NOT A2))); Y2<=NOT(((NOT EN)AND(NOT A7))OR((NOT EN)AND(NOT A6))OR((NOT EN)AND(NOT A5))OR((NOT EN)AND(NOT A4))); G2<=EN OR (A7 AND A6 AND A5 AND A4 AND A3 AND A2 AND A1 AND A0); G1<=EN OR NOT(A7 AND A6 AND A5 AND A4 AND A3 AND A2 AND A1 AND A0); end vhdlthree; 3线-8线译码器波形仿真 library ieee; use ieee.std_logic_1164.all; ENTITY shiyan51 IS PORT ( num : IN STD_LOGIC_VECTOR (2 DOWNTO 0 ) ; Code_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0 )) ; END; ARCHITECTURE shiyan51 OF shiyan51 IS BEGIN WITH num SELECT Code_out<="11111110" WHEN "000", "11111101" WHEN "001",  "11111011" WHEN "010", "11110111" WHEN "011", "11101111" WHEN "100", "11011111" WHEN "101", "10111111" WHEN "110", "01111111" WHEN "111", "XXXXXXXX" WHEN OTHERS ; end shiyan51; 六D触发器波形仿真 library ieee; use ieee.std_logic_1164.all; entity shiyan is PORT (d0, d1, d2, d3,d4,d5,cd,clk:in  STD_LOGIC; q0,q1,q2,q3,q4,q5:out  STD_LOGIC); end shiyan; architecture shiyan of shiyan is begin process(d0,d1,d2,d3,d4,d5,clk,cd) begin if cd='0' then q0<='0';q1<='0';q2<='0';q3<='0';q4<='0';q5<='0'; elsif clk='0' and clk'event then q0<=d0;q1<=d1;q2<=d2;q3<=d3;q4<=d4;q5<=d5; end  if; end process; end shiyan; 数码显示扫描电路波形仿真 library ieee; use ieee.std_logic_1164.all; entity shiyan7 is PORT ( num : IN STD_LOGIC_VECTOR (3 DOWNTO 0 ) ; Code_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0 )) ; end shiyan7; architecture shiyan7 of shiyan7 is begin WITH num SELECT Code_out <= "11111100" WHEN "0000", "01100000" WHEN "0001",  "11011010" WHEN "0010", "11110010" WHEN "0011", "01100110" WHEN "0100", "10110110" WHEN "0101", "10111110" WHEN "0110", "11100000" WHEN "0111", "11111110" WHEN "1000", "11110110" WHEN "1001", "XXXXXXXX" WHEN OTHERS ; end shiyan7; 四位二进制加法计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity add is port (CLK,LD,RD,EP,ET :in  STD_LOGIC; D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO : OUT STD_LOGIC); end; architecture add of add is begin PROCESS(RD,CLK,LD) BEGIN IF RD='0' THEN  Q<="0000" ;  CO <= '0'; ELSIF LD = '0' AND (CLK='1' AND CLK'EVENT)  THEN  Q <= D;  CO <='0'; ELSIF ET='1' AND EP='1' AND (CLK'EVENT AND CLK='1') THEN IF Q="1111" THEN CO<='1';Q<="0000"; ELSE Q<=Q+1; END IF; ELSIF EP='0' THEN CO<='0'; --ELSE Q<="1111"; END IF; END PROCESS; end add;