Compact Modeling of Stress Effects in Scaled CMOS

Compact Modeling of Stress Effects in Scaled CMOS Chi-Chao Wang, Wei Zhao, Frank Liu*, Min Chen, and Yu Cao Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 *IBM Austin Research Laboratory, Austin, TX 78758 Email: cwang73@asu.edu Abstract — Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically captures these behaviors is developed for circuit simulation with strained CMOS technology. Keywords — Layout Dependence, Stress Effect, Compact Modeling, Mobility, Threshold Voltage I. INTRODUCTION Strain technology, which alters band structure and reduces effective mass and scattering rate, is essential to elevate carrier mobility for continual scaling. The exact amount of mobility enhancement depends on both the applied stress level during the fabrication (for example, determined by the Ge composition for eSiGe technology) and circuit layout parameters, such as transistor length and source/drain size [1], because of the non-uniform stress distribution in the channel region. Such non-uniformity results in pronounced shifts in transistor and circuit performance. To capture such a systematic effect, traditional efforts resort to TCAD simulation to extract the stress level from the entire layout and analyze performance enhancement [2]. This approach is usually expensive in computation. Therefore, it is necessary to develop a more effective modeling approach that is able to extract the stress effect for each device and embed it into standard model parameters for circuit simulation. The layout-dependent stress effect is first observed and reported from STI stress [3]. Layout-dependent models regarding STI stress are proposed on the basis of the experimental observation that the changes of drive current and threshold voltage follow the trend of the length of oxide definition area (LOD) [4] [5]. Moreover, a modeling approach of equivalent stress level is proposed to account for the mobility enhancement with an assumption that the mobility enhancement is proportional to the applied stress [6]. However, this approach also results in empirical fitting. In this work, a new general modeling approach is proposed to capture the layout-dependent stress effect. This model is derived from the first principle and physically captures the impact of circuit layout on transistor performance such that model scalability is guaranteed for future technology generations. II. COMPACT STRESS MODELING A. Bathtub Curve of Stress Distribution As investigated in [7], the stress magnitude in Si substrate decays sharply from the edge of the channel to the center, and becomes less dependent on the distance when the location is far from the origin of the applied stress. Figure 1 (a) shows the simulated stress contour of a PMOS with SiGe stressors in source/drain area, illustrating that the stress is imposed from the source/drain area and results in the non-uniform distribution [8]. In Fig. 1 (b), the simulation shows the stress profiles for devices with different channel lengths: the shorter the channel length, the higher overall stress level. Although the stress magnitude is different, the stress profile is similar and behaves like a bathtub curve. Based on this observation, without losing the generality, a linear piecewise approximation is proposed to capture the stress profile as Eqs. (1)-(3), dxY P −= σ1 (1) BY σ=2 (2) )(3 LxdY P −+= σ (3) where σP and σB denote the peak and bottom stress levels in the channel, respectively, and d represents the slope. Moreover, Figure 1. Modeling of stress distribution. 0 20 40 60 80 100 120 140 0.8 1.2 1.6 2.0 2.4 Position along the channel (nm) L=40nm L=90nm L=140nm X 0 Y 3 =σ P +d(x-L) X 1 Y 2 =σ B S tr e s s L e v e l (G P a ) Y 1 =σ P -dx L sd =200nm Model Si 0.75 Ge 0.25 (a) Stress contour of a MOSFET with eSiGe in S/D area. (b) Bathtub curve approximation for stress distribution. 310 -270 -1050 -1740 StressXX Linear (MPa) 978-1-4244-3947-8/09/$25.00 ©2009 IEEE 131 Y1 and Y3 intercept with Y2 at points of x0 and x1, respectively. x0 and x1 are expressed by Eqs. (4) and (5). d x BP σσ −=0 (4) d Lx BP σσ −−=1 (5) The stress distribution in the channel is sensitive to some layout parameters and thus results in additional variations in device performance [1]. In Fig. 2, as S/D diffusion length (Lsd) increases, σP and σB become higher due to the increased amount of stressor material, and finally reaches the saturation state when Lsd is larger than the critical length [1]. Meanwhile, the stress for the device with smaller channel length is higher than that with larger channel length. To account for the stress dependence on L and Lsd, σP is modeled as Eq. (6), where σm is the saturation stress level and A and m are fitting parameters accounting for the dependence on Lsd and the stress decreasing rate over distance from neighboring transistors. m sd sd sdsd P LA L LL m LL m L m σσ ⋅ + ⋅⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ + + + ++= 2 1 (6) Each term in the parenthesis represents the contribution by a diffusion region, depending on their separation distance to the channel. The first two terms in Eq. (6) account for the contribution from the source/drain area of the target transistor, while the rest two terms represent the stress sources from the nearest neighboring transistors. Moreover, Eq. (6) assumes that all diffusion regions in the neighboring transistors have the same size Lsd. If they are different, the exact value should be used to replace the corresponding Lsd. On the other hand, as channel length becomes shorter, σB grows up and to the limit of σP when channel length reaches zero. This channel length dependence can be modeled by Eq. (7) with a fitting parameter C. In Fig. 2, the models show good agreement with TCAD simulation results. pB LC C σσ ⋅ + = (7) B. Equivalent Mobility (µe) in the Channel When the stress is applied, the band structure is altered and further changes the symmetrical ellipsoids of constant energy of silicon. This results in carrier redistribution and reduce carrier effective mass and scattering rate; then carrier mobility is enhanced. Based on strain-induced band splitting, the model regarding strain-induced mobility change is physically modeled with the form as Eq. (8), ⎥⎦ ⎤⎢⎣ ⎡ − Δ ⋅+= 1)exp(1 0 kT EB μ μ (8) where the coefficient, B, is a physical constant [9] [10]. ∆E denotes the strain-induced energy splitting of conduction band or valence band and can be calculated by the deformation potential theory [11], which indicates the applied stress level is linearly proportional to energy splitting. Therefore, energy splitting is modeled by Eq. (9). σ⋅=Δ PE (9) where P can be calculated by deformation potential constants, and it is also temperature dependent because the temperature variation alters the bandgap and further affects the energy band splitting. Therefore, the temperature-dependent behavior can be modeled as Eq. (10), α ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ ⋅= 0 0)( T TPTP (10) where P0 denotes its value at room temperature (T0) and α is a fitting parameter accounting for the temperature dependence. Moreover, since the stress level in the channel is not a constant, the enhancement in mobility is also non-uniformly distributed. Based on the principle of current continuity, the non-uniform mobility can be modeled as an equivalent mobility, µe, by using Eq. (11), [12] dx L L o e o ∫= 01 μμμμ (11) where µ0 denotes the unstrained mobility. Therefore, an analytical solution for mobility can be derived as function of channel length and S/D diffusion length to bridge the layout parameters to mobility variation, as expressed in Eq. (12). ⎪⎪⎭ ⎪⎪⎬ ⎫ ⎪⎪⎩ ⎪⎪⎨ ⎧ ⎥⎥ ⎥⎥ ⎦ ⎤ ⎢⎢ ⎢⎢ ⎣ ⎡ ⎟⎟⎠ ⎞⎜⎜⎝ ⎛ −⎟⎠ ⎞⎜⎝ ⎛ − + ⎟⎠ ⎞⎜⎝ ⎛ −⎟⎠ ⎞⎜⎝ ⎛ + + − ⋅ − = 1exp1 1exp1 ln )1( 2 0 00 kT dPxPB kT PB kT dPx BdPL kT P P e σ σ μ μ ⎥⎦ ⎤⎢⎣ ⎡ ⎟⎟⎠ ⎞⎜⎜⎝ ⎛ +−⋅ − + kT P BBL xL Bσexp1 2 0 (12) In Fig. 3, TCAD simulation shows the amount of mobility enhancement is strongly dependent on channel length and S/D diffusion length; as channel length becomes shorter, the stress effect becomes more effective. Meanwhile, with a larger Lsd, the mobility enhancement is stronger. This dependence is captured by the new model well. 0 100 200 300 400 500 0.0 1.5 3.0 4.5 L=150nm S tr e s s l e v e l (G P a ) Lsd (nm) Peak stress Bottom stress Model L=30nm PMOS w/ eSiGe 2 neighboring transistors Figure 2. Layout dependence is modeled through σP and σB in Eqs. (6) and (7). 978-1-4244-3947-8/09/$25.00 ©2009 IEEE 132 On the other hand, to assess the temperature effect, the device is operated at different temperatures from 100K to 800K. In Fig. 4, TCAD simulation shows that at 100K, the mobility enhancement increases 31% more than that at room temperature for the device with both L and Lsd at 100nm. On the contrary, as temperature increases more than the room temperature, the mobility enhancement declines. The sensitivity of mobility enhancement to temperature is higher at lower temperatures. This behavior can be explained by Eq. (8), where the temperature term is in the exponential function, so that the change is more dramatic under low temperatures. Moreover, the device with longer channel length is less sensitive to the temperature variation. The proposed model demonstrates the good agreement with TCAD simulation. C. Strain Induced Threshold Voltage Shift In addition to strain-induced mobility variation, strain- induced threshold voltage shift is also observed in the strained devices. The change in threshold voltage is attributed to strain- induced variation of energy bandgap, electron affinity, and density of states (DOS), where the effect of density of states (DOS) can be ignored due to its insignificant impact [13]. Based on the deformation potential theory [11], the strain- induced change in bandgap and electron affinity is proportional to the applied stress magnitude, so the threshold voltage change is modeled by Eq. (13), BBth STRVTHV σσ ⋅=Δ _)( (13) where VTH_STR is a fitting parameter to capture the linear relationship between threshold voltage shift and the applied stress magnitude. Note that the bottom stress level (σB) is chosen for threshold voltage shift because the barrier peak between source and substrate is controlled by σB, as shown the stress bathtub curve in Fig. 5. The simulated valence bands of unstrained/strained PMOSFETs indicate that Vbi is lowered by stress effect and thus it becomes easier for holes to pass through the channel. This lowering valence band confirms the strain-induced threshold shift. In Fig. 6, TCAD simulation based on eSiGe technology shows that the strain-induced Vth shift has strong dependence on the channel length and source/drain diffusion length; the strain induced ΔVth increases as L decreases, and meanwhile the lower ΔVth is observed for a smaller Lsd due to less S/D stressors. This dependence is captured well by Eq. (13). Figure 3. Layout dependence of channel mobility. 100 1000 1.0 1.2 1.4 1.6 1.8 2.0 Strained PMOS w/ S/D Si 0.8 Ge 0.2 T=300 K L sd =50 nmμ/ μ 0 L (nm) TCAD Model L sd =100 nm 60 80 100 120 140 160 180 200 1.5 1.0 0.5 0.0 -0.5 -1.0 σ P σ P V bi DrainChannel V DS =0 V V a le n c e B a n d ( V ) Channel Position (nm) Strained Unstrained V DS =-1V DIBL Source σ B Bathtub stress approximation PMOS Figure 5. Simulated Valence band diagram for unstrained/ strained PMOS under different drain biases. Figure 6. Strained induced ΔVth as a function of channel length (L) and S/D diffusion length (Lsd). 10 100 1000 0.00 0.02 0.04 0.06 0.08 L sd =50nm | ΔV th | (V ) L (nm) TCAD Model L sd =100nm Strained PMOS w/ S/D Si 0.8 Ge 0.2 BBth STRVTHV σσ ⋅=Δ _)( Figure 4. Temperature dependence of mobility. 0 100 200 300 400 500 600 700 800 900 1.0 1.5 2.0 2.5 3.0 3.5 Strained PMOS w/ S/D Si 0.8 Ge 0.2 L=100 nm L=200 nm L=100 nm L=200 nm Model Temperature μ/ μ o L sd =130 nm -40 -20 0 20 40 M o b ility V a ria tio n (% ) 978-1-4244-3947-8/09/$25.00 ©2009 IEEE 133 D. Other Secondary Effects The effect of drain induced barrier lowering (DIBL) becomes more important as channel keeps scaling. To the first order, the DIBL-induced threshold voltage shift can be modeled as Eq. (14) [14], [ ] lLdsBbith eVVDIBLV −+−≈Δ )2(3)( φ (14) where l denotes the characteristic length for DIBL effect. Vbi is the energy barrier between source and substrate and ΦB is the bulk potential with expressions in Eqs. (15)-(16), ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ = 2ln)( i SUBSOURCE pbi n NN q kTV σ (15) ⎟⎟⎠ ⎞ ⎜⎜⎝ ⎛ = i SUB B n N q kT lnφ (16) where NSOURCE and NSUB are the doping concentrations in source and substrate. Vbi and ΦB are important factors to DIBL effect. Moreover, applying stress affects the intrinsic carrier density (ni), which is an exponential function of bandgap, and further makes impact on Vbi and ΦB. However, in Eq. (14), the term of (Vbi-2ΦB) is independent of ni, indicating the impacts of stress on Vbi and ΦB cancel each other for DIBL effect. On the other hand, stress alters ΦB and further influences the depletion depth (Xdep), shown in Eq. (17), which further affects DIBL and subthreshold swing through Eqs. (18) and (19), respectively. SUB BSBsi dep qN VX )2(2 −= φε (17) ( )413 gdepox EXTl ∝= (18) )1(60.. ox dep C C mVSS +⋅= (19) Note that the characteristic length (l) in DIBL effect is the major term to be impacted by stress and is proportional to Eg1/4, making DIBL relatively insensitive to the stress effect. In Fig. 7, our model captures strain-induced ∆Vth in strained devices operated under different drain biases as well. III. CONCLUSION With the scaling of device dimension, the strain-induced mobility and threshold voltage variation becomes more pronounced. Therefore, it is essential to develop compact models of the layout dependent stress effect for circuit analysis and optimization. In this work, the solution that bridges layout parameters to device electrical characteristics is proposed for simulation. IV. ACKNOWLEDGEMENT The authors would like to acknowledge the support of the Focus Center for Materials, Structures, and Devices (MSD), as well as Center for Circuits & System Solutions (C2S2), two of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program. REFERENCES [1] G. Eneman, et al., “Scalability of the Si1-xGex Source/Drain technology for the 45-nm technology node and beyond,” TED, vol. 53, no. 7, pp.1647-1656, Jul. 2006. [2] V. Moroz, et al., “The impact of layout on stress-enhanced transistor performance,” pp. 143-146, SISPAD 2005. [3] G. Scott, et al., “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., 1999, pp. 827-830. [4] R.A. Bianchi, et al., “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” IEDM, pp.117-120, 2002. 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Payet, et al., “Nonuniform mobility-enhancement techniques and their impact on device performance,” TED, vol. 55, no. 4, pp. 1050-1057, April 2008 [13] W. Zhang, et al., “On the threshold voltage of strained-Si– Si1-xGex MOSFETs,” TED, Vol. 52, no. 2, pp.263-268, Feb. 2005. [14] Z.-H. Liu, et al., “Threshold voltage model for deep- submicrometer MOSFET’s,” TED, vol. 40, no. 1, pp. 86-95, Jan. 1993. Figure 7. Threshold voltage for strained/unstrained devices under different drain biases. 20 40 60 80 100 120 0.2 0.3 0.4 0.5 0.6 0.7 Unstrained |V th | (V ) L (nm) TCAD VDS=-0.1V TCAD VDS=-1V Model Strained 978-1-4244-3947-8/09/$25.00 ©2009 IEEE 134