UNDERSTANDING POWER FACTOR

APPLICATION NOTE UNDERSTANDING POWER FACTOR by L. Wuidart IF YOU THINK THAT POWER FACTOR IS ONLY COS ϕ, THINK AGAIN ! The big majority of Electronics designers do not worry about Power Factor (P.F.) P.F. is something you learnt one day at school in your Electrotechnics course"as being cos ϕ. This conventional definition is only valid when considering IDEAL Sinusoidal signals for both current and voltage waveforms. But the reality is something else, because most off- line power supplies draw a non-sinusoidal current! Many off-line systems have a typical front-end section made by a rectification bridge and an in- put filter capacitor. This front-end section acts as a peak detector (see figure 1). A current flows to charge the capacitor only when the istantaneous AC voltage exceeds the voltage on the capacitor. A single phase off-line supply draws a current pulse during a small fraction of the half-cycle du- ration. Between those current peaks, the load draws the energy stored inside the input capacitor. The phase lag ϕ but also the harmonic content of such a typical pulsed current waveform produce non efficient extra RMS currents, affecting then the real power available from the mains. So, P.F. is much more than simply cos ϕ! The P.F. value measures how much the mains ef- ficiency is affected by BOTH phase lag ϕ AND harmonic content of the input current. In this context, the standard European project IEC555-2 only defines the current harmonic con- tent limits of mains supplied equipments. THEORETICAL MEANING The power factor (P.F.) is defined by: P.F. = PS = REAL POWER TOTAL APPARENT POWER Ideal Sinusoidal Signals Both current and voltage waveforms are assumed to be IDEAL SINUSOIDAL waveforms. If the phase difference between the input voltage and the current waveforms is defined as the phase lag angle or displacement angle, the corresponding graphical representation of power vectors gives: The corresponding power give: AN824/1003 ® P = VRMS IRMS Cos ϕ ϕ S = VRMS IRMS total apparent power Q = VRMS IRMS Sin ϕ reactive or quadrature power D95IN224A Imains Vmains Load Vdc 0 T t Vmains Imains T/2 Vdc D95IN223 Figure 1: Full Wave Bridge Rectifier Waveforms. Then, by definition: P.F. = PS Cosϕ 1/5 Non-ideal sinusoidal current waveform Assume that the mains voltage is an IDEAL SINUSOIDAL voltage waveform. Its RMS value is: VRMS = Vpeak √2 If the current has a periodic non-ideal sinusoidal waveform, the FOURIER transform can be ap- plied IRMS total = √IO2 + I2 1RMS + I2 2RMS +....+ I2 nRMS Where IO is the DC component of the current, I1rms the fundamental of the RMS current and I2RMS ....InRMS the harmonics For a pure AC signal: IO = 0 The fundamental of the RMS current has an in- phase component I1RMSP and a quadrature com- ponent I1RMSQ. So, the RMS current can be espressed as: IRMS total = √ I2 1RMS P + I2 1RMS Q + ∑ n=2 ∞ I2 nRMS Then, the Real Power is given by: P = VRMS ⋅ I1RMS P As ϕ1 is the displacement angle between the in- put voltage and the in-phase component of the fundamental current: I1RMS P = I1RMS Cosϕ1 and P = VRMS ⋅ I1RMS ⋅ Cosϕ1 S = VRMS ⋅ IRMS total Then, the Power Factor can be calculated as: P.F. = PS = I1RMS ⋅ Cosϕ1 IRMS total One can introduce the k factor by k = I1RMSIRMS total = CosΘ Θ is the distortion angle. The k factor is linked to the harmonic content of the current. If the har- monic content of IRMS total is approaching zero, k------> 1. Conclusion Finally P.F. can be expressed by: P.F. = CosΘ ⋅ Cos ϕ1 So, the power vectors representation becomes P = Real Power = VRMS · I1RMS Cos ϕ1 ϕ1 Q = Reactive Power = VRMS · I1RMS Sin ϕ1 D95IN225A S1 = Apparent fundamental power = VMRS · I1RMS S - Total apparent Power -V RMS · IRMS total θ quadrature √ D = Distortion Power = VRMS ∑∞n=2 I2nRMS In-phase ϕ1 is the "conventional" displacement angle (phase lag) between the in-phase fundamental I and V Θ is the distortion angle linked to the harmonic content of the current. Both of reactive (Q) and distortion (D) powers produce extra RMS currents, giving extra losses so that then the mains supply network efficiency is decreased. Improving P.F. means to improve both of factors i.e.: ϕ1 → 0 ⇒ Cos ϕ1 → 1 ⇒ reduce phase lag between I and V Θ → 0 ⇒ Cos Θ → 1 ⇒ reduce harmonic content of I APPLICATION NOTE 2/5 PRACTICAL MEANING The unity power factor beneficiaries Both of the user and the Electricity distribution company take advantage from a unity power fac- tor. Moreover, adding a PFC brings components cost reduction in the downstream converter. The user’s benefit At minimum line voltage (85VAC), a standard 115VAC well socket should be able to deliver the nominal 15A to a common load. In similar conditions, a "non-corrected power fac- tor" SMPS (typical value of 0.6) drops the avail- able current from 15A to only 9A. For example, from one wall socket, four 280W computers each equipped with P.F.C. can be supplied instead of two with no P.F.C. The Electricity distribution company benefit Both of reactive (Q) power and distortion (D) power produce extra RMS currents. The resulting extra losses significantly decrease the mains supply network efficiency. This leads to oversize the copper area of distribution power wires (see figure 3) The distortion power is linked to the current har- monic content. Delivering power at other frequen- cies than the line frequency causes a lot of draw- backs. The current distortion disturbs the zero crossing detection systems, generates overcurrent in the neutral line and resonant overvoltages. In Europe, the standard EN 60555 and the inter- national project IEC 555-2 limit the current har- monic content of mains supplied equipments. Figure 3: Reactive and distortion power produce extra RMS currents leading to copper area oversize. 115VAC/15A Without P.F.C. With P.F.C. D95IN227 Figure 2: Reactive and distortion power produce extra RMS currents leading to copper area oversize. APPLICATION NOTE 3/5 Components cost reduction in the down- stream converter For the same output power capability, a conven- tional converter using a input mains voltage dou- bler, is penalized by a 1,8 times higher primary RMS current than with a PFC preregulator. Consequently, the PFC allows to select power MOSFET’s switches with up to 3 times higher on resistance (rds on) in the downstream converter(see figure 4). The converter transformer size can be optimized not only because the copper area is smaller but also, due to the regulated DC bulk voltage deliv- ered by the PFC preregulator. The PFC provides an automatic mains selection on a widerange voltage from 85VAC up to 265VAC. Compared to the conventional doubler front-end section, the same "hold-up" time can be achieved with a 6 times smaller bulk storage ca- pacitor. To get 10ms hold-up time, a 100W converter in doubler operation requires a series combination of two 440µF capacitos instead of one 130µF with PFC. General comments For new developments, SMPS designers will have to consider the IEC 555-2 standard. In the practice, this leads to use a PFC is com- pensated by significant component cost reduction in the downstream converter. The PFC also provides additional functions such as automatic mains voltage selection and a con- stant output voltage. Nevertheless, size a nd cost optimization of PFC has to take the RFI filter section into account. A PFC circuit generates more high frequency in- terferences to the mains than a conventional rec- tifier front-end section (see figure 5). The PFC use requires thus additional filtering. For this reason, modulation techniques and mode of operation for the PFC have to be carefully adapted to the application requirement. Figure 4: Power MOSFET On-resistance (rds on) is 3 times higher by using a PFC. without P.F.C. with P.F.C. rds on rds onX3 lower sym. attenuation filter Ci 220µF D95IN226 Usaual SMPS structure higher sym. attenuation filter Ci 0.1µF P.F.C. structure Figure 5: A Power Factor Converter generates higher frequency interferences to the mains than a conventional rectifier front-end APPLICATION NOTE 4/5 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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