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Analog Integrated Circuit Design 斯坦福大学stanfordEE214.pdf

Analog Integrated Circuit Desig…

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STANFORD UNIVERSITY Department of Electrical Engineering Prof. Boris Murmann EE214: Analog Integrated Circuit Design - Autumn 2007/08 - http://eeclass.stanford.edu/ee214/ Table of Contents Introduction 3 Lecture 1 CMOS Technology, Long Channel MOS Model 10 Lecture 2 Common Source Amplifier 16 Lecture 3 Technology Characterization: gm/ID 30 Lecture 4 Technology Characterization: fT, gm/gds 42 Lecture 5 gm/ID-based Design 56 Lecture 6 Extrinsic Capacitance 68 Lecture 7 Miller Approximation, ZV Time Constant Analysis 85 Lecture 8 Electronic Noise 96 Lecture 9 Electronic Noise (Continued) 109 Lecture 10 Backgate Effect, Common Gate Stage 118 Lecture 11 Common Drain Stage 130 Lecture 12 Differential Pair 141 Lecture 13 Current Mirrors, Offset Voltage 152 Lecture 14 Process Variations, Feedback 165 Lecture 15 Fully Differential Amplifiers, SC Circuits 175 Lecture 16 Stability, Analysis of Feedback Circuits 185 Lecture 17 Loop Gain Simulation 197 Lecture 18 Two-Stage OTA 209 Lecture 19 Compensation, Noise in Feedback OTAs 218 Lecture 20 OTA Design Considerations 233 Lecture 21 Step Response 258 Lecture 22 Slewing 275 Lecture 23 Feedback and Port Impedances, OTA Variants 285 Lecture 24 Single Ended OTAs, Output Stage Examples 298 Lecture 25 Supply Insensitive Biasing 307 Lecture 26 Bandgap Reference 317 Lecture 27 Bandgap Reference (Continued) 323 Lecture 28 Technology Scaling 332 Lecture 29 Class Summary 348 1 2 EE 214 IntroductionB. Murmann 1 EE214 Analog Integrated Circuit Design Boris Murmann Stanford University murmann@stanford.edu Copyright 2007 by Boris Murmann EE 214 IntroductionB. Murmann 2 A Few Words About Your Instructor • Assistant Professor in EE since 2004 • PhD, UC Berkeley 2003 – Digitally assisted A/D conversion – Use "minimalistic" analog circuits (low power, fast) – Correct errors using digital post-processor • ~ 4 years work experience in IC industry – Mixed signal IC design, low power, high voltage • Current research – Digital correction techniques for data converters – Sensor interfaces – Circuit design in new technologies • Post-CMOS devices, organic devices 3 EE 214 IntroductionB. Murmann 3 EE214 Basics (1) • Teaching assistants – Mohammad Hekmat, Bob Wiser, Ross Walker • Administrative support – Ann Guerra, CIS 207 • Lectures are televised – But please come to class to keep the discussion interactive! • Web page: http://eeclass.stanford.edu/ee214 – Check regularly, especially bulletin board – Register for online access to grades and solutions • Only enrolled students can register; we manually control the access list based on Axess data EE 214 IntroductionB. Murmann 4 EE214 Basics (2) • Required text – Analysis and Design of Analog Integrated Circuits, 4th Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001. (On reserve in Engineering Library) • Course prerequisites – EE101B or equivalent – Basic device physics and models • PN junctions, MOSFETs, BJTs – Basic linear systems • Frequency response, poles, zeros – Some exposure to a circuit simulator, basic Unix commands – May consider concurrent enrollment in EE114X to brush up on the above (primarily for undergraduates) 4 EE 214 IntroductionB. Murmann 5 Assignments • Homework (20%) – Handed out on Mondays, due following Monday in class – Late policy • Score drops 0.5 dB per hour after deadline – Lowest HW score will be dropped – Policy for off-campus students: Fax/email to SCPD before deadline stated on handout • Midterm Exam (30%) • Project (20%) – Design of an amplifier using HSpice (no layout) – Work in teams of two • OK to discuss with other teams, but no file exchange! • Final Exam (30%) EE 214 IntroductionB. Murmann 6 Honor Code • Please remember you are bound by the honor code – I will trust you not to cheat – I will try not to tempt you • But if you are found cheating it is very serious – There is a formal hearing – You can be thrown out of Stanford • Save yourself and me a huge hassle and be honest • For more info – http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/ honorcode.pdf 5 EE 214 IntroductionB. Murmann 7 Be Reasonable When Asking TAs • The TAs will not give you "the answer times two"… • They will also NOT debug your Spice deck – Figuring out what's wrong with your circuit is an essential component of this class EE 214 IntroductionB. Murmann 8 Circuit Simulation • We will HSpice for circuit simulation – You can use other tools at "own risk" – "CAD Basics" document and example simulation files are provided on course web site and in course directory • Plot HSpice results using Matlab ("HSpice Toolbox") – Toolbox is installed in course directory • See "CAD Basics" document for setup info – Can download toolbox from Mike Perrott's homepage (MIT) • EE214 Technology – 0.35μm CMOS – BSIM3v3 models provided on web site and in course directory • First review session (this week) will focus on simulation basics 6 EE 214 IntroductionB. Murmann 9 The Spice Monkey Problem (1) • What most people know – Even a very large number of monkeys randomly arranging characters will never manage to write an interesting book • What some people tend to forget – Even a very large number of "Spice Monkeys" randomly tweaking circuits will never manage to design a robust, optimized IC [Courtesy Isaac Martinez] EE 214 IntroductionB. Murmann 10 The Spice Monkey Problem (2) • Simply put – Spice is nothing but a "calculator" that lets you evaluate and test your ideas – There is no need to simulate anything unless you already know the (approximate) answer! – Must always be aware of modeling limitations • Especially in the integrated circuits arena, uneducated, purely simulator driven design can be costly – Mask sets cost up to $2 Million (90 nm production) – Turnaround time is on the order of months – If your chip doesn't work, you cannot simply send the customer a "patch"… 7 Administrator Underline Administrator Underline EE 214 IntroductionB. Murmann 11 Analysis versus Design • Unlike common perception, analog circuit analysis and design is not "black magic" • Circuit analysis – The art of decomposing a circuit into manageable pieces – Based on the simple, but sufficiently accurate model • "Just-in-time" modeling; do not use a complex model unless you know why it's needed… – One circuit one solution • Circuit design – The art of synthesizing circuits based on experience from extensive analysis – One set of specifications Many solutions – Design skills are best acquired through "learning by doing" • This is why we'll have a design project… EE 214 IntroductionB. Murmann 12 Learning Goals • Develop deeper understanding of MOS device behavior relevant to analog design • Develop a feel for limits and tradeoffs in analog circuits (speed, noise, power dissipation) • Learn to bridge the gap between complex device models/behavior and basic hand calculations – Design using look-up tables, "gm/ID methodology" • Develop a systematic, non-spice-monkey design style • Solidify the above aspects in a hands-on design project – Design and optimization of a high performance feedback amplifier used in many industrial circuits/applications 8 Administrator Underline EE 214 IntroductionB. Murmann 13 Preview - Design Example of Lecture 20 Cs - Vsd + + Vod - Cs Cf Cf CL CL Vid M1a,b M2a,bM3a,b M4a,b Specs: Loop bandwidth (fc) = 200MHz Phase margin = 75 degrees DR = 72dB Closed-loop gain =2 Static gain error < 0.5% EE 214 IntroductionB. Murmann 14 Course Topics • CMOS technology and device models • Electronic noise • Single-stage amplifiers • Current mirrors, active loads • Differential pairs • Operational transconductance amplifiers (OTAs) • Feedback, stability and compensation • Temperature and supply independent biasing 9 EE 214 Lecture 1B. Murmann 1 Lecture 1 CMOS Technology Long Channel MOS Model Boris Murmann Stanford University murmann@stanford.edu Copyright 2007 by Boris Murmann EE 214 Lecture 1B. Murmann 2 Overview • Reading – 2.8 (MOS fabrication), 2.9 (Active MOS devices) – 2.10.1 (Resistors), 2.10.2 (Capacitors) – 1.1, 1.5.0, 1.5.1, 1.5.2, 1.5.3 (Large signal MOS model) • Introduction – In this first lecture, we will cover some of the background that positions EE214 as an introductory course on circuit design using CMOS technology. In the lectures to come, we will focus on the problem of amplifier design as a vehicle to establish a set of considerations that apply to more complex circuits and also other technologies. At first, we will review the "long channel model" of a MOS transistor. Driven by circuit examples, we will later augment this simple model to include additional effects that are relevant in practice. 10 EE 214 Lecture 1B. Murmann 3 The Big Picture • Most modern electronic information processing systems rely on amplification of "small" physical signals – E.g. signal from RF antenna, disk drive head, microphone, … • EE214 uses amplifiers as a vehicle to teach you the basics of analog integrated circuit analysis and design – Material forms basis for other and/or more complex circuits EE 214 Lecture 1B. Murmann 4 Technological Progress Vacuum Tube 1906 Modern CMOS Transistor 1947 Modern Discrete Transistors Integrated Circuit 1958 11 EE 214 Lecture 1B. Murmann 5 45nm CMOS (Intel) Steve Cowden THE ORGONIAN July 2007 EE 214 Lecture 1B. Murmann 6 Economics [European Nanotechnology Roadmap] 12 EE 214 Lecture 1B. Murmann 7 Future Applications EE 214 Lecture 1B. Murmann 8 Discrete vs. Integrated Circuits • Minimize transistor count • Devices usually don't match • Arbitrary resistor values • Capacitors 1pF…10mF • "Unlimited" number of transistors • Devices match well • Keep resistors < 10…100k • Keep capacitors < 10…50pF Discrete Audio Amplifier Integrated CMOS Audio Amplifier 13 EE 214 Lecture 1B. Murmann 9 Modern Integrated Circuit Technologies • Why use CMOS for analog integrated circuits? – Low cost, driven by high volume digital ICs – Integration with high density digital circuits • BiCMOS tends to be expensive BestBetterPoorIntrinsic gain GoodGoodPoorTransconductance GoodGoodPoorNoise HighHighHighDevice Speed SiGe BJTSi BJTCMOSParameter EE 214 Lecture 1B. Murmann 10 Basic MOS Operation (1) • With zero voltage at the gate, device is "off" – Back-to-back reverse biased pn junctions 0V VD (>0V)0V 0V 14 EE 214 Lecture 1B. Murmann 11 Basic MOS Operation (2) • With a positive gate bias applied, electrons are pulled toward the positive gate electrode • Given a large enough bias, the electrons start to "invert" the surface (pn); a conductive channel forms – Magic "threshold voltage" Vt (more later) >0 EE 214 Lecture 1B. Murmann 12 Basic Operation (3) • If we now apply a positive drain voltage, current will flow • How can we calculate this current as a function of VGS, VDS? >0 VDS>0 ID=? 15 EE 214 Lecture 2B. Murmann 1 Lecture 2 Common Source Amplifier Small-Signal Model Boris Murmann Stanford University murmann@stanford.edu Copyright 2007 by Boris Murmann EE 214 Lecture 2B. Murmann 2 Overview • Reading – 3.0 (Amplifier basics), 3.1 (Model selection) – 3.3.2 (Common source amplifer) – 1.6.0 - 1.6.5 (Small signal MOS model) • Introduction – Today we'll complete our derivation of the basic long- channel MOSFET I-V characteristics. As a next step, we'll use this simple model to construct our first amplifier – a common source stage. Looking at its transfer function, we'll find that treating signals as "small" with respect to the bias conditions allows us to linearize the circuit. Next, we generalize this approach and develop a more universal "plug-and-play" small-signal model for MOS devices that are biased in the active region. 16 EE 214 Lecture 2B. Murmann 3 Basic MOS Operation • How can we calculate ID as a function of VGS, VDS? >0 VDS>0 ID=? EE 214 Lecture 2B. Murmann 4 Assumptions 1) Current is controlled by the mobile charge in the channel. This is a very good approximation. 2) "Gradual Channel Assumption" - The vertical field sets channel charge, so we can approximate the available mobile charge through the voltage difference between the gate and the channel 3) The last and worst assumption (we will fix it later) is that the carrier velocity is proportional to lateral field (ν = μE). This is equivalent to Ohm's law: velocity (current) is proportional to E-field (voltage) >0 VDS>0 17 EE 214 Lecture 2B. Murmann 5 First Order IV Characteristics (1) • What we know: [ ]tGSoxn VyVVCyQ = )()( WvQI nD = Ev = μ [ ] WEVyVVCI tGSoxD = μ)( EE 214 Lecture 2B. Murmann 6 First Order IV Characteristics (2) dy ydVE )(=[ ] WEVyVVCI tGSoxD = μ)( [ ] dVVyVVCWdyI tGSoxD = )(μ [ ] = DSV tGSoxLD dVVyVVCWdyI 00 )(μ ( ) DSDStGSoxD VVVVL WCI = 2 μ • For VDS/2 << VGS-Vt, this looks a lot like a linear resistor: I=1/R V • Lets plot this IV relationship... 18 EE 214 Lecture 2B. Murmann 7 Plot of First Order IV Curves • Something is wrong here... – Current should never decrease with increasing VDS • What happens when VDS>VGS-Vt? – VGD = VGS-VDS becomes less than Vt, i.e. no more channel or "pinch off" VDS ID VGS-Vt EE 214 Lecture 2B. Murmann 8 Pinch-Off • Effective voltage across channel is VGS - Vt – After channel charge goes to 0, there is a high lateral field that ‘sweeps’ the carriers to the drain, and drops the extra voltage (this is a depletion region of the drain junction) • To first order, current becomes independent of VDS N N – V G S + + V DS – y y = 0 y = L Q ( y ) , V ( y ) n Voltage at the end of channel Is fixed at VGS-Vt 19 EE 214 Lecture 2B. Murmann 9 Modified Plot and Equations VDS ID VGS-Vt Triode Region Active Region ( ) DSDStGSoxD VVVVL WCI = 2 μTriode Region: Active Region: ( ) 2)( 2 1)( 2 )( tGSoxtGS tGS tGSoxD VVL WCVVVVVV L WCI = = μμ EE 214 Lecture 2B. Murmann 10 First-Order MOS Model Summary ( )2 2 1 tGSoxD VVL WCI μ Su b-T hre sho ld (mo re l ate r...) Vt VGS VDS VGS-Vt ACTIVE TRIODE ( ) DSDStGSoxD VVVVL WCI 2 μ "VCCS" 20 EE 214 Lecture 2B. Murmann 11 Model Accuracy • The above equations constitute the most basic MOS IV model – "Long channel model", "quadratic model", "low field model" • Unfortunately this model doesn't describe modern CMOS devices accurately – Pushing towards extremely small geometries has resulted in very high electric fields • Some of the assumptions on slide 4 become invalid • Other second order dependencies arise • Nevertheless, we will use this simple model in the first few lectures to develop some basic circuit intuition – Will fix and refine as we go… – "Just-in-time" modeling EE 214 Lecture 2B. Murmann 12 Let's Build Our First Amplifier • One way to amplify – Convert input voltage to current using voltage controlled current source (VCCS) – Convert back to voltage using a resistor (R) • "Voltage gain" = ΔVout/ΔVin – Product of the V-I and I-V conversion factors 21 EE 214 Lecture 2B. Murmann 13 Common Source Amplifier • MOS device acts as VCCS ( )2 2 1 tioxD VVL WCI = μ ( ) RVV L WCVV tioxDDo = 22 1 μ EE 214 Lecture 2B. Murmann 14 Biasing • Need some sort of "battery" that brings input voltage into useful operating region • Define VOV=VI-Vt, "quiescent point gate overdrive" – VOV=VGS-Vt with no input signal applied "Bias" "Signal" VI ΔVo ΔVi VO VOV 22 EE 214 Lecture 2B. Murmann 15 Relationship Between Incremental Voltages • What is ΔVo as a function of ΔVi? ( ) ( )[ ] [ ] Δ+Δ= Δ+Δ= Δ+=Δ Δ+=Δ+ OV i i OV D iiOVox OViOVoxo iOVoxDDoO V VVR V I VVVR L WC VVVR L WCV RVV L WCVVV 2 12 2 2 1 2 1 2 1 2 22 2 μ μ μ • As expected, this is a nonlinear relationship • Nobody likes nonlinear equations; we need a simpler model – Fortunately, a linear approximation to the above expression is sufficient for 90% of all analog circuit analysis EE 214 Lecture 2B. Murmann 16 Small Signal Approximation (1) • Assuming ΔVi << 2VOV, we have Δ+Δ=Δ OV i i OV D o V VVR V IV 2 12 i OV D o VRV IV ΔΔ 2 • If we further pretend that the input voltage increment is infinitely small, we can find this result directly by taking the derivative of the large signal transfer function at the "operating point" VI R V I dV dV OV D VVi o Ii = = 2 23 EE 214 Lecture 2B. Murmann 17 Small Signal Approximation (2) • Graphical illustration: VI VO VOV dVo/dVi • The slope of the above tangent is the so called "small signal gain" of our amplifier EE 214 Lecture 2B. Murmann 18 Small Signal MOS Model • Fortunately we don't have to repeat this analysis for every single circuit we build • Instead, we derive a linearized circuit model for the MOS transistor and plug it into arbitrary circuits 24 EE 214 Lecture 2B. Murmann 19 Transconductance • The parameter that relates small signal gate voltage to drain current is called transconductance (gm), or y21 in two-port nomenclature • The transconductance is found by differentiating the large signal I-V characteristic of the transistor in its operating point ( )2 2 1 tGSoxD VVL WCI = μ ( ) OVoxtGSox GS D gs d m VL WCVV L WC V I v ig μμ == == OV D m V Ig 2= EE 214 Lecture 2B. Murmann 20 Additional Model Components • Now that we've decided to move on using "small signal" approximations, it also becomes easier to refine our model and make it more realistic • Let's first take a look at "intrinsic gate capacitance" – Intrinsic means that these capacitances are unavoidable and required for the operation of the device – Note that there are plenty of extrinsic, technology related capacitances • We'll talk about some of those later • When talking about gate capacitance, we must distinguish several operating regions – Transistor on • Triode and active regions – Transistor "off" • Subthreshold operation 25 EE 214 Lecture 2B. Murmann 21 Transistor in Triode Region • Gate terminal and conductive channel form a parallel plate capacitor across gate oxide CGC= WLεox/tox= WLCox – We can approximately model this using lumped capacitors of size CGC each from gate-source and gate-drain • Changing either voltage will change the channel charge • The depletion capacitance CCB adds extra capacitance from drain and source to substrate – Usually negligible L S D W G C GC C CB EE 214 Lecture 2B. Murmann 22 Transistor in Active Region • Assuming a long channel model, if we change the the source voltage in the forward active region – The voltage difference between the gate and channel at the drain end remains at Vt, but the voltage at the source end changes – This means that the "bottom plate" of the capacitor does not change uniformly • Detailed analysis shows that in this case Cgs=2/3WLCox – See text, section1.6.2 • In the long channel model for forward active operation, the drain voltage does not affect the channel charge – This means Cgd=0 in the forward active region! • Neglecting second order effects and extrinsic caps, of course 26 EE 214 Lecture 2B. Murmann 23 Transistor Off • There is no conductive channel – Gate sees a capacitor to substrate, equivalent to the series combination of the gate oxide capacitor and the depletion capacitance • If the gate voltage is taken negative, the depletion region shrinks, and the gate-substrate capacitance grows – With large negative bias, the capacitance approaches CGC L S D W G C GC C CB EE 214 Lecture 2B. Murmann 24 Intrinsic MOS Capacitor Summary 00Cgb 0 WLCox0Cgd 2/3 WLCox WLCox0Cgs Forward ActiveTriodeSubthreshold 1 11 + oxC

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