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Analog Circuit Design (2009).pdf

Analog Circuit Design (2009).pdf

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Analog Circuit Design Arthur H. M. van Roermund • Herman Casier Michiel Steyaert Editors Analog Circuit Design Smart Data Converters, Filters on Chip, Multimode Transmitters ABC Editors Dr. Arthur H. M. van Roermund Department of Electrical Engineering Eindhoven University of Technology 5600 MB Eindhoven Netherlands a.h.m.v.roermund@tue.nl Dr. Herman Casier Avondster 6 8520 Kuurne Belgium herman casier@ieee.org Prof. Michiel Steyaert Department of Electrical Engineering (ESAT) Katholieke Universiteit Leuven Kasteelpark Arenberg 10 3001 Leuven Belgium michiel.steyaert@esat.kuleuven.be ISBN 978-90-481-3082-5 e-ISBN 978-90-481-3083-2 DOI 10.1007/978-90-481-3083-2 Springer Dordrecht Heidelberg London New York Library of Congress Control Number: 2009929389 c No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Cover design: eStudio Calamar S.L. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Springer Science+Business Media B.V. 20 01 Preface This book is part of the Analog Circuit Design series and contains contributions of the speakers of the 18th workshop on Advances in Analog Circuit Design (AACD), which was organized by Sven Mattisson of Ericsson. The workshop was held in Lund, Sweden, from March 31 to April 2, 2009. The book comprises three parts, covering advanced analog and mixed-signal circuit design fields that are considered as very important by the circuit design com- munity: Smart Data Converters Filters on Chip Multimode Transmitters Each part is set up with six papers from experts in the field. The aim of the AACD workshop is to bring together a group of expert designers to discuss new developments and future options. Each workshop is then followed by the publication of a book by Springer in their successful series of Analog Circuit Design. This book is number 18 in this series. The books can be seen as a refer- ence for all people involved in analog and mixed-signal design. The full list of the previous books and topics in the series is given next. We are confident that this book, like its predecessors, provides a valuable contri- bution to our analog and mixed-signal circuit-design community. Arthur van Roermund. The topics covered before in this series: 2008 Pavia (Italy) High-speed Clock and Data Recovery High-performance Amplifiers Power Management 2007 Oostende (Belgium) Sensors, Actuators and Power Drivers for the Automotive and Industrial Environment Integrated PAs from Wireline to RF Very High Frequency Front Ends (continued) v vi Preface (continued) 2006 Maastricht (The Netherlands) High-speed AD Converters Automotive Electronics: EMC Issues Ultra Low Power Wireless 2005 Limerick (Ireland) RF Circuits: Wide Band, Front-Ends, DACs Design Methodology and Verification of RF and Mixed-Signal Systems Low Power and Low Voltage 2004 Montreux (Swiss) Sensor and Actuator Interface Electronics Integrated High-Voltage Electronics and Power Management Low-Power and High-Resolution ADCs 2003 Graz (Austria) Fractional-N Synthesizers Design for Robustness Line and Bus drivers 2002 Spa (Belgium) Structured Mixed-Mode Design Multi-Bit Sigma-Delta Converters Short-Range RF Circuits 2001 Noordwijk (The Netherlands) Scalable Analog Circuits High-Speed D/A Converters RF Power Amplifiers 2000 Munich (Germany) High-Speed A/D Converters Mixed-Signal Design PLLs and Synthesizers 1999 Nice (France) XDSL and other Communication Systems RF-MOST Models and Behavioural Modelling Integrated Filters and Oscillators 1998 Copenhagen (Denmark) 1-Volt Electronics Mixed-Mode Systems LNAs and RF Power Amps for Telecom 1997 Como (Italy) RF A/D Converters Sensor and Actuator Interfaces Low-Noise Oscillators, PLLs and Synthesizers 1996 Lausanne (Swiss) RF CMOS Circuit Design Bandpass Sigma Delta and Other Data Converters Translinear Circuits 1995 Villach (Austria) Low-Noise/Power/Voltage Mixed-Mode with CAD Tools Voltage, Current and Time References 1994 Eindhoven (Netherlands) Low-Power Low-Voltage Integrated Filters Smart Power 1993 Leuven (Belgium) Mixed-Mode A/D Design Sensor Interfaces Communication Circuits 1992 Scheveningen (The Netherlands) OpAmps ADC Analog CAD Contents Part I Smart Data Converters 1 LMS-Based Digital Assisting for Data Converters . . . . . . . . . . . . . . . . . . . . . . . . 3 Bang-Sup Song 2 Pipelined ADC Digital Calibration Techniques and Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Imran Ahmed 3 High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Hans Van de Vel 4 A Signal Processing View on Time-Interleaved ADCS . . . . . . . . . . . . . . . . . . . 61 Christian Vogel 5 DAC Correction and Flexibility, Classification, New Methods and Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Georgi Radulov, Patrick Quinn, Hans Hegt, and Arthur van Roermund 6 Smart CMOS Current-Steering D/A-Converters for Embedded Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Martin Clara, Daniel Gruber, and Wolfgang Klatzer Part II Filters On-Chip 7 Synthesis of Low-Sensitivity Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Lars Wanhammar 8 High-Performance Continuous-Time Filters with On-Chip Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Jose Silva-Martinez and Aydın I. Karsılayan vii viii Contents 9 Source-Follower-Based Continuous Time Analog Filters . . . . . . . . . . . . . . . .167 Stefano D’Amico, Marcello De Matteis, and Andrea Baschirotto 10 Reconfigurable Active-RC Filters with High Linearity and Low Noise for Home Networking Applications . . . . . . . . . . . . . . . . . . . . . .189 Jan Vandenbussche, Jan Crols, and Yuichi Segawa 11 On-Chip Instantaneously Companding Filters for Wireless Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Vaibhav Maheshwari and Wouter A. Serdijn 12 BAW-IC CO-Integration Tunable Filters at GHz Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 Andreia Cathelin, Stephane Razafimandimby, and Andreas Kaiser Part III Multi-mode Transmitters 13 Multimode Transmitters: Easier with Strong Nonlinearity. . . . . . . . . . . . . .247 Earl McCune 14 RBS High Efficiency Power Amplifier Research – Challenges and Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 Bo Berglund, Ulf Gustavsson, Johan Thoreback, Thomas Lejon, and Ericsson AB 15 Multi-Mode Transmitters in CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 Manel Collados, Xin He, Jan van Sinderen, and Raf Roovers 16 Challenges for Mobile Terminal CMOS Power Amplifiers . . . . . . . . . . . . . .295 Patrick Reynaert 17 Multimode Transmitters with †-Based All-Digital RF Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 A. Frappe, A. Kaiser, A. Flament, and B. Stefanelli 18 Switched Mode Transmitter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 Henrik Sjoland, Carl Bryant, Vandana Bassoo, and Mike Faulkner Part I Smart Data Converters The first part of this book covers the theme ‘Smart Data Converters’. As the name indicates, it deals with smart converters that have some kind of smartness imple- mented on chip, to make the converter better in performance for a given amount of resources like power dissipation and area. On-chip smartness might also result in an increase in yield, a decrease in design effort, a higher flexibility, more functionality and/or broader applicability. All these aspects in turn also pay off in less cost. The Part starts with AD converters. Three types of AD converters achieve considerable attention nowadays, and are therefore addressed here: pipelined, Sigma-Delta, and time-interleaved AD converters. The first paper discusses both LMS-based calibrated pipeline and Sigma-Delta converters and also makes some comparisons between the two. The second paper fully focuses on pipeline con- verters and addresses several calibration techniques. The third paper discusses a calibrated pipeline in the application context of a multi-channel, and thus wideband, front end of a cellular base station. Next we proceed with a paper on time-interleaved converters. Here the problem is in the equality of the channels in terms of gain, time, and more generically seen: in spectral behaviour. This paper will address the problem from a signal-processing point of view, so from a higher level of abstraction, to show what theoretical ap- proaches are possible to correct for lower-level induced channel differences, and what are the tradeoffs between them, on an algorithmic level. Finally we end up with two DA papers. The first one gives an overview and classification of smart approaches for Current-Steering DAs, as they are known now in literature, shows solutions for missing approaches, and addresses flexibility as one of the features of smart converters. The second DA paper also addresses Current- Steering DAs, but focuses more specifically on the embedding of these kinds of converters in systems-on-chip (SoCs), which implies some extra constraints that should be met. Arthur van Roermund Chapter 1 LMS-Based Digital Assisting for Data Converters Bang-Sup Song Abstract Aggressive device scaling down to the nano-meter range offers IC designers both opportunities and challenges. Digital designers benefit greatly from the system flexibility and affordability, but analog/RF designers are struggling with flawed devices. Since scaled devices are faster and smaller, the incentive to use such strengths advantageously has prompted many efforts to overcome analog im- perfection by digital means. Designers are introducing more DSP functionality to enhance the performance of analog/RF systems. More intelligence is being built into analog/RF designs as in linear PA, RF receiver front-end, ADC/DAC, digital PLL, etc. Such pervasive design techniques with digital assisting will prevail in the future SOC design. After a brief overview of the trend, examples of the LMS-based calibration algorithm applied to the pipeline and CT cascaded † modulator are discussed. 1.1 Introduction CMOS analog design has evolved along with the device scaling for three decades since early 1980s. In its early days, the supply voltage was higher, the opamp had high gain while devices were slow, and the crude lithography limited the capaci- tor matching only to 8–9 b level. The two-stage opamp and the simple SAR were predominantly used at low 10 s of kHz range mostly for the voice-band processing. The † modulator was feasible, but digital filtering was very costly. This changed in 1990s as CMOS was aggressively scaled down towards the sub-micron range. In this middle period, the supply voltage was lowered from high 5–10 to 1.8–3.3 V, and devices were fast enough to digitize the video band and beyond. Two ADC archi- tectures stood out – pipeline for high-speed communications and video, and † for high-resolution audio. Cascaded single-stage opamp was adopted, and many ADC calibration techniques were developed to enhance the resolution of the pipelined B.-S. Song () Department of Electrical and Computer Engineering, University of California, San Diego, USA e-mail: song@ece.ucsd.edu A.H.M. van Roermund et al. (eds.), Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters, DOI 10.1007/978-90-481-3083-2 1, c Springer Science+Business Media B.V. 2010 3 4 B.-S. Song ADC to above 12 b range. Now in 2000s, CMOS is still being scaled down from the sub-micron to the nano-meter range, and the supply voltage also approaches sub 1 V. The real advantages of such scaled devices are raw speed, fine lithography, and almost free digital circuitry. The fine-line lithography also made the bare capacitor matching of 12 b level feasible. These days, analog engineers start with faster and more accurate devices than earlier generations did, and most designs turn out to be already high speed and high resolution with low power. However, a couple of problems should be dealt with. With low supply voltages, SNR is limited by the signal swing, and the low gain de- feats any design effort to use the conventional analog design wisdom accumulated over decades. In addition, the device leakage makes any accurate switched-capacitor design difficult. In fact, it appears that the analog design trend is reset, and it starts over again from the beginning. Two or multi-stage opamps are back, but their gain is still low and non-linear. Old ADC designs such as algorithmic, SAR, and time- interleaving are also being revisited. In order to avoid using low-gain non-linear opamps, the new breeds of ADC architectures that use no opamps started to emerge. Examples are comparator-based pipeline ADCs and quantizers based on time res- olution. On the other hand, the industry has grown with the powerful broadband digital processing that enables SOCs such as cellphone, WiFi, TV tuner, : : : This new environment has created a demand for wideband ADCs such as IF quantizers with very high SFDR to facilitate the digital channel filtering after quantizing the desired spectrum with large blocker channels. Also for high-resolution graphic or imaging, high SNR over 80 dB and low-level linearity over 15 b at sampling rates over 50 MS/s are required to resolve even dark images further in more details. It is challenging to meet such demands with scaled low-voltage CMOS. Two high-resolution ADC architectures that can meet such high demands are the calibrated pipelined ADC and the CT † modulator. The former is now well estab- lished enough to calibrate even the opamp non-linearity. The latter exhibits many desirable features in wireless applications and gains momentum as it requires no anti-aliasing, and SNR is improved not by the calibration accuracy but by the feed- back. In the following sections, after high-resolution ADCs and their fundamental limits are overviewed, an LMS-based resolution-enhancing technique is introduced, which eliminates the residual error after calibration using the zero-forcing LMS servo feedback concept. 1.2 High-Resolution ADCs High-resolution ADCs sampling at 10–250 MS/s with 12–16 b linearity have been implemented mostly with SAR, †, or pipeline architectures as shown in the resolution spectrum of Fig. 1.1. The SAR is very desirable for low-voltage and low- power applications since it uses only one comparator. However, the pipeline offers a significant speed advantage while the † is more robust in achieving high reso- lution. High-resolution ADCs at high sampling rates are only feasible with scaled 1 LMS-Based Digital Assisting for Data Converters 5 Fig. 1.1 Resolution vs. bandwidth of ADCs High-Resolution Applications technology with low supply voltages, and their performance is commonly character- ized by their linearity measured by SFDR or THD. Such ADCs with high linearity but poor SNR are allowed in systems performing digital filtering. The earliest effort to enhance the ADC resolution was an EPROM-based code- mapping technique using a radix <2, which warrants monotonicity and proper addressing [1]. However, it was possible only at factory since it required external precision instruments. The first self-calibration concept for the SAR was introduced to measure capacitor mismatch errors, to store them digitally, and to subtract them during the normal operation [2, 3]. This self-calibrated SAR based on the charge redistribution capacitor array was slow, and the over-sampling ADC covered the voice or audio band better. Also one critical flaw of the high-resolution SAR was the slowly-varying offset of the comparator due to the stress inflicted upon the input differential pair of the comparator when several decisions are made repeatedly after one input sampling. Finally, the Nyquist-rate ADC above the video band became a reality when the pipelined architecture was introduced [4], and the capacitor-array MDAC as a residue amplifier enabled the development of high-resolution ADCs [5–7]. The switched-capacitor MDAC performs multiple functions of sampling, DAC subtraction, and amplification as a residue amplifier in the pipelined ADC or as an integrator in the DT † modulator. Figure 1.2 compares the switched-capacitor MDAC with the CT integrator. The former is used in an open-ended system, and the residue amplifier should settle with an absolute accuracy. However, the latter rests inside the feedback loop, and its gain and non-linearity errors are reduced by the loop gain. One critical fac- tor to consider at the system level is the anti-aliasing requirement. Nyquist-rate ADCs need high-order anti-aliasing filters when operated at close to the Nyquist rate while CT † modulators need no anti-aliasing at all. The speed advantage of the pipelined ADC over the † modulator has always been by a factor of 2 to 4, but the gap was quickly narrowed as technology was scaled. A good example is the first digitally-calibrated 1 MS/s, 16 b ADC product (MAX1200) overtaken by the 6 B.-S. Song Fig. 1.2 Pipeline vs. CT † modulator Pipeline MDAC CT Modulator Residue amp in open loop Integrator in feedback High opamp gain Low opamp gain Gain error No gain error Reduced by residue gain Reduced by loop gain DAC mismatch error DAC mismatch error Absolute settling Linear settling Tolerable offsetOffset in correction range Anti-aliasing filter No anti-aliasing filter ΔΣ † ADC [8]. It also happened earlier in 1980s when the † modulator replaced the self-calibrated SAR as audio coders. Even today, the same competition between the pipelined ADC and the † modulator still continues. The common theme in this competition for the best is now calibration. The CT † modulator also needs calibration as the over-sampling ratio is lowered to 6–8 approaching the Nyquist rate for high-speed operation. All earlier calibration was done in the analog domain although measured errors were stored digitally. An effort to perform the error subtraction in the digital do- main led to the digital calibration concept [9, 10], but error measurements were still performed in a separate measurement cycle. The term such as foreground or background is used depending on how the error measurement is performed [11– 15]. The latest background error measurement technique has evolved into a very sophisticated one, called PN dithering. The PN sequence is a pseudo-random binary pulse sequence with an equal probability of 1 or 1 over a long sample period. It was used for the pulse modulation for the radar jamming during the World War II, and also for the military security communications known as Spread Spectrum and Global Positioning System [16], which are now well known as commercial systems such as CDMA and GPS. The first example of using the PN sequence to enhance the ADC resolution was to dither the ADC for low DNL, a

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