High Speed Data Conversion

3 4 1INTRODUCTION The design considerations for high-speed data conversion are, in many ways, similar to those for data conversion in general. High speed circuits may sometimes seem different because device types can be limited and only certain design techniques and architectures can be used with success. But the basics are the same. High speed circuits or systems are really those that tend to press the limits of state-of-the-art dynamic performance. This bulletin focuses on the more fundamental building blocks such as op amps, sample/holds, digital to analog and analog to digital converters (DACs and ADCs). It concludes with test techniques. Op amps, which tend to be the basic building blocks of systems, are be considered first. Sample/ holds which play an important role in data conversion are considered next followed by DACs and finally ADCs. ADCs are really a combination of the other three circuits. Emphasis is given to hybrid and monolithic design techniques since, in practice, the highest levels of performance are achieved using these processes. The material is presented from a design perspective. Theory and practical examples are of- fered so both the data conversion component designer and user will find the material useful. The concepts presented do not require extensive experience with data conversion. Fun- damental concepts are discussed allowing the subject to be understood easily. The material emphasizes high speed cir- cuit considerations—circuit theory is not treated in depth. Topics Covered in this Bulletin A. Amplifier Architectures 1. Buffer 2. Operational 3. Open Loop 4. Comparator B. Amplifier Applications 1. Sample/Hold 2. Peak Detector C. Digital to Analog Converters 1. Bipolar 2. Deglitched DAC D. Analog to Digital Converters 1. Successive Approximation 2. Flash 3. Sub-ranging E. Test Techniques 1. Settling Time 2. Aperture Jitter 3. Beat Frequency Testing 4. Servo Loop Test AMPLIFIER ARCHITECTURES Amplifiers of all types play an important role in data conversion systems. Since high speed amplifiers are both useful and difficult to design, an understanding of their operation is important. Four different types of amplifier architectures will be discussed. Buffers, op amps, open loop amplifiers, and comparators can be found in just about any signal processing application. THE BUFFER The open loop buffer is the ubiquitous modern form of the emitter follower. This circuit is popular because it is simple, low cost, wide band, and easy to apply. The open loop buffer is important in high speed systems. It serves the same purpose as the voltage follower in lower speed systems. It is often used as the output stage of wideband op amps and other types of broadband amplifiers. Consider the two buffer circuit diagrams, Figures 1 and 2. The output impedance of each buffer is about 5 W and bandwidths of several hundred megahertz can be achieved. The FET buffer is usually implemented in hybrid form as very wideband FETs and transistors are usually not available on the same monolithic process. The all-bipolar form of the buffer is capable of FIGURE 1. High Speed Bipolar Buffer. VIN VOUT R4 R3 Q4 Q3 R2 Q2 V– V+ Q1 R1 R6 R5 Q6 Q5 VBIAS1 VBIAS2 HIGH SPEED DATA CONVERSION By Mike Koen (602) 746-7337 11 ©1991 Burr-Brown Corporation AB-027A Printed in U.S.A. June, 1991 ® SBAA045 2 being produced on a complementary monolithic process where both the NPN and PNP transistors are high perfor- mance vertical structures. Figure 1 shows the buffer in its most basic form. The input to the buffer is connected to a pair of complementary transistors. Each transistor is biased by a separate current source. The input transistors Q1 and Q2 through resistors R1 and R2 are connected to the bases of output transistors Q3 and Q4 so that offset will be zero if the base to emitter voltage of the NPN and PNP are equal. Zero offset requires that transistor geometries are designed for equal VBEs at the same bias current—achievable in a comple- mentary process. This circuit is very useful as it has a moderately high input impedance and the ability to supply high current outputs. One important use of this buffer circuit is to amplify the output current of a monolithic op amp. Monolithic op amps usually do not have output currents that exceed 10mA to 50mA, while the buffer shown in Figure 1 is capable of putting out more than 100mA. Typically this type of a buffer has a bandwidth of 250MHz, allowing it to be used in the feedback loop of most monolithic op amps with minimal effect on stability. Figure 3 shows how the loop is closed around the buffer so that the DC performance of the amplifier is determined by the unbuffered amplifier and not the output buffer. An advantage of the connection shown in Figure 3 is that load-driving heat dissipating is in the buffer so that thermally induced distortion and offset drift is removed from the sensitive input op amp. Figure 2 shows the FET version of the previously mentioned circuit. The FET buffer achieves zero offset by the mirror action of the NPN transistor Q5 that is reflected as the gate R2 Op Amp Buffer R1 VIN VOUT A1 A2 FIGURE 3. High Current Op Amp. FIGURE 2. High Speed FET Buffer. to source voltage of the input FET Q1. The VBE of Q5 determines the gate to source voltage of the FET current source Q4. Since the identical current flows in Q4 and Q1 the gate to source voltage of Q1 will also be equal to VBE. Since Q5 and Q6 are identical transistors the offset of the FET buffer circuit will be nominally zero. The circuit shown in Figure 2 is usually constructed in hybrid form so that it is usually necessary to adjust resistors R1 and R2 to set the offset of this circuit to zero. Setting the offset to zero is accomplished by laser-trimming resistors R1 and R2 with the buffer under power. (This is known as active trimming.) A common application of this circuit is to buffer the hold capacitor in a sample/hold. (See the section on sample/ holds.) The high impedance of the FET buffer allows the capacitor to retain the sample voltage for a comparatively long time as the room temperature input current of a typical FET is in the vicinity of 50pA. Another common application of either type of buffer circuit is to drive high capacitive loads without reducing the overall system bandwidth. Op amps, even though they have closed loop output impedances that are very low, can become unstable in the presence of high capacitive loads. The open loop buffer is usually more stable when driving capacitive loads, but this circuit will also develop a tendency to ring if the capacitive load becomes excessive. Figure 4 shows how the emitter follower can oscillate due to reactive output impedance. Figures 5 through 7 show calculated results for different conditions when a simple emitter follower is driv- ing a capacitive load which illustrates this oscillatory ten- dency. One very important application of the open loop buffer is to drive a “back matched” transmission cable. Back matching a cable is just as effective in preventing reflections as the more conventional method of terminating the cable at the receiving end. The advantage of the back matched cable is that the generating circuit does not have to supply steady- state current and there is no loss of accuracy due to the temperature dependent copper loss of the cable. Figure 8 shows circuit diagrams and explanations that describe the operation of the open loop buffer driving a “back matched” cable. V– VOUT R3 R4 Q6 Q7 R1 VBE + – R2 Q5 VBE + – VGS + – Q4 Q3 Q2 VIN Q1 V+ 3 phase margin. If open loop gain is stable over temperature and linearity with signal adequate, the requirement for high open loop gain is reduced. This is important since it is difficult to achieve high open loop gain for wideband ampli- fiers. There are several ways to shape the open-loop-gain/phase characteristics, or Bode Plot, of an amplifier. The method chosen depends on whether high slew rate or fast settling is to be emphasized. The methods of stabilizing the closed- loop gain of these amplifiers will also result in different settling time characteristics. The benefits of each of these methods will be explained. The first amplifier has a FET input and the other has a bipolar input. High speed amplifi- ers should be designed to drive 50 W loads to be most useful. 50 W cable is commonly used in high speed systems to interconnect signals. ZOUT = re + b (w ) = b (o) wb = w t b (o) RG RG + rb b (w ) 1 + j w wb ZOUT = re + ZOUT = REQ + j w LEQ RG + rb b (o) + j w (RG + rb) w t VIN VOUT RLCL V+ Q1 FIGURE 4. Output Impedance of Emitter Follower. = 1 – VOUT VIN [ k(1 – k2)1/2 sin 2 p (1 – k2) tT + cos 2 p (1 – k2) tT ] where: T = 2 p (LEQ • CL) k = T 4p REQ LEQ 1 RL CL + REQ = re + LEQ = RG + rb b (o) RG + rb w T 1 2 1 2 1 2 [ ] e–2p k(t/T) FIGURE 5. Time Response. fT = 1GHz RG = 50 W rb = 50 re = 5 CL = 50pF b (o) = 100 k = 0.35 T = 5.6ns fT = 5GHz RG = 50 W rb = 50 re = 5 CL = 50pF b (o) = 100 k = 0.44 T = 4.7ns fT = 5GHz RG = 50 W rb = 50 re = 5 CL = 50pF b (o) = 100 k = 0.51 T = 1.9ns FIGURE 6. Different Conditions. THE OPERATIONAL AMPLIFIER Several examples will be shown that depict the architecture of wideband op amps. These amplifiers have settling times to – 0.01% in under 100ns and closed loop bandwidths in excess of 100MHz. The question is often asked, “How much loop gain is enough?” Wideband amplifiers generally do not achieve as much open loop gain as lower frequency ampli- fiers. This is the result of optimization of bandwidth and FIGURE 7. Results. Time (ns) 0 1 2 3 4 5 6 7 8 9 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 Re la tiv e Am pl itu de k = 0.35, T = 5.6ns k = 0.44, T = 4.7ns k = 0.51, T = 1.9ns FIGURE 8. Back Matched Cable. RO VIN RO VOUT VIN V VOUT V T VIN VOUT VIN V VOUT V T T Reflected V/2 Received V/2 Cable Input V/2 V/2 4 Consider a classic two stage hybrid amplifier as shown in Figure 9. It can be compensated either with integrator feedback or with pole-zero compensation. Hybrid amplifiers can achieve the highest possible dynamic performance be- cause optimum input and output devices that can be used from widely differing technologies. Very often it is possible to achieve the combination of bandwidth, breakdown volt- age, and current levels needed only with hybrid techniques. It is instructive to analyze the performance of this amplifier in detail as a way of demonstrating many pertinent consid- erations for a high speed amplifier. High speed amplifiers may be configured in other ways but the major design considerations are the same. FET input amplifiers are very useful as their high input impedance serves to buffer the hold capacitor in sample and hold circuits. Additionally, a FET can tolerate much larger differential input voltages during overload conditions than bipolar input stages and there is no error due to input current. The input stage of the amplifier shown in Figure 9, draws 5mA per side and at 25 ° C the input current is typically 25pA. A bipolar input stage being operated at the same current would have an input current of approximately 50m A, which when transformed by the feedback resistor, would be an additional source of offset error and noise. To compen- sate for the low gain of the input stage (G = 25) it is desirable to maintain a differential connection between the first and second stages. When a connection of this type is made it is necessary to establish the operating point of the input stage using “common mode” feedback. Assuming that FET pair Q2 and Q3 are well-matched, the current is split evenly and emerges as equal collector current for transistors Q4 and Q5. The bases of Q4 and Q5 are connected together and applied to the common connection of the emitters of PNP transistors Q8 and Q9. Therefore, in order to establish balance in the loop, a voltage is created across R7 of such a magnitude to allow the current in transistors and Q4 to be a value that will exactly balance the current needed by FETs Q2 and Q3. Transistors Q8 and Q9 a driven from a pair of emitter followers to increase the overall loop gain. Emitter follower transistors Q6 and Q7 increase the gain of the first stage by preventing transistors Q8 and Q9 from loading the drains of the input FET pair. The differential output of transistors Q8 and Q9 are then connected to the output emitter followers directly and through the mirroring action of transistors Q12 and Q13. The overall DC gain of this amplifier is 94dB. The current through the output emitter follower is established by the biasing action of the diode connected transistors Q10 and Q11. The offset voltage of this amplifier is trimmed to under 1mV and the amplifier has a voltage offset drift coefficient of less than 10m V/ ° C. FIGURE 9. FET Operational Amplifier. VBIAS Q4 R5 Q1 R1 R2 –In +In Q2 Q5 R6 R3 Q3 Pole-Zero Comp R9 R7 Q8 Q9 Q6 Q7 To V– To V– Q10 Q11 Q12 Q13 R9R8 V– V+ Integrator Compensation Q15 R10 R11 Q14 VOUT C1 C2 C3 5 The second architecture that will be discussed is known as the folded cascode operational amplifier. This circuit ar- rangement is very useful as all the open loop gain is achieved in a single stage. Since all of the gain is developed in a single stage, higher usable gain bandwidth product will result as the Bode Plot will tend to look more like a single pole response which implies greater stability. Figure 17 shows a simplified schematic of this type of amplifier. The input terminals of this amplifier are the bases of transistors Q1 and Q2. The output of transistors Q1 and Q2 are taken from their respective collectors and applied to the emitters of the common base PNPs Q4 and Q5. Transistors Q4 and Q5 act as cascode devices reducing the impedance at FIGURE 10. Integrator Compensation. VOUT V+ V– +In–In G = 1 b Ab 1 + Ab A(w ) = A(o) 1 + j( w w 1 ) 1 + j( ww 2 ) Pole Due to Integrator Second Pole I2I1 C2 A1C1 Q1 Q2 Q3 Q4 FIGURE 11. Transient Response Integrator Compensation. G = 1 – 1 b where w n = A(o) b w 1w 2 z = ( w 1 + w 2 2 A(o) b w 1w 2 1 w 2 A(o) b w 1 w 2 + j w A(o) b 1 w 1 1 w 2 + G = 1 – 1 b 1 w 2 w n2 + 2 z w w n Step Response: e0(t) = 1 b t–zw nt 1 – z 2 e1(t) 1 – sin ( w n 1 – z 2 t + cos–1 z ) ) ( ) [ ] FIGURE 12. Open Loop Gain, Closed Loop Gain, and Tran- sient Response Integrator Compensation. Case 2 Ab f11 f12 f2 Case 2 Case 1 Case 1 z = 0.2 Case 2 z = 0.8 GT Case 2 Case 1 eO(t) Case 1 f f As previously mentioned, there are two methods for com- pensating the open loop frequency response of this ampli- fier. The first method to be discussed is called integrator feedback as a capacitor is connected from the output stage to the drain of the input stage. Figure 10 shows a block diagram of this connection which more clearly demonstrates why it is called integrator compensation as an integrator is formed around the output gain stage of the amplifier. The advantage of integrator feedback is that the closed loop frequency response has all the poles in the denominator which means that the transient response is tolerant to parameter variation. As will be shown, another type of frequency compensation is called “doublet” or “pole-zero cancellation” which can have poor transient response due to small parameter varia- tions. Another benefit of integrator feedback is lower noise output as the integrator forms an output filter as contrasted to pole-zero cancellation which only forms an incomplete filter of the input stage. Figures 11 and 12 show the relation- ship between the frequency and time or transient response of a feedback amplifier that employs integrator feedback. Figures 13 through 16 illustrate the effect of a pole-zero mismatch. A pole-zero mismatch creates a “tail” or a long time constant settling term in the transient response. Pole- zero compensation is not as effective as integrator feedback in stabilizing an amplifier but should be considered as there are times when the integrator itself can become unstable. Pole-zero compensated amplifiers often have higher slew rates. 6 FIGURE 13. Pole-Zero Compensation in Op Amp. V+ V– +In–In G = 1 b Ab 1 + Ab A(w ) = A(o) 1 +( S w 1 ) 2-Pole Amplifier Pole-Zero Network VOUT 1 +( S w 1 ) 1 +( Sw 0 ) 1 +( S w 1' ) Q2Q1 R1 C1 A1 I1 I2 FIGURE 15. Pole-Zero Transient Response. A w 0 w 1 w 2 A A w 0 w 1 w 2 A w 1 < w 1' w 1 > w 1' FIGURE 14. Pole-Zero Compensation Bode Plots. G = 1 b ( Ab 1 + A b S w 1 1 + A( w ) = A(o) Step Response: (t) = 1 b w 1' – w 1 w 1 1 – ) [ ] ( S w 2 1 + ) ( S w 0 1 + ) ( S w 1' 1 + ) For simplicity assume A(o) w 0 >> w 2. ( S w 1 1 + A( w ) = A(o) ) ( S w 0 1 + ) ( S w 1' 1 + ) If w 1 » w 1' : G = 1 b Ab 1 + A b ( S(1 + A b ) w 01 + ) ( S w 1' 1 + ) ( S w 1' 1 + ) eOUT eIN A b 1 + A b e –w 1t – e–(1 + A b) w 0t 7 FIGURE 16. Pole-Zero Transient Response and Pole-Zero Mismatch. (t) = 1 b 1 – e–(1 + A b) w 0t –[ ]eOUT eIN A b 1 + A b w 1' – w 1 w 1 e–w 1t w 1' – w 1 w 1 e–w 1t 1 – e–(1 + A b) w 0t( ) “Tail” can be stabilized with a single capacitor thereby approximat- ing a single pole response without a settling “tail.” COMPARATOR The comparator is a common element in a signal processing system and it is used to sense a level and then generate a digital signal, either a “1” or a “0,” to report the result of that comparison to the rest of the system. Comparators can be implemented two different ways, either using a high gain amplifier or by using the latching type approach. Each type of comparator has advantages as will now be explained. When a high gain amplifier is used as a comparator, many low gain stages are cascoded to achieve high gain bandwidth product. A simplified example of a 20ns comparator is shown in Figure 18. This is in contrast to the way a wideband operational amplifier would be designed. A de- sign objective for a wideband operational amplifier would be to achieve high gain in a single stage to avoid accumulat- ing an excessive amount of phase shift. Feedback will be applied around an operational amplifier. It is important to achieve a phase characteristic approaching single pole re- sponse. Phase shift through a comparator is usually not important although high bandwidth and low propagation delay is desirable. The design of an open loop amplifier and a comparator are similar. The main differences are that comparators do not have to have stable, or linear, gain characteristics and the output is designed to be logic compat- ible such as TTL or ECL. Unlike a linear open loop ampli- the collectors of Q1 and Q2 while allowing the signal current to pass through transistors Q4 and Q5 with little attenuation. The term “folded cascode” refers to the fact that the PNP transistors not only serve as cascoding devices but also “fold” the signal down to a load connected to the negative power supply. Transistors Q8 and Q9 act as current source loads for transistors Q4 and Q5 thereby enabling the ampli- fier to achieve gains of up to 80 in a single stage. Emitter followers drive the output load in a similar manner to the method described for the FET operational amplifier. An additional benefit of this architecture is that the amplifier FIGURE 17. Folded Cascode. VBIASQ3 V– V+ Q11 Q10 VOUT+InQ2–In Q1 Q8 Q9 VBIAS Q4 Q5 VBIAS Q6 Q7 CCOMP R1 R2 R3 R4 R5 R7R6 R8 R9 8 –In+In VBIAS V+ Logic Out V– To V+ I3I2I1 I4 R11 R10 R8 R9 R7 R5 R6 R4 R2 R3 R1 I6 I5 Q16 Q15Q14 Q12Q11 Q10 Q13 Q9 Q6 Q8Q7 Q5 Q3 Q4 Q2Q1 FIGURE 18. High Speed Comparator. fier, a comparator is designed to operate in a non-linear mode with the output saturating at either logic extreme, depending upon whether the input signal exceeds the input reference. Additionally, care is taken when the intermediate st