OV7670_datasheet_英文

Advanced Information OV7670/OV7171 CMOS VGA (640x480) C Omni ision® General Description The OV7670/OV7171 CAMERACHIPTM is a low voltage CMOS image sensor that provides the full functionality of a single-chip VGA camera and image processor in a small footprint package. The OV7670/OV7171 provides full-frame, sub-sampled or windowed 8-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface. This product has an image array capable of operating at up to 30 frames per second (fps) in VGA with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control and more, are also programmable through the SCCB interface. In addition, OmniVision CAMERACHIPs use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise (FPN), smearing, blooming, etc., to produce a clean, fully stable color image. Features • High sensitivity for low-light operation • Low operating voltage for embedded portable apps • Standard SCCB interface compatible with I2C interface • Output support for Raw RGB, RGB (GRB 4:2:2, RGB565/555/444), YUV (4:2:2) and YCbCr (4:2:2) formats • Supports image sizes: VGA, CIF, and any size scaling down from CIF to 40x30 • VarioPixel® method for sub-sampling • Automatic image control functions including: Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Band Filter (ABF), and Automatic Black-Level Calibration (ABLC) • Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), and anti-blooming • ISP includes noise reduction and defect correction • Supports LED and flash strobe mode • Supports scaling • Lens shading correction • Flicker (50/60 Hz) auto detection • Saturation level auto adjust (UV adjust) • Edge enhancement level auto adjust • De-noise level auto adjust Ordering Information Pb Note: The OV7670/OV7171 uses a lead-free package. Version 1.3, April 5, 2006 P Product Package OV07670-VL2A (Color, lead-free) 24 pin CSP2 OV07171-VL2A (B&W, lead-free) 24 pin CSP2 Preliminary Datasheet AMERACHIPTM with OmniPixel ® Technology Applications • Cellular and Picture Phones • Toys • PC Multimedia • Digital Still Cameras Key Specifications Figure 1 OV7670/OV7171 Pin Diagram (Top View) Active Array Size 640 x 480 Power Supply Digital Core 1.8VDC +10% Analog 2.45V to 3.0V I/O 1.7V to 3.0Va a. I/O power should be 2.45V or higher when using the internal regulator for Core (1.8V); otherwise, it is necessary to provide an external 1.8V for the Core power supply. Power Requirements Active 60 mW typical(15fps VGA YUV format) Standby < 20 µA Temperature Range Operation -30°C to 70°C Stable Image 0°C to 50°C Output Formats (8-bit) • YUV/YCbCr 4:2:2 • RGB565/555/444 • GRB 4:2:2 • Raw RGB Data Lens Size 1/6" Chief Ray Angle 25° Maximum Image Transfer Rate 30 fps for VGA Sensitivity 1.3 V/(Lux • sec) S/N Ratio 46 dB Dynamic Range 52 dB Scan Mode Progressive Electronics Exposure Up to 510:1 (for selected fps) Pixel Size 3.6 µm x 3.6 µm Dark Current 12 mV/s at 60°C Well Capacity 17 K e Image Area 2.36 mm x 1.76 mm Package Dimensions 3785 µm x 4235 µm OV7670/OV7171 AGND SIO_C A1 A2 A4A3 D1 D0 D3 D2 A5 B1 B2 B4B3 B5 C1 D1 D2 AVDD SIO_D PWDN VSYNC VREF2 HREF DVDD C2 VREF1 E1 E2 E4E3 E5 roprietary to OmniVision Technologies 1 D4 D5 F1 F2 F4F3 F5 DOGNDDOVDD PCLK STROBE RESET# D6 XCLK D7 OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Functional Description 2 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006 Figure 2 shows the functional block diagram of the OV7670/OV7171 image sensor. The OV7670/OV7171 includes: • Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode) • Analog Signal Processor • A/D Converters • Test Pattern Generator • Digital Signal Processor (DSP) • Image Scaler • Timing Generator • Digital Video Port • SCCB Interface • LED and Strobe Flash Control Output Figure 2 Functional Block Diagram A/D G D[7:0] B R 50/60 Hz Auto Detect Test Pattern Generator Video Port Image Scaler DSP Buffer Buffer (Lens shading correction, de-noise, white/ black pixel correction, auto white balance, etc.) FIFOAnalog Processing Image Array (656 x 488) Column Sense Amp Exposure/Gain Detect Exposure/Gain Control SCCB Interface Registers Video Timing GeneratorClock SIO_C SIO_DSTROBE PWDNRESET#VSYNCPCLKHREFXCLK R ow S el ec t Functional Description P Omni ision Version 1.3, April 5, 2006 Image Sensor Array The OV7670/OV7171 sensor has an image array of 656 x 488 pixels for a total of 320,128 pixels, of which 640 x 480 pixels are active (307,200 pixels). Figure 3 shows a cross-section of the image sensor array. Figure 3 Image Sensor Array Timing Generator In general, the timing generator controls the following functions: • Array control and frame generation • Internal timing signal generation and distribution • Frame rate timing • Automatic Exposure Control (AEC) • External timing outputs (VSYNC, HREF/HSYNC, and PCLK) Analog Signal Processor This block performs all analog image functions including: • Automatic Gain Control (AGC) • Automatic White Balance (AWB) A/D Converters After the Analog Processing block, the bayer pattern Raw signal is fed to a 10-bit analog-to-digital (A/D) converter shared by G and BR channels. This A/D converter operates at speeds up to 12 MHz and is fully synchronous to the pixel rate (actual conversion rate is related to the frame rate). In addition to the A/D conversion, this block also has the following functions: • Digital Black-Level Calibration (BLC) • Optional U/V channel delay • Additional A/D range controls In general, the combination of the A/D Range Multiplier and A/D Range Control sets the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application. Glass Microlens Blue Green Red roprietary to OmniVision Technologies 3 Test Pattern Generator The Test Pattern Generator features the following: • 8-bar color bar pattern • Fade-to-gray color bar pattern • Shift "1" in output pin Digital Signal Processor (DSP) This block controls the interpolation from Raw data to RGB and some image quality control. • Edge enhancement (a two-dimensional high pass filter) • Color space converter (can change Raw data to RGB or YUV/YCbCr) • RGB matrix to eliminate color cross talk • Hue and saturation control • White/black pixel correction • De-noise • Lens shading correction • Programmable gamma control • Transfer 10-bit data to 8-bit Image Scaler This block controls all output and data formatting required prior to sending the image out. This block scales YUV/RGB output from VGA to CIF and almost any size under CIF. Digital Video Port Register bits COM2[1:0] increase IOL/IOH drive current and can be adjusted as a function of the customer’s loading. SCCB Interface The Serial Camera Control Bus (SCCB) interface controls the CAMERACHIP operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port. LED and Strobe Flash Control Output The OV7670/OV7171 has a Strobe mode that allows it to work with an external flash and LED. Pin DescriptionOmni ision Pin Description Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 4 Table 1 Pin Description Pin Number Name Pin Type Function/Description A1 AVDD Power Analog power supply A2 SIO_D I/O SCCB serial interface data I/O A3 SIO_C Input SCCB serial interface clock input A4 D1a a. D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB) Output YUV/RGB video component output bit[1] A5 D3 Output YUV/RGB video component output bit[3] B1 PWDN Input (0)b b. Input (0) represents an internal pull-down resistor. Power Down Mode Selection 0: Normal mode 1: Power down mode B2 VREF2 Reference Reference voltage - connect to ground using a 0.1 µF capacitor B3 AGND Power Analog ground B4 D0 Output YUV/RGB video component output bit[0] B5 D2 Output YUV/RGB video component output bit[2] C1 DVDD Power Power supply (+1.8 VDC) for digital logic core C2 VREF1 Reference Reference voltage - connect to ground using a 0.1 µF capacitor D1 VSYNC Output Vertical sync output D2 HREF Output HREF output E1 PCLK Output Pixel clock output E2 STROBE Output LED/strobe control output E3 XCLK Input System clock input E4 D7 Output YUV/RGB video component output bit[7] E5 D5 Output YUV/RGB video component output bit[5] F1 DOVDD Power Digital power supply for I/O (1.7V ~ 3.0V) F2 RESET# Input Clears all registers and resets them to their default values. 0: Reset mode 1: Normal mode F3 DOGND Power Digital ground F4 D6 Output YUV/RGB video component output bit[6] F5 D4 Output YUV/RGB video component output bit[4] OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Electrical Characteristics 5 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006 NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage. Table 2 Absolute Maximum Ratings Ambient Storage Temperature -40ºC to +95ºC Supply Voltages (with respect to Ground) VDD-A 4.5 V VDD-C 3 V VDD-IO 4.5 V All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+0.5V Lead-free Temperature, Surface-mount process 245ºC Table 3 DC Characteristics (-30°C < TA < 70°C) Symbol Parameter Condition Min Typ Max Unit VDD-A DC supply voltage – Analog – 2.45 2.75 3.0 V VDD-C DC supply voltage – Digital Core – 1.62 1.8 1.98 V VDD-IO DC supply voltage – I/O power – 1.7 – 3.0V V IDDA Active (Operating) Current See Note a a. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps YUV output, no I/O loading 10 + 8b b. IDD-C = 10mA, IDD-A = 8mA, without loading mA IDDS-SCCB Standby Current See Note c c. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby 1 mA IDDS-PWDN Standby Current 10 20 µA VIH Input voltage HIGH CMOS 0.7 x VDD-IO V VIL Input voltage LOW 0.3 x VDD-IO V VOH Output voltage HIGH CMOS 0.9 x VDD-IO V VOL Output voltage LOW 0.1 x VDD-IO V IOH Output current HIGH See Note d d. Standard Output Loading = 25pF, 1.2KΩ 8 mA IOL Output current LOW 15 mA IL Input/Output Leakage GND to VDD-IO ± 1 µA Electrical CharacteristicsOmni ision Table 4 Functional and AC Characteristics (-30°C < T < 70°C) Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 6 A Symbol Parameter Min Typ Max Unit Functional Characteristics A/D Differential Non-Linearity + 1/2 LSB A/D Integral Non-Linearity + 1 LSB AGC Range 30 dB Red/Blue Adjustment Range 12 dB Inputs (PWDN, CLK, RESET#) fCLK Input Clock Frequency 10 24 48 MHz tCLK Input Clock Period 21 42 100 ns tCLK:DC Clock Duty Cycle 45 50 55 % tS:RESET Setting time after software/hardware reset 1 ms tS:REG Settling time for register change (10 frames required) 300 ms SCCB Timing (see Figure 4) fSIO_C Clock Frequency 400 KHz tLOW Clock Low Period 1.3 μs tHIGH Clock High Period 600 ns tAA SIO_C low to Data Out valid 100 900 ns tBUF Bus free time before new START 1.3 μs tHD:STA START condition Hold time 600 ns tSU:STA START condition Setup time 600 ns tHD:DAT Data-in Hold time 0 μs tSU:DAT Data-in Setup time 100 ns tSU:STO STOP condition Setup time 600 ns tR, tF SCCB Rise/Fall times 300 ns tDH Data-out Hold time 50 ns Outputs (VSYNC, HREF, PCLK, and D[7:0] (see Figure 5, Figure 6, Figure 7, Figure 9, and Figure 10) tPDV PCLK[↓] to Data-out Valid 5 ns tSU D[7:0] Setup time 15 ns tHD D[7:0] Hold time 8 ns tPHH PCLK[↓] to HREF[↑] 0 5 ns tPHL PCLK[↓] to HREF[↓] 0 5 ns AC Conditions: • VDD: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V • Rise/Fall Times: I/O: 5ns, Maximum SCCB: 300ns, Maximum • Input Capacitance: 10pf • Output Loading: 25pF, 1.2KΩ to 2.5V • fCLK: 24MHz OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Timing Specifications 7 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006 Figure 4 SCCB Timing Diagram Figure 5 Horizontal Timing Figure 6 VGA Frame Timing SIO_C tSU:STA tHD:STA SIO_D IN SIO_D OUT tF tLOW tHIGH tR tHD:DAT tSU:DAT tAA tDH tBUF tSU:STO PCLK D[7:0] Last Byte First Byte Last Byte tHD tSU tPCLK tPDV HREF (Row Data) tPHLtPHL VSYNC D[7:0] HREF 510 x tLINE Row 1 Row 2 Row 479Row 0 Invalid Data Invalid Data HSYNC 3 x tLINE 17 tLINE tLINE = 784 tP 144 tP P0 - P639 80 tP 45 tP 640 tP 19 tP NOTE: For Raw data, tP = tPCLK 480 x tLINE 10 tLINE For YUV/RGB, tP = 2 x tPCLK Timing SpecificationsOmni ision Figure 7 QVGA Frame Timing Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 8 Figure 8 QQVGA Frame Timing Figure 9 CIF Frame Timing Figure 10 QCIF Frame Timing QVGA HREF VGA HREF (see Figure 7, VGA Frame Timing) QQVGA HREF (1 from 4, 120 from 480) VGA HREF (see Figure 7, VGA Frame Timing) CIF HREF (3 from 5) VGA HREF (see Figure 7, VGA Frame Timing) QCIF HREF (3 from 5) QVGA HREF (see Figure 7, QVGA Frame Timing) OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Figure 11 RGB 565 Output Timing Diagram 9 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006 Figure 12 RGB 555 Output Timing Diagram PCLK D[7:0] Last Byte First Byte Last Byte tHD tSU tPCLK tPDV HREF (Row Data) tPHLtPHL First Byte Second Byte D[5] D[4] D[3] D[2] D[7] D[6] D[1] D[0] R0 G5 R4 G3 D[5] D[4] D[3] D[2] D[7] D[6] D[1] D[0] G0 B4 G2 B0 PCLK D[7:0] Last Byte First Byte Last Byte tHD tSU tPCLK tPDV HREF (Row Data) tPHLtPHL First Byte Second Byte D[5] D[4] D[3] D[2] D[7] D[6] D[1] D[0] D[5] D[4] D[3] D[2] D[7] D[6] D[1] D[0] R0 X R4 G4 G3 G0 B4 G2 B0 Timing SpecificationsOmni ision Figure 13 RGB 444 Output Timing Diagram Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 10 PCLK D[7:0] Last Byte First Byte Last Byte tHD tSU tPCLK tPDV HREF (Row Data) tPHLtPHL First Byte Second Byte D[5] D[4] D[3] D[2] D[7] D[6] D[1] D[0] D[5] D[4] D[3] D[2] D[7] D[6] D[1] D[0] R 2 X R 3 R 1 R 0 G0 B3 B2 B1 G 3 G 2 G 1 B0 OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Register Set 11 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006 Table 5 provides a list and description of the Device Control registers contained in the OV7670/OV7171. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read. Table 5 Device Control Register List Address (Hex) Register Name Default (Hex) R/W Description 00 GAIN 00 RW AGC – Gain control gain setting Bit[7:0]: AGC[7:0] (see VREF[7:6] (0x03) for AGC[9:8]) • Range: [00] to [FF] 01 BLUE 80 RW AWB – Blue channel gain setting • Range: [00] to [FF] 02 RED 80 RW AWB – Red channel gain setting • Range: [00] to [FF] 03 VREF 00 RW Vertical Frame Control Bit[7:6]: AGC[9:8] (see GAIN[7:0] (0x00) for AGC[7:0]) Bit[5:4]: Reserved Bit[3:2]: VREF end low 2 bits (high 8 bits at VSTOP[7:0] Bit[1:0]: VREF start low 2 bits (high 8 bits at VSTRT[7:0] 04 COM1 00 RW Common Control 1 Bit[7]: Reserved Bit[6]: CCIR656 format 0: Disable 1: Enable Bit[5:2]: Reserved Bit[1:0]: AEC low 2 LSB (see registers AECHH for AEC[15:10] and AECH for AEC[9:2]) 05 BAVE 00 RW U/B Average Level Automatically updated based on chip output format 06 GbAVE 00 RW Y/Gb Average Level Automatically updated based on chip output format 07 AECHH 00 RW Exposure Value - AEC MSB 5 bits Bit[7:6]: Reserved Bit[5:0]: AEC[15:10] (see registers AECH for AEC[9:2] and COM1 for AEC[1:0]) 08 RAVE 00 RW V/R Average Level Automatically updated based on chip output format 09 COM2 01 RW Common Control 2 Bit[7:5]: Reserved Bit[4]: Soft sleep mode Bit[3:2]: Reserved Bit[1:0]: Output Drive Capability 00: 1x 01: 2x 10: 3x 11: 4x Register SetOmni ision Table 5 Device Control Register List (Continued) Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 12 0A PID 76 R Product ID Number MSB (Read only) 0B VER 73 R Product ID Number LSB (Read only) 0C COM3 00 RW Common Control 3 Bit[7]: Reserved Bit[6]: Output data MSB and LSB swap Bit[5]: Tri-state option for output clock at power-down period 0: Tri-state at this period 1: No tri-state at this period Bit[4]: Tri-state option for output data at power-down period 0: Tri-state at this period 1: No tri-state at this period Bit[3]: Scale enable 0: Disable 1: Enable - if set to a pre-defined format (see COM7[5:3]), then COM14[3] must be set to 1 for manual adjustment. Bit[2]: DCW enable 0: Disable 1: Enable - if set to a pre-defined format (see COM7[5:3]), then COM14[3] must be set to 1 for manual adjustment. Bit[1:0]: Reserved 0D COM4 00 RW Common Control 4 Bit[7:6]: Reserved Bit[5:4]: Average option (must be same value as COM17[7:6]) 00: Full window 01: 1/2 window 10: 1/4 window 11: 1/4 window Bit[3:0]: Reserved 0E COM5 01 RW Common Control 5 Bit[7:0]: Reserved 0F COM6 43 RW Common Control 6 Bit[7]: Output of optical black line option 0: Disable HREF at optical black 1: Enable HREF at optical black Bit[6:2]: Reserved Bit[1]: Reset all timing when format changes 0: No reset 1: Resets timing Bit[0]: Reserved 10 AECH 40 RW Exposure Value Bit[7:0]: AEC[9:2] (see registers AECHH for AEC[15:10] and COM1 for AEC[1:0]) Address (Hex) Register Name Default (Hex) R/W Description OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Table 5 Device Control Register List (Continued) 13 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006 11 CLKRC 80 RW Internal Clock Bit[7]: Reserved Bit[6]: Use external clock directly (no clock pre-scale available) Bit[5:0]: Internal clock pre-scalar F(internal clock) = F(input clock)/(Bit[5:0]+1) • Range: [0 0000] to [1 1111] 12 COM7 00 RW Common Control 7 Bit[7]: SCCB Register Reset 0: No change 1: Resets all registers to default values Bit[6]: Reserved Bit[5]: Output format - CIF selection Bit[4]: Output format - QVGA selection Bit[3]: Output format - QCIF selection Bit[2]: Output format - RGB selection (see below) Bit[1]: Color bar 0: Disable 1: Enable Bit[0]: Output format - Raw RGB (see below) COM7[2] COM7[0] YUV 0 0 RGB 1 0 Bayer RAW 0 1 Processed Bayer RAW 1 1 13 COM8 8F RW Common Control 8 Bit[7]: Enable fast AGC/AEC algorithm Bit[6]: AEC - Step size limit 0: Step size is limited to vertical blank 1: Unlimited step size Bit[5]: Banding filter ON/OFF - In order to turn ON the banding filter, BD50ST (0x9D) or BD60ST (0x9E