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AN-877_en.pdf

AN-877_en

katgjko
2012-05-10 0人阅读 举报 0 0 暂无简介

简介:本文档为《AN-877_enpdf》,可适用于IT/计算机领域

ANAPPLICATIONNOTEOneTechnologyWay•POBox•Norwood,MA,USA•Tel:•Fax:•wwwanalogcomInterfacingtoHighSpeedADCsviaSPIbytheHighSpeedConverterDivisionINTRODUCTIONDEFINITIONThisapplicationnotedescribeshowtousetheSPIportonTheSPIportconsistsofthreepins:theserialclockpin(SCLK),AnalogDevices,Inc,highspeedconvertersInaddition,thistheserialdatainputoutputpin(SDIO),andthechipselectbarapplicationnotedefinestheelectrical,timing,andproceduralpin(CSB)Optionally,somechipsmayimplementaserialdatarequirementsforinterfacingtothesedevicesTheimplementaoutpin(SDO),whichisreferredtoaswiremodeTominimizetioniscompatiblewithindustrystandardSPIportsandpincount,mostchipsomitthispinHowever,ifitisincluded,itisemploys,atminimum,awiremodeandoptionalchipselectusedonlyforreadingdatafromthedeviceCSBSCLKSCLKSDIOSDIOCSBSPICONTROLLERCONVERTERINTERFACEFigureSingleDeviceControlinWireModeCSBCSBCSBSCLKCONVERTERSPIINTERFACECONTROLLERSCLKDEVICESDIOSDIOCSBSCLKCONVERTERINTERFACESDIODEVICEFigureMultipleDeviceControlinWireModeRevA|PageofANTABLEOFCONTENTSIntroductionDefinitionSPIPortPinsSerialClock(SCLK)SerialDataInputOutput(SDIO)ChipSelectBar(CSB)SerialDataOut(SDO)FormatInstructionPhaseReadWriteWordLengthStreamingAddressBitsDataPhaseBitOrderDetectionofSPIModeandPinModeHardwareInterfacingChipProgrammingConfigurationRegister(X)BitSDOActiveBitLSBFirstBitSoftResetControlBitReservedTransferRegister(MasterSlaveLatching)(xFF)BitSoftwareTransferBitEnableHardwareTransferChipID(x)ChipGrade(x)DeviceIndexing(xandx)BittoBitAuxiliaryDevicesREVISIONHISTORYInitialVersiontoRevAUpdatedFormatUniversalChangestoTransferRegisterSectionChangestoFigureAddedTableAddedPLLControl(xA)SectionChangestoTableRevision:InitialVersionBittoBitMainConvertersWritingReadingProgramRegistersModes(x)Clock(x)PLLControl(x)ClockDivider(xB)EnhancementModes(xC)OutputTestModes(xD)BuiltInSelfTest(xE)AnalogInput(xF)OffsetAdjust(x)GainAdjust(x)OutputMode(x)OutputSettings(x)ClockDividerPhase(x)OutputDelayAdjust(x)ReferenceAdjust(x)UserTestPatterns(xThroughx)SerialDataControlChannel(x)SerialChannelPowerDown(x)MISRRegisters(xandx)Features(xA)HighPass(xB)AnalogIn(xC)CrossPointSwitch(xD)ProgrammingExampleControlRegisterRevA|PageofANSPIPORTPINSThefollowingsectionsdescribedtheSPIportpinsCaution:RefertospecificADCdatasheetstodeterminethenominalandabsolutemaximumlogicvoltagesSERIALCLOCK(SCLK)TheSCLKpinistheserialshiftclockinpinThispinisimplementedwithaSchmitttrigger,tominimizesensitivitytonoiseontheclockline,anditispulledlowbyanominalkΩresistortogroundThispinmaystalleitherhighorlowSCLKisusedtosynchronizeserialinterfacereadsandwritesInputdataisregisteredontherisingedgeofthisclockandoutputdatatransmissionsareregisteredonthefallingedgeTheminimumguaranteedspeedoftheSCLKisMHz(tCLKns)Thetypicalholdtime(tDH)isns,andaminimumsetuptime(tDS)ofnsisrequiredbetweenSCLKandSDIO(Seethespecificdevicedatasheettodeterminetheexactinterfacetimingrequirements)Tooptimizeinternalandexternaltiming,thebusiscapableofturningaroundthestateoftheSDIOlineinhalfanSCLKcycleThismeansthat,aftertheaddressinfor­mationispassedtotheconverterrequestingaread,theSDIOlineistransitionedfromaninputtoanoutputwithinonehalfofaclockcycleThisensuresthatbythetimethefallingedgeofthenextclockcycleoccurs,datacanbesafelyplacedonthisseriallineforthecontrollertoreadIftheexternalcontrollerisinsufficientlyfasttokeepupwiththeADCSPIport,theexternaldevicecanstalltheclocklinetoaddadditionaltimeallowingforexternaltimingissuesSERIALDATAINPUTOUTPUT(SDIO)TheSDIOpinisadualpurposepinThetypicalroleforthispinisaseitheraninputoranoutput,dependingontheinstructionbeingsent(readorwrite)andtherelativeposition(instructionordataphase)inthetimingframeDuringthefirstphaseofawriteoraread,thispinfunctionsasaninputthatpassesinformationtotheinternalstatemachineIfthecommandisdeterminedtobeareadcommand,thestatemachinechangesthispin(SDIO)toanoutput,whichthenpassesdatabacktothecontroller(SeetENSDIOandtDISSDIOinTable)IfthedeviceincludesanSDOpinandtheconfigurationregisterissettotakeadvantageofit,theSDObecomesactiveinsteadoftheSDIOpinchangingtoanoutputAtallothertimes,theSDOpinremainsinahighimpedancestateIfthecommandisdeterminedtobeawritecommand,theSDIOpinremainsaninputforthedurationoftheinstructionCHIPSELECTBAR(CSB)CSBisanactivelowcontrolthatgatesthereadandwritecyclesThereareseveralmodesinwhichtheCSBcanbeoperatedForsituationswherethecontrollerhasachipselectoutputorothermeansofselectingmultipledevices,thispincanbetiedtotheCSBlineWhenthislineislow,thedeviceisselectedandinfor­mationontheSCLKandSDIOlinesisprocessedIfthispinishigh,thedeviceignoresanyinformationontheSCLKandSDIOlinesInthismanner,multipledevicescanbeconnectedtotheSPIportIncaseswhereonlyonedeviceisconnected,theCSBlinecanbeoptionallytiedlowandthedeviceisperma­nentlyenabled(TyingtheCSBlinelowexcludesthepossibilityofresettingthedeviceifanerroroccursontheport)TheCSBlinecanalsobetiedhightoenablesecondaryfunctionoftheSPIport(SeetheDetectionofSPIModeandPinModesectionformoredetails)CSBisahighimpedanceline,pulledhighbyanominalkΩresistorCSBmaystallhigh,thatis,remainhighformultipleclockcycles(seeFigure)insomeconfigurationstoallowforadditionalexternaltimingIfthreeorfewerwords(notcountinginstructioninformation)arebeingtransmittedthroughtheinterfaceatatime,CSBmaystallhighbetweenbytes,includingthebytesoftheinstructioninformationIfCSBstallshighinthemiddleofabyte,thestatemachineisresetandthecontrollerreturnstotheidlestate,awaitingthetransmissionofanewinstructionThismechanismallowsrestorationafterafaulthasbeendetectedTodetectthereset,atleastoneandnomorethansevenserialclocksmustoccurOncethestatemachinehasenteredtheidlestate,thenextfallingedgeoftheCSBinitiatesanewtransmissioncycleSomedevicesimplementsecondaryfunctionswiththeSPIpinsTypically,thesefunctionsincludeoutputdataformat,dutycyclestabilizer,orothercommonfeaturesThesepinfunctionsareenabledbytheCSBpinIftheCSBpinistiedhigh,theSPIfunctionsareplacedinahighimpedancemodeInthismode,secondaryfunctionsarethenturnedon,allowingcontroloffeaturesonchip,withoutrequiringtheSPItooperateThesefeaturesvarybydeviceTherefore,theindividualdevicedatasheetmustbeconsultedtodetermineifthisfeatureissupportedandwhatitcontrolsForapplicationstobecontrolledbytheSPIport,thesecondaryfunctiontakespriorityuntilthedevicehasbeenaccessedbytheSPIportByextension,anyactivityontheSCLK,SDIO,andSDO(ifprovided)isinterpretedasasecondaryfunctionuntilthechiphasbeenaccessedbytheSPIportTherefore,thechipneedstobeinitializedassoonafterpowerupaspractical(SeetheDetectionofSPIModeandPinModesectionformoredetails)RevA|PageofANSERIALDATAOUT(SDO)TodetermineifadevicesupportstheSDOpin,refertothedevicedatasheetIfSDOispresent,itisinahighimpedancestate,unlessdataisactivelybeingshiftedonthispintoallowtyingmultipledevicestogetheratthereceivingendAdditionally,dataisshiftedoutonthefirstfallingedgeofSCLKaftertheinstructtionphaseiscompleteWhendataisreturnedtothecontroller,theinformationisplacedintheoutputshifters,withinthetimeperiodbetweenthelastrisingedgeofSCLKassociatedwiththeinstructionphaseandtheimmediatelynextfallingedgeThiscanbenominallynswhenoperatingatMHzCSBCSBSCLKSCLKSDOSDOSDISDIOSPIHIGHZWHENCONTROLLERCONVERTERINTERFACENOTUSEDORINACTIVETableSerialTimingSpecificationsSymbolDescriptiontDSSetuptimebetweendataandrisingedgeofSCLKtDHHoldtimebetweendataandrisingedgeofSCLKtCLKPeriodoftheclocktSSetuptimebetweenCSBandSCLKtHHoldtimebetweenCSBandSCLKtHIMinimumperiodthatSCLKneedstobeinalogichighstatetLOMinimumperiodthatSCLKneedstobeinalogiclowstatetENSDIOMinimumtimeittakestheSDIOpintoswitchbetweenaninputandanoutputrelativetoSCLKfallingedgetDISSDIOMinimumtimeittakestheSDIOpintoswitchbetweenanoutputandaninput,relativetoSCLKrisingedgeSeedevicedatasheetforminimumandmaximumratingsFigureWireControlCSBSCLKDON'TCAREDON'TCAREtStDStDHtHItLOtCLKtHWWAAAAAADDDDDDRWSDIODON'TCAREDON'TCAREFigureSetupandHoldTimingMeasurementsCSBSCLKSDIODON'TCAREWAAAAAAAAAAAAARWWDON'TCAREDON'TCAREDDDDDDDDDON'TCAREDDDDDDDDDDDDDDDDBITINSTRUCTIONHEADERREGISTER(N)DATAREGISTER(N–)DATAREGISTER(N–)DATAMSBFIRSTBITINSTRUCTION,BYTESDATAWITHSTALLINGFigureMSBFirstInstructionandDatawithStallingCSBSCLKSDIODON'TCAREWAAAAAAAAAAAAARWWDON'TCAREBITINSTRUCTIONHEADERREGISTER(N–)DATAREGISTER(N–)DATARWWDRIVENOUTPUTDATASTREAMMSBFIRSTBITREADINSTRUCTION,BYTESDATAWIREREGISTER(N)DATAREGISTER(N–)DATASCLKSCLKOUTPUTDRIVEROFFOUTPUTDRIVERONOUTPUTDRIVERONOUTPUTDRIVEROFFtENSDIOtDISSDIOFigureTypicalSDIOOutputEnableAndDisableTimingRevA|PageofANFORMATThefallingedgeofCSB,inconjunctionwiththerisingedgeWhenthefirstbitinthedatastreamislow,awritephaseisenteredofSCLK,determinesthestartofframingOncetheAtthecompletionoftheinstructionphase,theinternalstatebeginningoftheframehasbeendetermined,timingismachineusestheinformationprovidedtodecodetheinternalstraightforwardThefirstphaseofthetransferistheaddresstobewrittenAlldataaftertheinstructionisshiftedintheinstructionphase,whichconsistsofbitsfollowedbydataSDIOpinandsenttothetargetaddressesOncealldataspecifiedthatcanbeofvariablelengthsinmultiplesofbitsIfthebythewordlengthhasbeentransferred,thestatemachinereturnsdeviceisconfiguredwithCSBtiedlow,framingbeginswithtoidlemodeandawaitsthenextinstructionphasethefirstrisingedgeofSCLKIneitherreadorwritemode,theprocesscontinuesuntilthewordINSTRUCTIONPHASElengthisreachedoruntiltheCSBlineisliftedIftheendofTheinstructionphaseisthefirstbitstransmittedAsshownmemoryisreached(eitherxorxFF),therolloveroccursandthenextaddressprocessedisx,iftheaddressisinFigureandFigure,theinstructionphaseisdividedintoanumberofbitfieldsincrementing,orxFF,iftheaddressisdecrementingREADWRITEWORDLENGTHWandWrepresentthenumberofdatabytestotransferforThefirstbitinthestreamisthereadwriteindicatorbit(RW)eitherreadorwriteThevaluerepresentedbyW:WistheWhenthisbitishigh,areadisbeingrequestedAtthecom­numberofbytestotransferIfthenumberofbytestotransferispletionoftheinstructionphase(thefirstbits),theinternalthreeorless(,,or),CSBcanstallhighonbytestatemachineusestheinformationprovidedtodecodetheboundariesStallingonanonbyteboundaryterminatestheinternaladdresstobereadThedirectionoftheSDIOlineiscommunicationscycleIfthesebitsare,datacanbetransferredchangedfrominputtooutput,andtheappropriatenumberofuntilCSBtransitionshighCSBisnotallowedtostallduringthewordsdefinedbythewordlengthareshiftedoutofthedevicestreamingprocessOncestreaminghasbegun(definedasbeyond(seetheWordLengthsection)Ifthedeviceisequippedwithanthethirddatabyte),CSBisnotallowedtoreturnhighuntiltheSDOandtheconfigurationregisterisappropriatelyset,theoperationiscompleteWhenCSBdoesgohigh,streamingisSDOlineistakenoutofhighimpedanceanddataispassedoutterminated,andthenexttimeCSBgoeslow,anewinstructiontheSDOpininsteadoftheSDIOpinOncealldataspecifiedbycycleisinitiatedIfCSBgoeshighonanonbitboundary,thethewordlengthhasbeenshiftedout,thestatemachinereturnscommunicationscycleisterminated,andanyincompletebytestoidlemodeandawaitsthenextinstructionphasearelostCompleteddatabytes,however,areproperlyhandledCSBWAAAAAAAAAAAAARWWDON'TCAREDON'TCARECLSDIOBITINSTRUCTIONHEADERFigureInstructionPhaseBitFieldRevA|PageofANTableW:WCSBSettingActionStallingbyteofdatacanbetransferredOptionalbytesofdatacanbetransferredOptionalbytesofdatacanbetransferredOptionalormorebytesofdatacanbeNotransferredCSBmustbeheldlowforentiresequenceotherwise,thecycleisterminated,andaninstructioncycleisanticipatedwhenCSBreturnslowIfthevaluerepresentedbyWandWis,onebyteofdataistransferredIfthevaluerepresentedbyWandWis,twobytesofdataaretransferredIfthevaluerepresentedbyWandWis,thenthreebytesofdataaretransferredFollowingcompletionofthedatatransfer,thestatemachinereturnstoidlestate,awaitingthenextinstructionphaseSTREAMINGIfthevaluerepresentedbyWandWis,dataisconstantlystreamedtothedeviceAslongasCSBremainslow,thepartcontinuestoacceptnewdata,startingwiththeinitialaddressandcontinuingtothenextaddresswitheachnewwordreceivedItisrecommendedthatstreamingnotbecombinedwiththeCSBlinephysicallytiedlow,becausestreamingcanonlyb

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