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首页 FPGA设计秘笈.pdf

FPGA设计秘笈.pdf

FPGA设计秘笈.pdf

上传者: huihuang_70 2012-05-09 评分 0 0 0 0 0 0 暂无简介 简介 举报

简介:本文档为《FPGA设计秘笈pdf》,可适用于IT/计算机领域,主题内容包含DesignRecipesforFPGAsPrelimsHqxd:PMPageiThispageintentionallyleftblankDesi符等。

DesignRecipesforFPGAsPrelimsHqxd:PMPageiThispageintentionallyleftblankDesignRecipesforFPGAsDrPeterRWilsonAMSTERDAM•BOSTON•HEIDELBERG•LONDON•NEWYORK•OXFORDPARIS•SANDIEGO•SANFRANCISCO•SINGAPORE•SYDNEY•TOKYONewnesisanimprintofElsevierPrelimsHqxd:PMPageiiiNewnesisanimprintofElsevierLinacreHouse,JordanHill,OxfordOXDPCorporateDrive,Suite,BurlingtonMAFirstpublishedCopyright,PeterRWilsonAllrightsreservedTherightofPeterRWilsontobeidentifiedastheauthorofthisworkhasbeenassertedinaccordancewiththeCopyright,DesignsandPatentsActNopartofthispublicationmaybereproduced,storedinaretrievalsystemortransmittedinanyformorbyanymeanselectronic,mechanical,photocopying,recordingorotherwisewithoutthepriorwrittenpermissionofthepublisherPermissionmaybesoughtdirectlyfromElsevier’sScienceTechnologyRightsDepartmentinOxford,UK:phone()()fax()()email:permissionselseviercomAlternativelyyoucansubmityourrequestonlinebyvisitingtheElsevierwebsiteathttp:elseviercomlocatepermissions,andselectingObtainingpermissiontouseElseviermaterialNoticeNoresponsibilityisassumedbythepublisherforanyinjuryandordamagetopersonsorpropertyasamatterofproductsliability,negligenceorotherwise,orfromanyuseoroperationofanymethods,products,instructionsorideascontainedinthematerialhereinBritishLibraryCataloguinginPublicationDataWilson,PeterRDesignrecipesforFPGAsFieldprogrammablegatearrays–DesignandconstructionITitleLibraryofCongressNumber:ISBN:PrintedandboundinGreatBritainbyMPGBooksLtd,BodminCornwallCoverimageofanActelRTAXSFPGAchipsuppliedcourtesyofActel–wwwactelcomForinformationonallNewnespublicationsvisitourwebsiteatwwwbookselseviercomPrelimsHqxd:PMPageivThiseBookdoesnotincludeancillarymediathatwaspackagedwiththeprintedversionofthebookForHeatherPrelimsHqxd:PMPagevThispageintentionallyleftblankContentsAcknowledgementsxviiPrefacexixListofFiguresxxiPartOverviewChapterIntroductionWhyFPGASChapterAnFPGAPrimerIntroductionFPGAevolutionProgrammablelogicdevicesFieldprogrammablegatearraysFPGAdesigntechniquesDesignconstraintsusingFPGAsSummaryChapterAVHDLPrimer:TheEssentialsIntroductionEntity:modelinterfaceEntitydefinitionPortsGenericsConstantsEntityexamplesArchitecture:modelbehaviorBasicdefinitionofanarchitectureArchitecturedeclarationsectionArchitecturestatementsectionProcess:basicfunctionalunitinVHDLPrelimsHqxd:PMPageviiBasicvariabletypesandoperatorsConstantsSignalsVariablesBooleanoperatorsArithmeticoperatorsComparisonoperatorsShiftingfunctionsConcatenationDecisionsandloopsIfthenelseCaseForWhileandloopExitNextHierarchicaldesignFunctionsPackagesComponentsProceduresDebuggingmodelsAssertionsBasicdatatypesBasictypesDatatype:BITDatatype:BooleanDatatype:integerIntegersubtypes:naturalIntegersubtypes:positiveDatatype:characterDatatype:realDatatype:timeSummaryChapterDesignAutomationandTestingforFPGAsSimulationTestbenchesTestbenchgoalsSimpletestbench:instantiatingcomponentsAddingstimuliLibrariesIntroductionContentsviiiPrelimsHqxd:PMPageviiiUsinglibrariesStdlogiclibrariesStdlogictypedefinitionSynthesisDesignflowforsynthesisSynthesisissuesRTLdesignflowPhysicaldesignflowPlaceandrouteRecursivecutTiminganalysisDesignpitfallsVHDLissuesforFPGAdesignInitializationFloatingpointnumbersandoperationsSummaryPartApplicationsChapterImagesandHighSpeedProcessingIntroductionThecameralinkinterfaceHardwareinterfaceDataratesTheBayerpatternMemoryrequirementsGettingstartedSpecifyingtheinterfacesDefiningthetopleveldesignSystemblockdefinitionsandinterfacesOverallsystemdecompositionMouseandkeyboardinterfacesMemoryinterfaceThedisplayinterface:VGAThecameralinkinterfaceThePCinterfaceSummaryChapterEmbeddedProcessorsIntroductionAsimpleembeddedprocessorEmbeddedprocessorarchitectureBasicinstructionsContentsixPrelimsHqxd:PMPageixFetchexecutecycleEmbeddedprocessorregisterallocationAbasicinstructionsetStructuralorbehavioralMachinecodeinstructionsetStructuralelementsofthemicroprocessorProcessorfunctionspackageThePCTheIRTheArithmeticandLogicUnitThememoryMicrocontroller:controllerSummaryofasimplemicroprocessorSoftcoreprocessorsonanFPGASummaryPartDesigner’sToolboxChapterSerialCommunicationsIntroductionManchesterencodinganddecodingNRZcodinganddecodingNRZIcodinganddecodingRSIntroductionRSbaudrategeneratorRSreceiverUniversalSerialBusSummaryChapterDigitalFiltersIntroductionConvertingSdomaintoZdomainImplementingZdomainfunctionsinVHDLIntroductionGainblockSumanddifferenceDivisionmodelUnitdelaymodelBasiclowpassfiltermodelFIRfiltersIIRfiltersSummaryContentsxPrelimsHqxd:PMPagexChapterSecureSystemsIntroductiontoblockciphersFeistellatticestructuresTheDataEncryptionStandardIntroductionDESVHDLimplementationValidationofDESAdvancedEncryptionStandardImplementingAESinVHDLSummaryChapterMemoryIntroductionModelingmemoryinVHDLReadOnlyMemoryRandomAccessMemorySynchronousRAMFLASHmemorySummaryChapterPSMouseInterfaceIntroductionPSmousebasicsPSmousecommandsPSmousedatapacketsPSoperationmodesPSmousewithwheelBasicPSmousehandlerVHDLModifiedPSmousehandlerVHDLSummaryChapterPSKeyboardInterfaceIntroductionPSkeyboardbasicsPSkeyboardcommandsPSkeyboarddatapacketsPSkeyboardoperationmodesBasicPSkeyboardhandlerVHDLModifiedPSkeyboardhandlerVHDLSummaryChapterASimpleVGAInterfaceIntroductionBasicpixeltimingContentsxiPrelimsHqxd:PMPagexiImagehandlingVGAinterfaceVHDLHorizontalsyncVerticalsyncHorizontalandverticalblankingpulsesCalculatingthecorrectpixeldataSummaryPartOptimizingDesignsChapterSynthesisIntroductionVHDLsupportedinRTLsynthesisInitialconditionsConcurrentedgesNumerictypesWaitstatementsAssertionsLoopsSomeinterestingcaseswheresynthesismayfailWhatisbeingsynthesizedOveralldesignstructureControllerDatapathSummaryChapterBehavioralModelinginVHDLIntroductionHowtogofromRTLtobehavioralVHDLSummaryChapterDesignOptimizationIntroductionTechniquesforlogicoptimizationImprovingperformanceCriticalpathanalysisSummaryChapterVHDLAMSIntroductionIntroductiontoVHDLAMSAnalogpins:TERMINALSMixeddomainmodelingContentsxiiPrelimsHqxd:PMPagexiiAnalogvariables:quantitiesSimultaneousequationsinVHDLAMSAVHDLAMSexampleADCvoltagesourceResistorDifferentialequationsinVHDLAMSMixedsignalmodelingwithVHDLAMSAbasicswitchmodelBasicVHDLAMScomparatormodelMultipledomainmodelingSummaryChapterDesignOptimizationExample:DESIntroductionTheDESMoodsInitialdesignIntroductionOverallstructureDatatransformationsKeytransformationsInitialsynthesisOptimizingthedatapathOptimizingthekeytransformationsFinaloptimizationResultsTripleDESIntroductionMinimumarea:iterativeMinimumlatency:pipelinedComparingtheapproachesSummaryPartFundamentalTechniquesChapterCountersIntroductionBasicbinarycounterSynthesizedsimplebinarycounterShiftregisterTheJohnsoncounterBCDcounterSummaryContentsxiiiPrelimsHqxd:PMPagexiiiChapterLatches,FlipFlopsandRegistersIntroductionLatchesFlipflopsRegistersSummaryChapterSerialtoParallelParalleltoSerialConversionSerialtoParallelConversionParalleltoSerialConversionSummaryChapterALUFunctionsIntroductionLogicfunctionsbitadderStructuralnbitadditionConfigurablenbitadditionTwoscomplementSummaryChapterDecodersandMultiplexersDecodersMultiplexersSummaryChapterFiniteStateMachinesinVHDLIntroductionStatetransitiondiagramsImplementingFSMinVHDLSummaryChapterFixedPointArithmeticinVHDLIntroductionBasicfixedpointtypesFixedpointfunctionsFixedpointtostdlogicvectorfunctionsFixedpointtorealconversionTestingthefixedpointfunctionSummaryChapterBinaryMultiplicationIntroductionBasicbinarymultiplicationVHDLunsignedmultiplierContentsxivPrelimsHqxd:PMPagexivContentsSynthesisofthemultiplicationfunction‘Simple’multiplicationSummaryChapterBibliographyIntroductionUsefultextsforVHDLDigitalSystemsDesignDesignersGuidetoVHDLVHDL:AnalysisandModelingofDigitalSystemsVHDLforLogicSynthesisUsefulTextsforFPGAsDesignWarriorsGuidetoFPGAsGeneralDigitalDesignBooksDigitalDesignIndexxvPrelimsHqxd:PMPagexvThispageintentionallyleftblankAcknowledgementsIwouldliketothankProfessorAndrewBrown,theheadoftheElectronicSystemsDesignGroup,SchoolofElectronicsandComputerScience,attheUniversityofSouthampton,UKGivingmetheopportunitytofirststudyandthenworkinhisgrouphasleddirectlytomebeingabletowritethisbookForthatIamdeeplygratefulInaddition,thecontinuingsupportandencouragementofcolleaguesandstudentsintheESDresearchgrouphasbeenaconstantsourceofsupportandideasIalsowishtosingleoutTimPitts(ElsevierPublishing)whowasinstrumentalinmestartingthisproject,andalsoforhisencouragementtoseeitthroughtoaconclusionIalsowouldliketothankthosewhohavecontributedtotheproductionofthebookincludingLisaJones,HelenEaton,LewinEdwards,CharonTecandteamandallatElsevierFinallyaheartfeltthankyoutoallofmyfamily,especiallymywifeCaroline,andchildren,NathanandHeatherAsalways,withouttheirsupport,noneofthiswouldbepossiblePeterRWilsonPrelimsHqxd:PMPagexviiThispageintentionallyleftblankPrefaceThisbookisdesignedtobeadesktopreferenceforengineers,studentsandresearcherswhouseFieldProgrammableGateArrays(FPGA)astheirhardwareplatformofchoiceThisbookhasbeenproducedinthespiritofthe‘numericalrecipe’seriesofbooksforvariousprograminglanguages–wheretheintentionisnottoteachthelanguageperse,butratherthephilosophyandtechniquesrequired,makingyourapplicationworkTherationaleofthisbookissimilarinthattheintentionistoprovidethemethodsandunderstandingtomakethereaderabletodeveloppractical,operationalVHDLthatwillruncorrectlyonFPGAsItisimportanttostressthathisbookisnotdesignedasalanguagereferencemanualforVHDLThereareplentyofthoseavailableandIhavereferencedthemthroughoutthetextThisbookisintendedasareferencefordesignwithVHDLandcanbeseenascomplementarytoaconventionalVHDLtextbookPrelimsHqxd:PMPagexixThispageintentionallyleftblankListofFiguresFigureProgrammableLogicDeviceFigureComplexProgrammableLogicDeviceFigureFPGACLBFigureXilinxCLBFigureFPGAStructureofCLBsFigureVHDLModelswithDifferentArchitecturesFigureHDLDesignFlowFigureRTLSynthesisandDesignFlowFigureVideoMonitorSystemOverviewFigureBasicBayerPattern,andExtendedOveraLargerImageAreaFigureTopLevelDesign–SketchFigureSimpleMicrocontrollerFigureEmbeddedMicrocontrollerArchitectureFigureStructuralModeloftheMicroprocessorFigureBasicProcessorControllerStateMachineFigureManchesterEncodingSchemeFigureManchesterEncodingUsingXORFunctionFigureBaudClockGeneratorFigureSerialDataReceiverFigureBasicSerialReceiverFigureUSBTransceiverChipCPFigureRCFilterintheAnalogDomainFigureSimpleZDomainLowPassFilterFigureBasicLowPassFilterSimulationWaveformsFigureFIRFilterSchematicFigureReversibleandIrreversibleTransformationsFigureFeistelLatticeStructureFigureDESCoarseStructureFigureDESFineStructureFigureSBoxArchitectureFigureDESRoundKeyGenerationFigureAESRoundStructurePrelimsHqxd:PMPagexxiListofFiguresxxiiFigureAESStructureFigureDRAMSimulationResultsFigureSynthesizableDigitalCircuitFigureBasicStateMachineFigureDataPathFigureCrossProductMultiplierSpecificationFigureDataPathModelFigureBasicInputKarnaughMapFigureSpecificKarnaughMapExampleFigureFunctionsIdentifiedonKarnaughMapFigureNaïveDataflowDiagramforAdditionFigureReducedCycleImplementationFigureCriticalPathAnalysisFigureScopeofVHDLAMSFigureBasicVoltageSourceFigureVHDLAMSResistorSymbolFigureNewton–RaphsonMethodFigureComparatorFigureOverallStructureoftheDESAlgorithmFigureControlStateMachineforInitialSynthesisFigureControlStateMachineforOptimizedSblocksFigureControlStateMachineforOptimizedKeyRotateFigureAreavsThroughputforAllDESDesignsFigureControlStateMachineforPipelinedTripleDESFigureSimpleBinaryCounterFigureShiftRegisterFunctionality:(a)beforeand(b)aftertheclockedgeFigureDLatchSymbolFigureSynthesisedLatchFigureDTypeFlipFlopFigureDTypeFlipFlopwithAsynchronousSetandResetFigureSimpleBitAdderFigureBitAdderwithCarryinandCarryoutFigure–DecoderFigureInputMultiplexerwithasingleselectlineFigureHardwareStateMachineStructureFigureStateTransitionDiagramFigureBasicBinaryNotationFigureNegativeNumberBinaryNotationFigureFixedPointNotationFigureBasicSignedMultiplicationPrelimsHqxd:PMPagexxiiPartOverviewThebookisdividedintofivemainpartsIntheintroductorypartofthebook,primersaregivenintoFieldProgrammableGateArrays(FPGA),VHDLandthestandarddesignflowInthesecondpartofthebook,aseriesofcomplexapplicationsthatencompassmanyofthekeydesignproblemsfacingdesignerstodayareworkedthroughfromstarttofinishinapracticalwayThiswillshowhowthedesignercaninterpretaspecificationanddevelopatopdowndesignmethodologyandeventuallybuildindetaileddesignblocksperhapsdevelopedpreviouslyorbyathirdpartyInthethirdpartofthebook,importanttechniquesarediscussed,workedthroughandexplainedfromanexampleperspective,soyoucanseeexactlyhowtoimplementaparticularfunctionThispartisreallyatoolboxofadvancedspecificfunctionsthatarecommonlyrequiredinmoderndigitaldesignThefourthpartonadvancedtechniquesdiscussestheimportantaspectofdesignoptimization,thatishowcanImakemydesignfasterOrmorecompactThefifthpartinvestigatesthedetailsoffundamentalissuesthatareimplementedinVHDLThisfinalpartisaimedatdesignerswithalimitedVHDLbackground,perhapsthoselookingforsimplerexamplestogetstarted,ortosolveaparticulardetailedissueChHqxd:AMPageThispageintentionallyleftblankIntroductionWhyFPGAsTherearenumerousoptionsfordesignersinselectingahardwareplatformforcustomelectronicsdesign,rangingfromembeddedprocessors,ApplicationSpecificIntegratedCircuits(ASICs),ProgrammableMicroprocessors(PICs),FPGAstoProgrammableLogicDevices(PLDs)ThedecisiontochooseaspecifictechnologysuchasanFPGAshoulddependprimarilyonthedesignrequirementsratherthanapersonalpreferenceforonetechniqueoveranotherForexample,ifthedesignrequiresaprogrammabledevicewithmanydesignchanges,andalgorithmsusingcomplexoperationssuchasmultiplicationsandlooping,thenitmaymakemoresensetouseadedicatedsignalprocessordevicesuchasaDSPthatcanbeprogrammedandreprogrammedeasilyusingCorsomeotherhighlevellanguageIfthespeedrequirementsarenotparticularlystringent,andacompactcheapplatformisrequired,thenageneralpurposemicroprocessorsuchasaPICwouldbeanidealchoiceFinally,ifthehardwarerequirementsrequireahigherlevelofperformance,sayuptoseveralMHzoperation,thenanFPGAoffersasuitablelevelofperformance,whilestillretainingtheflexibilityandreusabilityofprogrammablelogicOtherissuestoconsiderarethelevelofoptimizationinthehardwaredesignrequiredForexample,asimplesoftwareprogramcanbewritteninC,andthenaPICdeviceprogrammed,buttheperformancemaybelimitedbytheinabilityoftheprocessortoofferparalleloperationofkeyfunctionsThiscanbeimplementedmuchmoredirectlyinanFPGAusingparallelismandpipeliningChHqxd:AMPagetoachievemuchgreaterthroughputthanwouldbepossibleusingaPICAgeneralruleofthumbwhenchoosingahardwareplatformistoidentifyboththedesignrequirementsandthehardwareoptions,andthenselectasuitableplatformbasedonthoseconsiderationsForexample,ifthedesignrequiresabasicclockspeedofuptoMHzthenanFPGAwouldbeasuitableplatformIftheclockspeedcouldbe–MHz,thentheFPGAmaybeanexpensive(overkill)optionIfthedesignrequiresaflexibleprocessoroption,althoughtheFPGAsavailabletodaysupportembeddedprocessors,itprobablymakessensetouseaDSPorPICIfthedesignrequiresdedicatedhardwarefunctionality,thenanFPGAis

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