关闭

关闭

关闭

封号提示

内容

首页 一个ARM7的手册,全部的语言格式和用法.pdf

一个ARM7的手册,全部的语言格式和用法.pdf

一个ARM7的手册,全部的语言格式和用法.pdf

上传者: xl46512 2012-05-08 评分 0 0 0 0 0 0 暂无简介 简介 举报

简介:本文档为《一个ARM7的手册,全部的语言格式和用法pdf》,可适用于IT/计算机领域,主题内容包含AdvancedRISCMachinesARMDocumentNumber:ARMDDIEIssued:AugustCopyrightAdvance符等。

AdvancedRISCMachinesARMDocumentNumber:ARMDDIEIssued:AugustCopyrightAdvancedRISCMachinesLtd(ARM)AllrightsreservedARMTDMIDataSheetOpenAccessProprietaryNoticeARM,theARMPoweredlogo,EmbeddedICE,BlackICEandICEbreakeraretrademarksofAdvancedRISCMachinesLtdNeitherthewholenoranypartoftheinformationcontainedin,ortheproductdescribedin,thisdatasheetmaybeadaptedorreproducedinanymaterialformexceptwiththepriorwrittenpermissionofthecopyrightholderTheproductdescribedinthisdatasheetissubjecttocontinuousdevelopmentsandimprovementsAllparticularsoftheproductanditsusecontainedinthisdatasheetaregivenbyARMingoodfaithHowever,allwarrantiesimpliedorexpressed,includingbutnotlimitedtoimpliedwarrantiesormerchantability,orfitnessforpurpose,areexcludedThisdatasheetisintendedonlytoassistthereaderintheuseoftheproductARMLtdshallnotbeliableforanylossordamagearisingfromtheuseofanyinformationinthisdatasheet,oranyerrororomissioninsuchinformation,oranyincorrectuseoftheproductChangeLogIssueDateByChangeA(Draft)SeptEHBJHCreated(Draft)OctEHFirstpassreviewcommentsaddedBDecEHAWFirstformalreleaseCDecAWFurtherreviewcommentsMarAWReissuedwithopenaccessstatusNochangetothecontentDdraftMarAWChangesinlinewiththeARMTDMdatasheetFurthertechnicalchangesDMarAWReviewcommentsaddedEAugAPSignalsaddedplusminorchangesiiARMTDMIDataSheetARMDDIEOpenAccessKey:OpenAccessNoconfidentialityToenabledocumenttracking,thedocumentnumberhastwocodes:MajorreleasePrereleaseAFirstreleaseBSecondreleaseetcetcDraftStatusFullandcompletedraftFirstDraftdraftSecondDraftetcetcEEmbargoed(dategiven)ARMTDMIDataSheetARMDDIEContentsiOpenAccessIntroductionIntroductionARMTDMIArchitectureARMTDMIBlockDiagramARMTDMICoreDiagramARMTDMIFunctionalDiagramSignalDescriptionSignalDescriptionProgrammer’sModelProcessorOperatingStatesSwitchingStateMemoryFormatsInstructionLengthDataTypesOperatingModesRegistersTheProgramStatusRegistersExceptionsInterruptLatenciesResetContentsTOCContentsARMTDMIDataSheetARMDDIEContentsiiOpenAccessARMInstructionSetInstructionSetSummaryTheConditionFieldBranchandExchange(BX)BranchandBranchwithLink(B,BL)DataProcessingPSRTransfer(MRS,MSR)MultiplyandMultiplyAccumulate(MUL,MLA)MultiplyLongandMultiplyAccumulateLong(MULL,MLAL)SingleDataTransfer(LDR,STR)HalfwordandSignedDataTransferBlockDataTransfer(LDM,STM)SingleDataSwap(SWP)SoftwareInterrupt(SWI)CoprocessorDataOperations(CDP)CoprocessorDataTransfers(LDC,STC)CoprocessorRegisterTransfers(MRC,MCR)UndefinedInstructionInstructionSetExamplesTHUMBInstructionSetFormat:moveshiftedregisterFormat:addsubtractFormat:movecompareaddsubtractimmediateFormat:ALUoperationsFormat:HiregisteroperationsbranchexchangeFormat:PCrelativeloadFormat:loadstorewithregisteroffsetFormat:loadstoresignextendedbytehalfwordFormat:loadstorewithimmediateoffsetFormat:loadstorehalfwordFormat:SPrelativeloadstoreFormat:loadaddressFormat:addoffsettoStackPointerFormat:pushpopregistersFormat:multipleloadstoreFormat:conditionalbranchFormat:softwareinterruptContentsARMTDMIDataSheetARMDDIEContentsiiiOpenAccessFormat:unconditionalbranchFormat:longbranchwithlinkInstructionSetExamplesMemoryInterfaceOverviewCycleTypesAddressTimingDataTransferSizeInstructionFetchMemoryManagementLockedOperationsStretchingAccessTimesTheARMDataBusTheExternalDataBusCoprocessorInterfaceOverviewInterfaceSignalsRegisterTransferCyclePrivilegedInstructionsIdempotencyUndefinedInstructionsDebugInterfaceOverviewDebugSystemsDebugInterfaceSignalsScanChainsandJTAGInterfaceResetPullupResistorsInstructionRegisterPublicInstructionsTestDataRegistersARMTDMICoreClocksDeterminingtheCoreandSystemStateThePC’sBehaviourDuringDebugPrioritiesExceptionsScanInterfaceTimingDebugTimingContentsARMTDMIDataSheetARMDDIEContentsivOpenAccessICEBreakerModuleOverviewTheWatchpointRegistersProgrammingBreakpointsProgrammingWatchpointsTheDebugControlRegisterDebugStatusRegisterCouplingBreakpointsandWatchpointsDisablingICEBreakerICEBreakerTimingProgrammingRestrictionDebugCommunicationsChannelInstructionCycleOperationsIntroductionBranchandBranchwithLinkTHUMBBranchwithLinkBranchandExchange(BX)DataOperationsMultiplyandMultiplyAccumulateLoadRegisterStoreRegisterLoadMultipleRegistersStoreMultipleRegistersDataSwapSoftwareInterruptandExceptionEntryCoprocessorDataOperationCoprocessorDataTransfer(frommemorytocoprocessor)CoprocessorDataTransfer(fromcoprocessortomemory)CoprocessorRegisterTransfer(Loadfromcoprocessor)CoprocessorRegisterTransfer(Storetocoprocessor)UndefinedInstructionsandCoprocessorAbsentUnexecutedInstructionsInstructionSpeedSummaryDCParametersAbsoluteMaximumRatingsDCOperatingConditionsContentsARMTDMIDataSheetARMDDIEContentsvOpenAccessACParametersIntroductionNotesonACParametersContentsARMTDMIDataSheetARMDDIEContentsviOpenAccessARMTDMIDataSheetARMDDIEOpenAccessIntroductionThischapterintroducestheARMTDMIarchitecture,andshowsblock,core,andfunctionaldiagramsfortheARMTDMIIntroductionARMTDMIArchitectureARMTDMIBlockDiagramARMTDMICoreDiagramARMTDMIFunctionalDiagramIntroductionARMTDMIDataSheetARMDDIEOpenAccessIntroductionTheARMTDMIisamemberoftheAdvancedRISCMachines(ARM)familyofgeneralpurposebitmicroprocessors,whichofferhighperformanceforverylowpowerconsumptionandpriceTheARMarchitectureisbasedonReducedInstructionSetComputer(RISC)principles,andtheinstructionsetandrelateddecodemechanismaremuchsimplerthanthoseofmicroprogrammedComplexInstructionSetComputersThissimplicityresultsinahighinstructionthroughputandimpressiverealtimeinterruptresponsefromasmallandcosteffectivechipPipeliningisemployedsothatallpartsoftheprocessingandmemorysystemscanoperatecontinuouslyTypically,whileoneinstructionisbeingexecuted,itssuccessorisbeingdecoded,andathirdinstructionisbeingfetchedfrommemoryTheARMmemoryinterfacehasbeendesignedtoallowtheperformancepotentialtoberealisedwithoutincurringhighcostsinthememorysystemSpeedcriticalcontrolsignalsarepipelinedtoallowsystemcontrolfunctionstobeimplementedinstandardlowpowerlogic,andthesecontrolsignalsfacilitatetheexploitationofthefastlocalaccessmodesofferedbyindustrystandarddynamicRAMsARMTDMIArchitectureTheARMTDMIprocessoremploysauniquearchitecturalstrategyknownasTHUMB,whichmakesitideallysuitedtohighvolumeapplicationswithmemoryrestrictions,orapplicationswherecodedensityisanissueTheTHUMBConceptThekeyideabehindTHUMBisthatofasuperreducedinstructionsetEssentially,theARMTDMIprocessorhastwoinstructionsets:•thestandardbitARMset•abitTHUMBsetTheTHUMBset’sbitinstructionlengthallowsittoapproachtwicethedensityofstandardARMcodewhileretainingmostoftheARM’sperformanceadvantageoveratraditionalbitprocessorusingbitregistersThisispossiblebecauseTHUMBcodeoperatesonthesamebitregistersetasARMcodeTHUMBcodeisabletoprovideuptoofthecodesizeofARM,andoftheperformanceofanequivalentARMprocessorconnectedtoabitmemorysystemIntroductionARMTDMIDataSheetARMDDIEOpenAccessTHUMB’sAdvantagesTHUMBinstructionsoperatewiththestandardARMregisterconfiguration,allowingexcellentinteroperabilitybetweenARMandTHUMBstatesEachbitTHUMBinstructionhasacorrespondingbitARMinstructionwiththesameeffectontheprocessormodelThemajoradvantageofabit(ARM)architectureoverabitarchitectureisitsabilitytomanipulatebitintegerswithsingleinstructions,andtoaddressalargeaddressspaceefficientlyWhenprocessingbitdata,abitarchitecturewilltakeatleasttwoinstructionstoperformthesametaskasasingleARMinstructionHowever,notallthecodeinaprogramwillprocessbitdata(forexample,codethatperformscharacterstringhandling),andsomeinstructions,likeBranches,donotprocessanydataatallIfabitarchitectureonlyhasbitinstructions,andabitarchitectureonlyhasbitinstructions,thenoverallthebitarchitecturewillhavebettercodedensity,andbetterthanonehalftheperformanceofthebitarchitectureClearlybitperformancecomesatthecostofcodedensityTHUMBbreaksthisconstraintbyimplementingabitinstructionlengthonabitarchitecture,makingtheprocessingofbitdataefficientwithacompactinstructioncodingThisprovidesfarbetterperformancethanabitarchitecture,withbettercodedensitythanabitarchitectureTHUMBalsohasamajoradvantageoverotherbitarchitectureswithbitinstructionsThisistheabilitytoswitchbacktofullARMcodeandexecuteatfullspeedThuscriticalloopsforapplicationssuchas•fastinterrupts•DSPalgorithmscanbecodedusingthefullARMinstructionset,andlinkedwithTHUMBcodeTheoverheadofswitchingfromTHUMBcodetoARMcodeisfoldedintosubroutineentrytimeVariousportionsofasystemcanbeoptimisedforspeedorforcodedensitybyswitchingbetweenTHUMBandARMexecutionasappropriateIntroductionARMTDMIDataSheetARMDDIEOpenAccessARMTDMIBlockDiagramFigure:ARMTDMIblockdiagram••ScanChainA:CoreScanChainD:nOPCnRWAllOtherSignalsTCKTMSTDInTRSTTDOEXTERNEXTERNnTRANSnMREQScanChainICEBreakerTAPcontrollerMAS:BusSplitterDIN:DOUT:RANGEOUTRANGEOUTTAPSM:IR:SCREG:IntroductionARMTDMIDataSheetARMDDIEOpenAccessARMTDMICoreDiagramFigure:ARMTDMIcorenRESETnMREQSEQABORTnIRQnFIQnRWLOCKnCPICPACPBnWAITMCLKnOPCnTRANSInstructionDecoderControlLogicInstructionPipelineReadDataRegisterDBED:bitALUBarrelShifterAddressIncrementerAddressRegisterRegisterBank(xbitregisters)(statusregisters)A:ALEMultiplierABEWriteDataRegisternM:xnENOUTnENINTBEScanControlBREAKPTIDBGRQInEXECDBGACKECLKISYNCBbusALUbusAbusPCbusIncrementerbusAPEBL:MAS:TBITHIGHZThumbInstructionDecoderIntroductionARMTDMIDataSheetARMDDIEOpenAccessARMTDMIFunctionalDiagramFigure:ARMTDMIfunctionaldiagramLOCKA:ABORTMemoryManagementnOPCnCPICPACPBCoprocessorInterfacenTRANSMemoryInterfaceInterfaceD:TCKTMSTDInTRSTBoundaryScanTDOProcessorModenRWnMREQSEQBL:MAS:APETBITProcessorStatenM:ARMTDMIDIN:DOUT:TAPSM:IR:BoundaryScanTCKTCKControlSignalsnTDOENSCREG:ABEALEnIRQnFIQBusInterruptsISYNCnRESETMCLKnWAITClocksVDDVSSPowerDBGRQBREAKPTDBGACKnEXECDebugControlsEXTERNDBETBEEXTERNnENOUTnENINECLKDBGENAPEHIGHZBIGENDBUSENRANGEOUTRANGEOUTDBGRQICOMMRXCOMMTXnENOUTIECAPCLKBUSDISARMTDMIDataSheetARMDDIEOpenAccessSignalDescriptionThischapterlistsanddescribesthesignalsfortheARMTDMISignalDescriptionSignalDescriptionARMTDMIDataSheetARMDDIEOpenAccessSignalDescriptionThefollowingtablelistsanddescribesallthesignalsfortheARMTDMITransistorsizesForaµmARMTDMI:INVdriverhastransistorsizesofp=µmµmN=µmµmINVdriverhastransistorsizesofp=µmµmN=µmµmKeytosignaltypesICInputCMOSthresholdsPPowerOOutputwithINVdriverOOutputwithINVdriverNameTypeDescriptionA:AddressesThisistheprocessoraddressbusIfALE(addresslatchenable)isHIGHandAPE(AddressPipelineEnable)isLOW,theaddressesbecomevalidduringphaseofthecyclebeforetheonetowhichtheyreferandremainsoduringphaseofthereferencedcycleTheirstableperiodmaybecontrolledbyALEorAPEasdescribedbelowABEAddressbusenableICThisisaninputsignalwhich,whenLOW,putstheaddressbusdriversintoahighimpedancestateThissignalhasasimilareffectonthefollowingcontrolsignals:MAS:,nRW,LOCK,nOPCandnTRANSABEmustbetiedHIGHwhenthereisnosystemrequirementtoturnofftheaddressdriversABORTMemoryAbortICThisisaninputwhichallowsthememorysystemtotelltheprocessorthatarequestedaccessisnotallowedALEAddresslatchenableICThisinputisusedtocontroltransparentlatchesontheaddressoutputsNormallytheaddresseschangeduringphasetothevaluerequiredduringthenextcycle,butfordirectinterfacingtoROMstheyarerequiredtobestabletotheendofphaseTakingALELOWuntiltheendofphasewillensurethatthishappensThissignalhasasimilareffectonthefollowingcontrolsignals:MAS:,nRW,LOCK,nOPCandnTRANSIfthesystemdoesnotrequireaddresslinestobeheldinthisway,ALEmustbetiedHIGHTheaddresslatchisstatic,soALEmaybeheldLOWforlongperiodstofreezeaddressesTable:SignalDescriptionSignalDescriptionARMTDMIDataSheetARMDDIEOpenAccessAPEAddresspipelineenableICWhenHIGH,thissignalenablestheaddresstimingpipelineInthisstate,theaddressbusplusMAS:,nRW,nTRANS,LOCKandnOPCchangeinthephasepriortothememorycycletowhichtheyreferWhenAPEisLOW,thesesignalschangeinthephaseoftheactualcyclePleaserefertoòChapter,MemoryInterfacefordetailsofthistimingBIGENDBigEndianconfigurationICWhenthissignalisHIGHtheprocessortreatsbytesinmemoryasbeinginBigEndianformatWhenitisLOW,memoryistreatedasLittleEndianBL:ByteLatchControlICThesesignalscontrolwhendataandinstructionsarelatchedfromtheexternaldatabusWhenBLisHIGH,thedataonD:islatchedonthefallingedgeofMCLKWhenBLisHIGH,thedataonD:islatchedandsoonPleaserefertoòChapter,MemoryInterfacefordetailsontheuseofthesesignalsBREAKPTBreakpointICThissignalallowsexternalhardwaretohalttheexecutionoftheprocessorfordebugpurposesWhenHIGHcausesthecurrentmemoryaccesstobebreakpointedIfthememoryaccessisaninstructionfetch,ARMTDMIwillenterdebugstateiftheinstructionreachestheexecutestageoftheARMTDMIpipelineIfthememoryaccessisfordata,ARMTDMIwillenterdebugstateafterthecurrentinstructioncompletesexecutionThisallowsextensionoftheinternalbreakpointsprovidedbytheICEBreakermoduleSeeòChapter,ICEBreakerModuleBUSDISBusDisableOThissignalisHIGHwhenINTESTisselectedonscanchainorandmaybeusedtodisableexternallogicdrivingontothebidirectionaldatabusduringscantestingThissignalchangesonthefallingedgeofTCKBUSENDatabusconfigurationICThisisastaticconfigurationsignalwhichdetermineswhetherthebidirectionaldatabus,D:,ortheunidirectionaldatabusses,DIN:andDOUT:,aretobeusedfortransferofdatabetweentheprocessorandmemoryReferalsotoòChapter,MemoryInterfaceWhenBUSENisLOW,thebidirectionaldatabus,D:isusedInthiscase,DOUT:isdriventovaluex,andanydatapresentedonDIN:isignoredWhenBUSENisHIGH,thebidirectionaldatabus,D:isignoredandmustbeleftunconnectedInputdataandinstructionsarepresentedontheinputdatabus,DIN:,outputdataappearsonDOUT:COMMRXCommunicationsChannelReceiveOWhenHIGH,thissignaldenotesthatthecommschannelreceivebufferisemptyThissignalchangesontherisingedgeofMCLKSeeòDebugCommunicationsChannelonpageformoreinformationonthedebugcommschannelNameTypeDescriptionTable:SignalDescription(Continued)SignalDescriptionARMTDMIDataSheetARMDDIEOpenAccessCOMMTXCommunicationsChannelTransmitOWhenHIGH,thissignaldenotesthatthecommschanneltransmitbufferisemptyThissignalchangesontherisingedgeofMCLKSeeòDebugCommunicationsChannelonpageformoreinformationonthedebugcommschannelCPACoprocessorabsentICAcoprocessorwhichiscapableofperformingtheoperationthatARMTDMIisrequesting(byassertingnCPI)shouldtakeCPALOWimmediatelyIfCPAisHIGHattheendofphaseofthecycleinwhichnCPIwentLOW,ARMTDMIwillabortthecoprocessorhandshakeandtaketheundefinedinstructiontrapIfCPAisLOWandremainsLOW,ARMTDMIwillbusywaituntilCPBisLOWandthencompletethecoprocessorinstructionCPBCoprocessorbusyICAcoprocessorwhichiscapableofperformingtheoperationwhichARMTDMIisrequesting(byassertingnCPI),butcannotcommittostartingitimmediately,shouldindicatethisbydrivingCPBHIGHWhenthecoprocessorisreadytostartitshouldtakeCPBLOWARMTDMIsamplesCPBattheendofphaseofeachcycleinwhichnCPIisLOWD:DataBusICThesearebidirectionalsignalpathswhichareusedfordatatransfersbetweentheprocessorandexternalmemoryDuringreadcycles(whennRWisLOW),theinputdatamustbevalidbeforetheendofphaseofthetransfercycleDuringwritecycles(whe

用户评论(0)

0/200

精彩专题

上传我的资料

每篇奖励 +2积分

资料评价:

/49
仅支持在线阅读

意见
反馈

立即扫码关注

爱问共享资料微信公众号

返回
顶部