FPGA to PCB
Training Module
Document Version 1.2, February 2008
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Module 3
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FPGA to PCB Training Module
1. From FPGA project to PCB project...................................................................... 32
1.1 Understanding the document stack............................................................. 32
1.2 Using the FPGA to PCB project wizard....................................................... 34
1.3 Choosing the FPGA configuration............................................................... 34
1.4 Initial FPGA pin assignments...................................................................... 35
1.5 Choosing the target PCB project................................................................. 37
1.6 Configuring the FPGA component schematic sheet .................................... 37
1.7 Configuring the sheet symbol schematic sheet ........................................... 38
1.8 Exercise 1 – Running the FPGA to PCB project wizard............................... 39
1.9 Modifying the auto generated sheet .......................................................... 311
1.10 A word about special function FPGA pins ................................................. 311
1.11 Recreating the autogenerated sheet ......................................................... 312
2. Maintaining project synchronization ................................................................. 313
2.1 The FPGA workspace map....................................................................... 313
2.2 The synchronize dialog............................................................................. 314
2.3 Synchronizing matched signals................................................................. 316
2.4 Synchronizing unmatched signals............................................................. 317
3. Configuring FPGA I/O......................................................................................... 320
3.1 Configuring I/O standards......................................................................... 320
3.2 Exercise 2 – Using the FPGA signal manager........................................... 321
4. Manually linking FPGA and PCB projects ......................................................... 323
4.1 Supported devices.................................................................................... 324
4.2 Creating the link ....................................................................................... 324
4.3 Linking an auto generated sheet to an existing PCB project ...................... 327
4.4 Exercise 3 – Manually linking a PCB and FPGA project ............................ 327
5. Pin swapping ...................................................................................................... 328
5.1 Pin swapping in the PCB document .......................................................... 328
5.2 Pin swapping in the FPGA project............................................................. 335
5.3 Pin swapping in both PCB and FPGA projects .......................................... 336
5.4 Exercise 4 – Pin swapping........................................................................ 336
6. Commissioning the design ................................................................................ 338
6.1 Exercise 5 – Migration stage 1.................................................................. 338
6.2 Exercise 6 – Migration stage 2.................................................................. 339
6.3 Exercise 7 – Calibration............................................................................ 339
6.4 Exercise 8 – Bootstrapping the FPGA....................................................... 340
6.5 Exercise 9 – Reverting to test mode ......................................................... 341
7. Review................................................................................................................. 342
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1. From FPGA project to PCB project
At some point in the life of all designs there comes a point where they must move from the laboratory
prototype to production. If a design has been successfully running on the Desktop NanoBoard, the
process of migrating from an FPGA based project to a PCB based project containing the FPGA
project is simplified through the use of the FPGA to PCB Project Wizard. This method
automatically links the two projects and maximizes synchronization functionality between them.
Project synchronization is important as it ensures that design changes made to either the PCB
document or FPGA project are propagated in a controlled fashion.
Over the remainder of the course we will look at moving a design from the test environment, to the
target PCB. To do this we will use a design that has already been completed for us, a Digital Spirit
Level. The FPGA portion of this design includes a softcore TSK51 processor which takes as its input
the output of an accelerometer and outputs a small bubble on an LCD mimicking a traditional spirit
level.
1.1 Understanding the document stack
Figure 1. Visualization of how the various project documents are stacked
Synchronization between PCB and FPGA projects is carried out and maintained by establishing a
link between the toplevel ports in the FPGA project – specified in the relevant constraint file – and
the corresponding pins on the FPGA component schematic. Linking is achieved using the signal
name. The name given to the port in the FPGA project must be the same as the net label assigned
to the corresponding pin on the schematic component in the PCB project. Figure 1 provides a
visualization of how the various documents in an FPGA/PCB project stack are linked together.
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FPGA_Top.SchDoc FPGA project
The top level FPGA schematic document
must contain ports at the point where
signals are connected to physical pins on
the FPGA device. The name of the ports is
important as they will be used in the
constraints file.
FPGA.Constraint FPGA project
The Constraint file defines the physical pin
number that ports defined in the top level
FPGA schematic will be connected to. This
is referred to as a port name to FPGA pin
number mapping. Port names declared in
the constraint file mustmatch those
included in the top level FPGA schematic
document.
FPGA_Auto.SchDoc PCB project
The autogenerated schematic sheet is
created from information contained in the
FPGA constraint file. Essentially the
autosheet is a schematic representation of
the port to pin mappings made by the
constraint file. Port to pin connectivity on
the autosheet is accomplished through the
use of net labels – i.e. a net label is
attached to wires connected to the ports on
the sheet and a corresponding net label is
also attached to the device pin.
FPGA_Manual.SchDoc PCB project
An optional ‘manual’ sheet is generated as
part of the FPGA to PCB project wizard.
This manual sheet contains a sheet symbol
of the autosheet – the ports on the
autosheet are connected to corresponding
ports on the sheet symbol. Connecting to
this sheet symbol rather than directly to the
FPGA symbol introduces an important
abstraction layer. This layer facilitates easy
(automated) updates to the project if the
device or pin allocations should change as
the project develops.
TargetPCB.PCBDoc PCB project
The FPGA depicted in the autosheet and
abstracted on the ‘manual’ sheet will
eventuate into a physical device on the final
PCB. The physical pins of this device will
be connected to ports as described in the
autosheet.
Figure 2. The role of the various documents in the project stack
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1.2 Using the FPGA to PCB project wizard
With a schematic document in the FPGA project open as the active view in the main design window,
simply choose the Tools » FPGA To PCB Project Wizard entry from the menu. The wizard will
appear, as shown in Figure :
Figure 3. The FPGA To PCB project wizard.
1.3 Choosing the FPGA configuration
The second page of the wizard allows you to choose the configuration that will be used for targeting
the FPGA design to the PCB. The configuration uses a constraint file that defines the FPGA device
to be used and its associated pin mappings.
The configuration can either be an existing one that you have already defined as part of the FPGA
project, or a new one, generated by the wizard. In the case of the latter, the wizard will generate a
configuration and add to it a new constraint file. These will have default names (PCB
Configuration and PCB Constraints.Constraint respectively) and the constraint file will be
stored in the same location as the FPGA project file (*.PrjFPG), unless otherwise specified.
Figure 4. Wizardbased configuration generation.
The constraint file that is added to the configuration will contain a target device definition for the
FPGA project, according to the device you select in the Selected Device field. You can browse for a
device by clicking the … button, to the right of the field. This will open the Choose Physical Device
dialog, from where you can peruse from a number of devices available across a spectrum of FPGA
vendordevice families.
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Figure 5. Browsing for the required FPGA device.
1.4 Initial FPGA pin assignments
The second page of the FPGA to PCB Project wizard gives you the choice of what to do with
unconstrained ports – i.e. ports that have not been tied to a specific pin on the target device. The
decision as to how these pins are assigned is somewhat arbitrary and so there are a number of ways
of doing this:
1.4.1 Importing pin file from vendor place and route tools
Clearly for this option to be available the design must have previously been built for the current
device and a constraint file and configuration must already exist. For totally new designs this is the
preferred design path. It ensures that the vendor tools are given the most opportunity to optimize the
design without being unduly constrained and it ensures that the selected device is capable of
supporting the design. In this case, the pin assignments should be made prior to running the FPGA
to PCB project wizard. With a constraint file open in the main window, select Design » Import Pin
File from the menu to import the vendor pin file. The following dialog box will appear:
Figure 6. Selecting constraints to be imported from the vendor tools
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1.4.2 Assigning pins during the FPGA to PCB wizard
Probably the quickest and simplest way to allocate pins is whilst executing the FPGA to PCB project
wizard. Select the Assign Unconstrained Ports on the second page of the wizard. As the wizard
executes it will automatically allocate pin numbers to unallocated ports updating the constraint file
and auto generated sheet as it goes.
Figure 7. Assigning unconstrained ports as part of the FPGA to PCB project wizard
1.4.3 Assigning unconstrained signals from the FPGA signal manager
It is also possible to allocate unconstrained signals by selecting the Assign Unconstrained Signals
button in the FPGA Signal Manager dialog (Figure 8).
Figure 8. Using the FPGA signal manager to assign unconstrained signals
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Performing pin assignments via this method is probably less advisable as it does not give the user
the choice which constraint file (project or target) records the pin allocations. Furthermore, an
additional step is required after this one to resynchronize the net labels in the autogenerated sheet.
1.4.4 Assigning signals manually in the auto generated sheet
This is the most laborious method and generally not advisable. Using this method requires the
designer to manually enter the net names for all ports onto the autogenerated sheet. A second
synchronization step is also required to propagate the pin assignments into the constraints file.
1.5 Choosing the target PCB project
After choosing the FPGA configuration, the actual target PCB project must now be defined. Simply
accept the Wizard's generation of a new project (PCB Project1.PrjPCB), or browse to and select
an existing project. In the case of a new PCB project, the file will be stored in the same location as
the FPGA project.
1.6 Configuring the FPGA component schematic sheet
Whether the PCB project already exists or is being newly created, the relationship between the
FPGA project and its corresponding component in the PCB project has to be managed in some way.
This is achieved using a dedicated, autogenerated schematic sheet, referred to as the 'Main Sheet'
in the Wizard.
Figure 2. The autogenerated FPGA component schematic sheet.
This schematic sheet will be created with the component symbol placed for the FPGA device
targeted in the constraint file. The Wizard allows you to determine where and by what name, the
schematic is created. By default, the schematic will be named using the chosen designator for the
FPGA component (e.g. FPGA_U1_Auto.SchDoc) and will be stored in the same location as the
FPGA project. Each used pin on the component symbol is linked to a port entry in the constraint file
by signal (net label/port) name. The names for nets in the PCB project are therefore required to be
the same as those in the FPGA project. Once linked, any changes made to the source documents of
either PCB or FPGA project can be passed on, ensuring that the two projects remain synchronized.
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1.6.1 Configuring unallocated I/O
The Wizard also allows you to determine how any unused I/O pins on the component are handled.
You have the ability to control the treatment of various categories of pin types individually – Input
only pins, VREF pins, Special Function pins and all other unused pins.
For each category, the pins can be handled in one of the following ways:
Tie to single port Tie all unused pins in the category to a single port (which will also
appear on the parent sheet symbol (if applicable) on the sheet above)
Tie to individual ports Tie all unused pins in the category to their own, individual ports
(which will also appear on the parent sheet symbol (if applicable) on
the sheet above)
Tie to ports by IO
bank (VREF only)
Tie all unused VREF pins to a port on a bank by bank basis (which
will also appear on the parent sheet symbol (if applicable) on the
sheet above).
Add No ERC directive Add a No ERC directive to an unused pin, so that it is not included as
part of error checking when the design is compiled
Ignore Do nothing with an unused pin
Figure 3. Selecting how unused I/O is to be handled
Note: For VREF pins, when the Tie to single port or Tie to ports by IO bank options are selected,
you are given the additional option of whether or not to connect via Power Ports.
1.7 Configuring the sheet symbol schematic sheet
As part of the PCB project, you have the option of defining the 'owner' of the FPGA Component
sheet (holding the component symbol for the FPGA device). The final page of the Wizard allows you
to define the owner as a sheet symbol, which, if enabled, will be created on an additional schematic
sheet, the name and location of which you can freely choose. By default, the schematic will be
named using the chosen designator for the FPGA component on the previous page of the Wizard
(e.g. FPGA_U1_Manual.SchDoc) and will be stored in the same location as the FPGA project.
In summary, after all of the options in the Wizard have been set as required, the following will be
generated:
· A new PCB project (if specified)
· A new schematic sheet, added to the new or existing PCB project, which contains the schematic
representation of the FPGA component
· A new schematic sheet with parent sheet symbol (if specified). If an existing sheet is targeted,
the parent sheet symbol for the FPGA Component schematic will be added/updated as
necessary
· A new configuration (if specified), which will be added to the FPGA project file and which
contains a new constraint file
· The constraint file – either new for a new configuration or an existing one contained in a chosen
configuration – containing:
a part constraint
a PCB board constraint
a list of constraints for all ports on the toplevel source file of the FPGA project. Each of
these port constraints is matched (and therefore linked), by net name, to the equivalent pin
on the FPGA component in the PCB project's autogenerated schematic sheet.
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1.8 Exercise 1 – Running the FPGA to PCB project wizard
In this exercise we will utilize the design targeted to the Spartan2E device and we will run through
the FPGA to PCB Project Wizard.
1. Open the design SpiritLevel.PRJFPG in the folder \Module3\Exercise 1\
2. Open the configuration manager and make sure the NB1_6_XC2S300E6PQ208.Constraint is
included in the configuration. Click OK to close the configuration manager.
3. Open the FPGA schematic document – SL_FPGA_Complete.SchDoc.
4. Select Tools » FPGA to PCB Project Wizard.
5. At the Select the FPGA Configuration step, check the Use Existing Configuration option and
specify NB_Xilinx_Spartan2 configuration. Make sure Assign Unconstrained Ports is not
checked.
Figure 4. Use an existing configuration in the FPGA to PCB Project Wizard
6. At the Configure the PCB Project step, specify the PCB Project File Name as
SpiritLevel_2E.PrjPCB.
Figure 5. Specify the PCB project file name.
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7. At the Configure the Main Sheet step, specify the Main Sheet File Name as
Auto_2E.SchDoc and any further options as depicted in Figure 6. Click Next to continue.
Figure 6. Main sheet options.
8. At the Configure th
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