74HC595

DATA SHEET Product specification Supersedes data of 1998 Jun 04 2003 Jun 25 INTEGRATED CIRCUITS 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 2003 Jun 25 2 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 FEATURES • 8-bit serial input • 8-bit serial or parallel output • Storage register with 3-state outputs • Shift register with direct clear • 100 MHz (typical) shift out frequency • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. APPLICATIONS • Serial-to-parallel data conversion • Remote control holding register. DESCRIPTION The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SH_CP input. The data in each register is transferred to the storage register on a positive-going transition of the ST_CP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC595 the condition is VI = GND to VCC. For 74HCT595 the condition is VI = GND to VCC − 1.5 V. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 74HC 74HCT tPHL/tPLH propagation delay CL = 50 pF; VCC = 4.5 V SH_CP to Q7’ 19 25 ns SH_CP to Qn 20 24 ns MR to Q7’ 100 52 ns fmax maximum clock frequency SH_CP and ST_CP 100 57 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 115 130 pF 2003 Jun 25 3 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; Z = high-impedance OFF-state; n.c. = no change; X = don’t care. ORDERING INFORMATION INPUT OUTPUT FUNCTION SH_CP ST_CP OE MR DS Q7’ Qn X X L L X L n.c. a LOW level on MR only affects the shift registers X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state ↑ X L H H Q6’ n.c. logic high level shifted into shift register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) X ↑ L H X n.c. Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6’ Qn’ contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages TYPE NUMBER PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC595N −40 to +125 °C 16 DIP16 plastic SOT38-4 74HCT595N −40 to +125 °C 16 DIP16 plastic SOT38-4 74HC595D −40 to +125 °C 16 SO16 plastic SOT109-1 74HCT595D −40 to +125 °C 16 SO16 plastic SOT109-1 74HC595DB −40 to +125 °C 16 SSOP16 plastic SOT338-1 74HCT595DB −40 to +125 °C 16 SSOP16 plastic SOT338-1 74HC595PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1 74HCT595PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1 74HC595BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1 74HCT595BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1 2003 Jun 25 4 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 PINNING PIN SYMBOL DESCRIPTION 1 Q1 parallel data output 2 Q2 parallel data output 3 Q3 parallel data output 4 Q4 parallel data output 5 Q5 parallel data output 6 Q6 parallel data output 7 Q7 parallel data output 8 GND ground (0 V) 9 Q7’ serial data output 10 MR master reset (active LOW) 11 SH_CP shift register clock input 12 ST_CP storage register clock input 13 OE output enable (active LOW) 14 DS serial data input 15 Q0 parallel data output 16 VCC positive supply voltage handbook, halfpage Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7' Q0 DS GND ST_CP SH_CP VCC OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 595 MLA001 MR Fig.1 Pin configuration DIP16, SO16 and (T)SSOP16. handbook, halfpage 1 16 GND(1) Q1 VCC 8 2 3 4 5 7 Q2 Q3 Q4 Q5 Q6 15 14 13 12 10 6 11 9 GNDTop view MBL893 Q7 Q7' MR SH_CP ST_CP OE DS Q0 Fig.2 Pin configuration DHVQFN16. (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. 2003 Jun 25 5 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, halfpage OEMR 9 15 1 2 3 4 5 6 7 1310 14 11 12 MLA002 Q1 Q0 Q2 Q3 Q4 Q5 Q6 Q7 Q7' DS ST_CPSH_CP Fig.3 Logic symbol. handbook, halfpage MSA698 15 9 1 2 3 4 5 6 7 1D 2D C1/ 10 11 14 C212 13 EN3 SRG8R 3 OE MR Q1 Q0 Q2 Q3 Q4 Q5 Q6 Q7 Q7' DS ST_CP SH_CP Fig.4 IEC logic symbol. handbook, full pagewidth ST_CP DS SH_CP MR Q7' 8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER 14 11 10 12 9 OE 3-STATE OUTPUTS Q1 Q2 Q3 Q5 Q6 Q7 Q4 Q0 15 1 2 3 4 5 6 7 13 MLA003 Fig.5 Functional diagram. 2003 Jun 25 6 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth STAGE 0 STAGES 1 to 6 STAGE 7 FF0 D CP Q R LATCH D CP Q FF7 D CP Q R LATCH D CP Q MLA010 D Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7' Q0 DS ST_CP SH_CP OE MR Fig.6 Logic diagram. 2003 Jun 25 7 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth high-impedance OFF-state ST_CP DS SH_CP MR OE Q1 Q0 Q7' Q6 Q7 MLA005-1 Fig.6 Timing diagram. 2003 Jun 25 8 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 RECOMMENDED OPERATING CONDITIONS LIMITED VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Note 1. For DIP16 packages: above 70 °C derate linearly with 12 mW/K. For SO16 packages: above 70 °C derate linearly with 8 mW/K. For SSOP16 packages: above 60 °C derate linearly with 5.5 mW/K. For TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K. SYMBOL PARAMETER CONDITIONS 74HC 74HCT UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb ambient temperature −40 − +125 −40 − +125 °C tr, tf input rise and fall time VCC = 2.0 V − − 1000 − − − ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns VCC = 6.0 V − − 400 − − − ns SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +7.0 V IIK input diode current VI < −0.5 V to VI > VCC + 0.5 V − ±20 mA IOK output diode current VO < −0.5 V to VO > VCC + 0.5 V − ±20 mA IO output source or sink current VO = −0.5 V to VCC + 0.5 V Q7’ standard output − ±25 mA Qn bus driver outputs − ±35 mA ICC, IGND VCC or GND current − ±70 mA Tstg storage temperature −65 +150 °C Ptot power dissipation Tamb = −40 to +125 °C; note 1 − 500 mW 2003 Jun 25 9 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 DC CHARACTERISTICS Type 74HC At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V VIL LOW-level input voltage 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = −20 µA 2.0 1.9 2.0 − V 4.5 4.4 4.5 − V 6.0 5.9 6.0 − V Q7’ standard output IO = −4.0 mA 4.5 3.84 4.32 − V IO = −5.2 mA 6.0 5.34 5.81 − V Qn bus driver outputs IO = −6.0 mA 4.5 3.84 4.32 − V IO = −7.8 mA 6.0 5.34 5.81 − V VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA 2.0 − 0 0.1 V 4.5 − 0 0.1 V 6.0 − 0 0.1 V Q7’ standard output IO = 4.0 mA 4.5 − 0.15 0.33 V IO = 5.2 mA 6.0 − 0.16 0.33 V Qn bus driver outputs IO = 6.0 mA 4.5 − 0.16 0.33 V IO = 7.8 mA 6.0 − 0.16 0.33 V ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 6.0 − − ±5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 80 µA 2003 Jun 25 10 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Note 1. All typical values are measured at Tamb = 25 °C. Tamb = −40 to +125 °C VIH HIGH-level input voltage 2.0 1.5 − − V 4.5 3.15 − − V 6.0 4.2 − − V VIL LOW-level input voltage 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = −20 µA 2.0 1.9 − − V 4.5 4.4 − − V 6.0 5.9 − − V Q7’ standard output IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.2 − − V Qn bus driver outputs IO = −6.0 mA 4.5 3.7 − − V IO = −7.8 mA 6.0 5.2 − − V VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA 4.5 − − 0.1 V Q7’ standard output IO = 4.0 mA 4.5 − − 0.4 V Qn bus driver outputs IO = 6.0 mA 4.5 − − 0.4 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 160 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) 2003 Jun 25 11 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Type 74HCT At recommended operating conditions; voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = −20 µA 4.5 4.4 4.5 − V Q7’ standard output IO = −4.0 mA 4.5 3.84 4.32 − V Qn bus driver outputs IO = −6.0 mA 4.5 3.7 4.32 − V VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA 4.5 − 0 0.33 V Q7’ standard output IO = 4.0 mA 4.5 − 0.15 0.33 V Qn bus driver outputs IO = 6.0 mA 4.5 − 0.16 0.33 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 80 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0; note 2 4.5 to 5.5 − 100 450 µA 2003 Jun 25 12 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Notes 1. All typical values are measured at Tamb = 25 °C. 2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input, multiply this value by the unit load coefficient per input pin: a. pin DS: 0.25 b. pins MR, SH_CP, ST_CP and OE: 1.50. Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = −20 µA 4.5 4.4 − − V Q7’ standard output IO = −4.0 mA 4.5 3.7 − − V Qn bus driver outputs IO = −6.0 mA 4.5 3.7 − − V VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA 4.5 − − 0.1 V Q7’ standard output IO = 4.0 mA 4.5 − − 0.4 V Qn bus driver outputs IO = 6.0 mA 4.5 − − 0.4 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 160 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0; note 2 4.5 to 5.5 − − 490 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) 2003 Jun 25 13 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 AC CHARACTERISTICS Family 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb = 25 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 − 52 160 ns 4.5 − 19 32 ns 6.0 − 15 27 ns propagation delay ST_CP to Qn see Fig.8 2.0 − 55 175 ns 4.5 − 20 35 ns 6.0 − 16 30 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 − 47 175 ns 4.5 − 17 35 ns 6.0 − 14 30 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 − 47 150 ns 4.5 − 17 30 ns 6.0 − 14 26 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 − 41 150 ns 4.5 − 15 30 ns 6.0 − 12 26 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 75 17 − ns 4.5 15 6 − ns 6.0 13 5 − ns storage clock pulse width HIGH or LOW see Fig.8 2.0 75 11 − ns 4.5 15 4 − ns 6.0 13 3 − ns master reset pulse width LOW see Fig.10 2.0 75 17 − ns 4.5 15 6.0 − ns 6.0 13 5.0 − ns tsu set-up time DS to SH_CP see Fig.9 2.0 50 11 − ns 4.5 10 4.0 − ns 6.0 9.0 3.0 − ns set-up time SH_CP to ST_CP see Fig.8 2.0 75 22 − ns 4.5 15 8 − ns 6.0 13 7 − ns th hold time DS to SH_CP see Fig.9 2.0 +3 −6 − ns 4.5 +3 −2 − ns 6.0 +3 −2 − ns 2003 Jun 25 14 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 trem removal time MR to SH_CP see Fig.10 2.0 +50 −19 − ns 4.5 +10 −7 − ns 6.0 +9 −6 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 9 30 − MHz 4.5 30 91 − MHz 6.0 35 108 − MHz Tamb = −40 to +85 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 − − 200 ns 4.5 − − 40 ns 6.0 − − 34 ns propagation delay ST_CP to An see Fig.8 2.0 − − 220 ns 4.5 − − 44 ns 6.0 − − 37 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 − − 220 ns 4.5 − − 44 ns 6.0 − − 37 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 − − 190 ns 4.5 − − 38 ns 6.0 − − 33 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 − − 190 ns 4.5 − − 38 ns 6.0 − − 33 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns storage clock pulse width HIGH or LOW see Fig.8 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns master reset pulse width LOW see Fig.10 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns tsu set-up time DS to SH_CP see Fig.9 2.0 65 − − ns 4.5 13 − − ns 6.0 11 − − ns set-up time SH_CP to ST_CP see Fig.8 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) 2003 Jun 25 15 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 th hold time DS to SH_CP see Fig.9 2.0 3 − − ns 4.5 3 − − ns 6.0 3 − − ns trem removal time MR to SH_CP see Fig.10 2.0 65 − − ns 4.5 13 − − ns 6.0 11 − − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.8 − − MHz 4.5 24 − − MHz 6.0 28 − − MHz Tamb = −40 to +125 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 − − 240 ns 4.5 − − 48 ns 6.0 − − 41 ns propagation delay ST_CP to Qn see Fig.8 2.0 − − 265 ns 4.5 − − 53 ns 6.0 − − 45 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 − − 265 ns 4.5 − − 53 ns 6.0 − − 45 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 − − 225 ns 4.5 − − 45 ns 6.0 − − 38 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 − − 225 ns 4.5 − − 45 ns 6.0 − − 38 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns storage clock pulse width HIGH or LOW see Fig.8 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns master reset pulse width LOW see Fig.10 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) 2003 Jun 25 16 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 tsu set-up time DS to SH_CP see Fig.9 2.0 75 − − ns 4.5 15 − − ns 6.0 13 − − ns set-up time SH_CP to ST_CP see Fig.8 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns th hold time DS to SH_CP see Fig.9 2.0 3 − − ns 4.5 3 − − ns 6.0 3 − − ns trem removal time MR to SH_CP see Fig.10 2.0 75 − − ns 4.5 15 − − ns 6.0 13 − − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4 − − MHz 4.5 20 − − MHz 6.0 24 − − MHz SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) 2003 Jun 25 17 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Family 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb = 25 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 − 25 42 ns propagation delay ST_CP to Qn see Fig.8 4.5 − 24 40 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − 23 40 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − 21 35 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − 18 30 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 16 6 − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 16 5 − ns master reset pulse width LOW see Fig.10 4.5 20 8 − ns tsu set-up time DS to SH_CP see Fig.9 4.5 16 5 − ns set-up time SH_CP to ST_CP see Fig.8 4.5 16 8 − ns th hold time DS to SH_CP see Fig.9 4.5 +3 −2 − ns trem removal time MR to SH_CP see Fig.10 4.5 +10 −7 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 30 52 − MHz Tamb = −40 to +85 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 − − 53 ns propagation delay ST_CP to Qn see Fig.8 4.5 − − 50 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − − 50 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − − 44 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − − 38 ns 2003 Jun 25 18 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 tW shift clock pulse width HIGH or LOW see Fig.7 4.5 20 − − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 20 − − ns master reset pulse width LOW see Fig.10 4.5 25 − − ns tsu set-up time DS to SH_CP see Fig.9 4.5 20 − − ns set-up time SH_CP to ST_CP see Fig.8 4.5 20