LA7321P_PBL50

A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P01-Cover Page B 1 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P01-Cover Page B 1 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P01-Cover Page B 1 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. AMD APU Zacate-FT1 + FCH Hudson-M1 + DGPU Seymour XT-M2 PBL50 Schematics Document REV:0.22 Compal Confidential 2011-02-15 ZZZ PCB Part Number = DA60000M700 ZZZ PCB Part Number = DA60000M700 A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P02-Block Diagrams B 2 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P02-Block Diagrams B 2 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P02-Block Diagrams B 2 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. BGA 605-Ball 23mm x 23mm AMD Brazos APU UMI Gen.1 x4 Hudson M1 page 5,6,7 page 12 ~ 16 Single Channel BANK 0, 1, 2, 3 204pin DDRIII-SO-DIMM X2 1.5V DDRIII Memory BUS(DDRIII) page 8,9 PCI-E 2.0 x1 FT1 BGA 413-Ball 19mm x 19mm LAN(GbE) RTL8111E 2.5GT/s per lane Mini Card WLAN (With Bluetooth) USB Conn. SATA HDD Conn. SATA ODD Conn.SATA Camera Audio Codec ALC269 VB5 2Channel Speaker AZALIA USB2.0 USB Conn. (LS-7322P) Card Reader RTS5137 SPI ROM LPC BUS Int.KBD Touch Pad ENE KB930 Thermal Sensor File Name : LA-7321P Compal confidential page 25 page 26 page 26 page 18 page 28 page 29 page 28 page 30 page 31 page 31 page 30 page 27 page 32 page 26 page 10 Mini Card-1 WLAN (With Bluetooth) RJ45 Port 0Port 1 Port 1 Port 5 Port 2 Port 3 Port 4 Port 0 Port 1 USB Conn. page 32 Port 0 page 29 page 25 Audio Jacks X 2 (Headphone, MIC) DMIC page 10 page 26 page 17 ~ 23 DDR3*4 AMD SeymourXT-M2 VRAM 64M*16 / 128M*16 PCI-E GPP x4 GEN2 HDMI(UMA & PX) CRT(UMA & PX) LVDS(UMA & PX)LVDS Conn. CRT Conn. page 10 page 10 page 11 HDMI Conn. LS-7322P page 26 LS-7321P page 33 Sub-Board Sub-Board Audio Jack & USB PWR/B & LID Sub-Board RTC CKT page 12 Power On/Off CKT page 33 DC/DC CKT page 24,34 Power Circuit page 35 ~ 44 Fan Control page 33 3 in 1 Socket page 27 A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P03-Notes List B 3 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P03-Notes List B 3 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P03-Notes List B 3 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. +APU_CORE_NB 1.0V switched power rail ON OFF +0.75VS 0.75VS switched power rail for DDR terminator +RTCVCC RTC power +1.8VS 1.8V switched power rail +5VS +3VS +5VALW +1.5V +3VALW 1.5V power rail for CPU VDDIO and DDRIII 3.3V always on power rail 5V always on power rail 3.3V switched power rail 5V switched power rail +VSB VSB always on power rail ON ON* ONON ON ON ON OFF OFF +APU_CORE Voltage Rails VIN B+ +1.0VS Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU (0.7-1.2V) OFF 1.0V switched power rail for NB VDDC & VGA +1.1VS 1.1VS switched power rail ON OFF OFF ON ON* ON OFF OFF +3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF S1 S3 S5 ON OFF ON N/A N/A N/A N/AN/AN/A Power Plane Description OFF OFF ON OFF OFF ON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. OFFON ON ON ON ON* OFF OFF ON OFF ON ON*ON+1.1VALW 1.1V always on power rail FCH Hudson-M1 USB Port List USB1.1 USB2.0 Port0 Port1 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port11 Port12 Port13 JUSB1 JUSB2 JUSB3 Camera JMINI(WLAN) Card Reader NC NC NC NC NC NC NC NC NC NC Brazos PCIE Port List PCIE0 PCIE1 PCIE2 PCIE3 PCIE0 PCIE1 PCIE2 PCIE3 A P U F C H GPU PCIE x4 LAN WLAN NC NC FCH Hudson-M1 SATA Port List SATA0 SATA1 SATA2 SATA3 SATA4 SATA5 HDD ODD NC NC NC BOM Structure NC Symbol Note : : means Digital Ground : means Analog Ground SCL0, SDA0 (Primary SMBUS in the S0 domain) SCL1, SDA1 (Secondary SMBUS supporting ASF) SCL2, SDA2 (Primary SMBUS in the S5 domain) SCL3, SDA3 (Primary low-voltage SBMBUS for Processor TSI) SCL4, SDA4 (Primary SMBUS in the S5 domain) V APU FCH EC_SMB_CK2 SOURCE KB930 MIINI1 BATT SODIMM SMBUS Control Table FCH_SMCLK0 FCH_SMDAT0 FCH EC_SMB_DA2 EC_SMB_CK1 EC_SMB_DA1 KB930 FCH_SIC FCH X X X X X X X X XV X FCH_SID V V V X X V VRAM X X XXV PU Rail +3VALW +3VALW +3VS 10G@ : 1.0G CPU (C50) 15G@ : 1.5G CPU (E240) 16G@ : 1.6G CPU (E350) UMA@ : APU output. VGA@ : GPU used. LS@ : Level shift used. X76@ : VRAM. +3VS V Reserve X76@L01: Samsung 1G X76@L02: Hynix 1G X76@L03: Samsung 512M X76@L04: Hynix 512M DIS M/B BOM Config L01: 16G@/VGA@/LS@ --X76@L04 L02: 16G@/UMA@/LS@ L03: 15G@/VGA@/LS@ --X76@L03 L04: 15G@/UMA@/LS@ L05: 16G@/VGA@/LS@ --X76@L01 L06: 15G@/VGA@/LS@ --X76@L02 L07: 10G@/UMA@/LS@ jzxy 高亮 jzxy 高亮 jzxy 铅笔 jzxy 铅笔 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P04-dGPU Block Diagram B 4 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P04-dGPU Block Diagram B 4 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P04-dGPU Block Diagram B 4 46Tuesday, February 15, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Note: Do not drive any IOs before VDDR3 is ramped up. VDD_CT(1.8V) VDDR3(3.3VSG) VDDC/VDDCI(1.12V) PERSTb Straps Reset Straps Valid REFCLK VDDR1(1.5VSG) Power-Up/Down Sequence 1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. 2. VDDR3 should ramp-up before or simultaneously with VDDC. 3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. 4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up. 5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).) PCIE_VDDC(1.0V) Global ASIC Reset T4+16clock dGPU Power Pins Max current 1679mA 575mA 2A 190mA 70mA 2.8A 12.9A PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18 DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10 PCIE_VDDC VDDR3 , and A2VDD BIF_VDDC (current consumption = 55mA@1.0V, in BACO mode) VDDR1 VDDC/VDDCI Voltage 1.8V 1.0V 1.0V 3.3V VDDC Same as 1.5V 1.12V PX 3.0 OFF MOS OFF OFF OFF OFF OFF OFF BACO Mode ON ON ON ON ON Same as PCIE_VDDC OFF OFF +1.0VSG +3.3VSG +1.5VSG +VGA_CORE +1.8VSG iGPU +1.0V dGPU +3.3VALW PE_GPIO1 +1.5V +B +1.8V PE_GPIO0 PE_EN BACO Switch BIF_VDDC PX_mode PWRGOOD PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON Without BACO option : BACO option : PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode) PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High) SI4800 SI4800 Regulator Regulator 1 2 3 4 5 5 5 4 4 3 3 2 2 1 1 D D C C B B A A APU_RST# APU_PWRGD APU_SVC APU_PROCHOT# APU_THERMTRIP# APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# APU_SIC APU_SID APU_SVD APU_ALERT#_R APU_SIC APU_SID TEST19 TEST18 TEST25_H TEST_25_L APU_PROCHOT# APU_THERMTRIP# TEST31 TEST36 TEST37 TEST15 TEST_25_L TEST33_H TEST33_L TEST36 APU_LCD_CLK APU_LCD_DATA APU_HDMI_DATA APU_HDMI_CLK J108_PLLTST0 APU_TDO J108_PLLTST1 APU_PWRGD TEST19 TEST18 APU_TRST#_R APU_RST# APU_TCK APU_DBRDY APU_TMS APU_DBREQ# APU_TRST# APU_TDI TEST35 FCH_SID FCH_SIC EC_SMB_CK2 EC_SMB_DA2 EC_SMB_DAAPU_SID EC_SMB_CKAPU_SIC APU_ALERT#_R APU_RST# APU_PWRGD APU_CLKP12 APU_CLKN12 APU_DISP_CLKP12 APU_DISP_CLKN12 APU_RST#12 APU_PWRGD12 H_THERMTRIP# 13 APU_HDMI_HPD 11 ALLOW_STOP# 12 APU_ENBKL 10 APU_ENVDD 10 APU_BLPWM 10 APU_CRT_HSYNC 10 APU_CRT_VSYNC 10 APU_CRT_DDC_SCL 10 APU_CRT_DDC_SDA 10 APU_VDDNB_RUN_FB_H43 APU_VDD0_RUN_FB_H43 APU_SVC43 APU_SVD43 APU_LCD_CLK 10 APU_LCD_DATA 10 APU_TXOUT2+10 APU_TXOUT2-10 APU_TXCLK+10 APU_TXCLK-10 APU_TXOUT0+10 APU_TXOUT0-10 APU_TXOUT1+10 APU_TXOUT1-10 APU_VDD0_RUN_FB_L43 APU_HDMI_DATA 11 APU_HDMI_CLK 11 EC_SMB_DA2 18,30 FCH_SIC 13 FCH_SID 13 EC_SMB_CK2 18,30 EC_THERM#30 FCH_PROCHOT#12 APU_HDMI_TX2N11 APU_HDMI_TX2P11 APU_HDMI_TX1N11 APU_HDMI_TX1P11 APU_HDMI_TX0N11 APU_HDMI_TX0P11 APU_HDMI_CLKN11 APU_HDMI_CLKP11 APU_CRT_R 10 APU_CRT_G 10 APU_CRT_B 10 +1.8VS +3VS +3VS +1.8VS +1.8VS +1.8VS +1.8VS +1.8VS +3VS +5VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P05-FT1 CTRL/DP/CRT Custom 5 46Thursday, February 17, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P05-FT1 CTRL/DP/CRT Custom 5 46Thursday, February 17, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA7321P PBL50 0.22 P05-FT1 CTRL/DP/CRT Custom 5 46Thursday, February 17, 2011 2010/11/25 2011/12/31 Compal Electronics, Inc. If FCH internal pull-up disabled, level-shifter could be deleted. Need BIOS to disable internal pull-up!! Close to APU AMD Debug Please be noted about TEST_18 and TEST_19 CPU TSI interface level shift BSH111, the Vgs is: min = 0.4V Typ = 1.0V Max = 1.3V FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V 1.607V for Gate T0 FCH TO EC TO EC T0 FCH If use level shift, EC_SMB need pull up (pop R747 & R748) Delete Test point for layout limitation 20100917 APU 15G@: SA00004KF50 (S IC ZACATE EME240GBB12GT 1.5G BGA 413P) - E240 APU 16G@: SA00004KG70 (S IC ZACATE EME350GBB22GT 1.6G BGA 413P) - E350 APU 10G@: SA00004KD70 (S IC ONTARIO CMC50AFPB22GT 1.0G BGA 413P) - C50 R415 1K_0402_5%@R415 1K_0402_5%@1 2 R168 0_0402_5%@R168 0_0402_5%@1 2 R176 10K_0402_5% R176 10K_0402_5% 12 R428 31.6K_0402_1% @ R428 31.6K_0402_1% @ 1 2 R843 1K_0402_5% R843 1K_0402_5% 12 R430 0_0402_5%R430 0_0402_5% 1 2 R410 1K_0402_5% R410 1K_0402_5% 1 2 R799 0_0402_5%R799 0_0402_5%1 2 R143 1K_0402_5% R143 1K_0402_5% 1 2 R425 1K_0402_5% R425 1K_0402_5% 1 2 R846 0_0402_5%R846 0_0402_5%1 2 R407 150_0402_1% R407 150_0402_1% 1 2 R840 1K_0402_5% R840 1K_0402_5% 12 G DS Q23 BSH111 1N_SOT23-3 @ G DS Q23 BSH111 1N_SOT23-3 @ 2 13 R417 1K_0402_5% R417 1K_0402_5% 1 2 R424 10K_0402_5%@ R424 10K_0402_5%@ 1 2 R414 1K_0402_5% R414 1K_0402_5% 1 2 U22 ZACATE EME350GBB22GT 1.6G BGA 413P 16G@U22 ZACATE EME350GBB22GT 1.6G BGA 413P 16G@ C237 0.01U_0402_25V7K @ C237 0.01U_0402_25V7K @1 2 R434 0_0402_5%R434 0_0402_5% 1 2 T76PAD @ T76PAD @ R416 1K_0402_5% R416 1K_0402_5% 1 2 C516 0.1U_0402_16V4Z C516 0.1U_0402_16V4Z 1 2 T94PAD @ T94PAD @ R409 150_0402_1% R409 150_0402_1% 1 2 R847 10K_0402_5% R847 10K_0402_5%