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or1ktools

188*****902@sina.cn 2012-04-02 评分 0 浏览量 0 0 0 0 暂无简介 简介 举报

简介:本文档为《or1ktoolspdf》,可适用于IT/计算机领域,主题内容包含BuildingaMinimalOpenRISCSystemMatthewHicksUniversityofIllinoisatUrbanaCham符等。

BuildingaMinimalOpenRISCSystemMatthewHicksUniversityofIllinoisatUrbanaChampaignTousetheOROpenRISCprocessorweneedtocombineitwithseveralotherperipherals,usingtheirwishboneinterfaces,creatingasystemonchip(SoC)AbasicSoCcontainstheORprocessorwithJTAGbaseddebuginterface,aninternalmemory,andaUARTThisallowsforsmallprogramstobeloadedintomemoryusingtheXilinxUSBprogrammingcablewhichusesoneoftheFPGA’suserJTAGaccessportsTheprocessorrunstheprogramfrommemory,outputtingconsoletexttotheUARTportThissystemissufficientenoughtolearnhowtobuildasystem,compilesoftwareforthatsystem,attachadebugger,andruna”HelloWorld”programPrerequisites•XilinxXUPVdevelopmentboard(akaML)•Linux•XilinxISEwithbindirectoryaddedtothePATH•RStoUSBadapter•cutecomBuildingthehardwareDownloadthesvnrepositoriesforeachcoreintheSoCintoacommonfolder(a)svncohttp:opencoresorgocsvnadvdebugsysadvdebugsystrunkadvdebugsys(b)svncohttp:opencoresorgocsvnopenriscopenrisctrunkoror(c)svncohttp:opencoresorgocsvnuartuarttrunkuart(d)svncohttp:opencoresorgocsvnminsocminsoctrunkminsocConfigurethecores(a)TheVerilogoptionsfilefortheXilinxJTAGuserinterfaceofadvdebugsysneedstobeupdatedwiththecorrectmodelFPGAThefileislocatedinadvdebugsysHardwarexilinxinternaljtagrtlverilogUncommenttheVIRTEXlineandensureallotherlinesarecommentedout(b)TheVerilogdefinesfileforthedebuginterface(advdebugsys)needstobeupdatedwiththecorrectparametersThefileislocatedinadvdebugsysHardwareadvdbgifrtlverilogCommentoutthedefinitionofDBGJSPSUPPORTEDandADBGJSPSUPPORTMULTI(c)TheVerilogdefinesfileforthetopleveldesignneedstobeconfiguredsothattheminimalSoCisimplementedcorrectlyThefileislocatedinminsocrtlverilogUncommentandcommentlinesasrequiredtobuildaSoCwithonlydebug,UART,andinternalmemoryperipherals,foraXilinxVirtexFPGA,runningatMHZ(inputclockisMHz),withnegativeresetItiskeythatETHERNETandSTARTUPareleftundefinedPreparetheMakefile(a)CopytheMakefiletothedirectorywhereallthesvnreposofthecoreswerecheckedoutinto(b)CopytheMakefilesupportfiles(prjandxst)folderbuildSupporttothedirectorywhereallsvnreposwerecheckedoutinto(c)UpdatetheROOTdirectoryinMakefiletothepathofthecorerepocontainingdirectoryVerifytheexistenceorcreateaconstraints(ucf)fileforyourdevelopmentboardinminsocbackendCopytheblackBoxesfoldertothefolderwherethecoresarecheckedoutinto(a)Inordertoreducesynthesistimesandkeepthesystemmoremodular,thisprojectsynthesizeseachcoreseparately,thenconnectstheresultingnetliststogether,atthetoplevel,usingaWISHBONEcompliantbusTodothis,thetopleveltreatseachcoreasablackboxduringsynthesisThisrequiresanempty,interfaceonlyversionofeachcore’stopleveldesignfileTheblackBoxesfoldercontainsaninterfaceversionoftheUART,OR,anddebugcores(b)AddingotherperipheralstotheSoCrequirescreatinganinterfaceversionofthatperipheral’stoplevelfileandthenaddingittotheblackBoxesfolderTodothis,removealllogicfromtheperipheral’stoplevelHDLfile,keepingonlytheinputoutputdescriptionmakeallsynthesizes,translates,maps,placesandroutes,thengeneratesabitstreamfortheSoC(a)makehelpprovidesmoreinformationaboutothermaketargetsProblems(a)MissingVerilogfilesduetocoredesigneraddingorremovingfilesfromthedesign(b)ChangeinXilinxcommandlinetoolsacceptedswitchesProgrammingtheFPGAMakesurethattheFPGAisconfiguredtoloadconfigurationdatafromJTAGanduseXilinx’sImpacttooltoloadthebitfile(minsocbit)ontotheFPGAInstallingorksim,theOpenRISCSimulatororksimisaninstructionlevelsimulatorfortheOpenRISCplatformItiscapableofbootingLinuxandrunningbaremetalprogramsorksimisrequiredforbuildingtheOpenRISCGCCtoolchainfromsourcesvncohttp:opencoresorgocsvnopenriscopenrisctrunkorksimorksimmkdirorksimbuildcdorksimbuildorksimconfiguretarget=orelfprefix=optorksimmakeallsudomakeinstallcdrmrforksimbuildAddoptorksimbintoyourPATHvariableInstalltheOpenRISCGCCToolchainCheckoutthetoolchainsourcesvncohttp:opencoresorgocsvnopenriscopenrisctrunkgnusrcorGNUVerifythattheentirerepositorywastransferedusing“svnupdate”Librariesrequiredforbuildingthetoolchain(a)buildessential(b)make(c)gcc(d)g(e)flex(f)bison(g)patch(h)texinfo(i)libncursesdev(j)libmpfrdev(k)libgmpdev(l)libmpcdev(m)libzipdevDownloadClibraryandLinuxkernelsources(a)Verifygitisinstalled(b)cdorGNU(c)gitclonegit:gitopenriscnetjonasuClibc(d)gitclonegit:gitopenriscnetjonaslinuxIntheorGNUfolder,buildbothbaremetal(newlib,orelf)andLinux(uLibC,orlinux)OpenRISCtoolchainsbyexecutingthecommandsudobldallshforceprefixoptopenriscuclibcdiruClibclinuxdirlinuxorksimdiroptorksimUpdateyourPATHvariabletoincludeoptopenriscbinrmrforGNUIfyouhaveproblemsvisithttp:opencoresorgopenrisc,gnutoolchainWriteandCompilea“HelloWorld”ProgramcdminsocswutilsmakecleanmakeallcdminsocswsupportInbothexceptSandresetS,removeallunderscoreprefixesfromallreferencedfunctionsUpdateboardhwiththecorrectfrequency“defineINCLK”makecleanmakeallcdminsocswdriversmakecleanmakeallcdminsocswuartmakecleanmakeallCompiletheDebugInterfacecdadvdebugsyssoftwareadvjtagbridgeConfiguretheMakefile(a)Change“prefix”tothepathwherethebinarywillbestored,inabinfolder(b)Selectthecorrectoptionfor“BUILDENVIRONMENT”(c)Change“INCLUDEJSPSERVER=true”to“INCLUDEJSPSERVER=false”makesudomakeinstallAdd“prefix”bintoyouPATHvariableGathertheJTAGDeviceFilesCopythebsdlFilesfoldertothedirectorywhereallthecoreswerecheckedoutinto(a)TofindthebsdlfilesforallthedevicesontheJTAGchainoftheFPGA,firstcreatealistofdevicesusingXilinx’sImpacttool(b)LocatethebsdfileforeachdeviceintheXilinxISEinstallationfoldersandcopyittothebsdlFilesfolderDebuggingStarttheJTAGbridgesoftware(a)cdbsdlFiles(b)advjtagbridgexpcusbStartcutecom(a)Changetothecutecomfolder(b)sudocutecom(c)Setthebaudrateto(d)UsedevicedevttyUSB(e)ConnecttotheboardLoadandruntheuartprogramusinggdb(a)cdminsocswuart(b)orelfgdbuartnocacheor(c)setremotetimeout(d)targetremote:(e)load(f)cHelloWorldIfeverthingissetupcorrectly,youshouldsee“HelloWorld”printedinthecutecomwindowAdditionally,whatevertextyousendtotheboardusingcutecomwillbereturned,butusingthenextASCIIcharacter

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