开关电源2n60b

©2001 Fairchild Semiconductor Corporation November 2001 Rev. B, November 2001 SSW 2N 60B / SSI2N 60B SSW2N60B / SSI2N60B 600V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies. Features • 2.0A, 600V, RDS(on) = 5.0Ω @VGS = 10 V • Low gate charge ( typical 12.5 nC) • Low Crss ( typical 7.6 pF) • Fast switching • 100% avalanche tested • Improved dv/dt capability Absolute Maximum Ratings TC = 25°C unless otherwise noted Thermal Characteristics Symbol Parameter SSW2N60B / SSI2N60B Units VDSS Drain-Source Voltage 600 V ID Drain Current - Continuous (TC = 25°C) 2.0 A - Continuous (TC = 100°C) 1.3 A IDM Drain Current - Pulsed (Note 1) 6.0 A VGSS Gate-Source Voltage ± 30 V EAS Single Pulsed Avalanche Energy (Note 2) 120 mJ IAR Avalanche Current (Note 1) 2.0 A EAR Repetitive Avalanche Energy (Note 1) 5.4 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns PD Power Dissipation (TA = 25°C) * 3.13 W Power Dissipation (TC = 25°C) 54 W - Derate above 25°C 0.43 W/°C TJ, Tstg Operating and Storage Temperature Range -55 to +150 °C TL Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 300 °C Symbol Parameter Typ Max Units RθJC Thermal Resistance, Junction-to-Case -- 2.32 °C/W RθJA Thermal Resistance, Junction-to-Ambient * -- 40 °C/W RθJA Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W * When mounted on the minimum pad size recommended (PCB Mount) ●●●● ●●●● ●●●● ▲▲▲▲ !!!! !!!! !!!! ◀◀◀◀ ●●●● ●●●● ●●●● ▲▲▲▲ !!!! !!!! !!!! ◀◀◀◀ S D G D2-PAK SSW Series I2-PAK SSI Series G S D G SD Rev. B, November 2001 SSW 2N 60B / SSI2N 60B (Note 4) (Note 4, 5) (Note 4, 5) (Note 4) ©2001 Fairchild Semiconductor Corporation Electrical Characteristics TC = 25°C unless otherwise noted Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 55mH, IAS = 2.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 2.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 600 -- -- V ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.65 -- V/°C IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V -- -- 10 µA VDS = 480 V, TC = 125°C -- -- 100 µA IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2.0 -- 4.0 V RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 1.0 A -- 3.8 5.0 Ω gFS Forward Transconductance VDS = 40 V, ID = 1.0 A -- 2.05 -- S Dynamic Characteristics Ciss Input Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz -- 380 490 pF Coss Output Capacitance -- 35 46 pF Crss Reverse Transfer Capacitance -- 7.6 9.9 pF Switching Characteristics td(on) Turn-On Delay Time VDD = 300 V, ID = 2.0 A, RG = 25 Ω -- 16 40 ns tr Turn-On Rise Time -- 50 110 ns td(off) Turn-Off Delay Time -- 40 90 ns tf Turn-Off Fall Time -- 40 90 ns Qg Total Gate Charge VDS = 480 V, ID = 2.0 A, VGS = 10 V -- 12.5 17 nC Qgs Gate-Source Charge -- 2.2 -- nC Qgd Gate-Drain Charge -- 5.4 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 2.0 A ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 6.0 A VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.0 A -- -- 1.4 V trr Reverse Recovery Time VGS = 0 V, IS = 2.0 A, dIF / dt = 100 A/µs -- 250 -- ns Qrr Reverse Recovery Charge -- 1.31 -- µC Rev. B, November 2001©2001 Fairchild Semiconductor Corporation SSW 2N 60B / SSI2N 60B 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10-1 100 150℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test 25℃ I DR , R ev er se D ra in Cu rre nt [A ] VSD, Source-Drain voltage [V] 2 4 6 8 10 10-1 100 150oC 25oC -55oC ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test I D, D ra in Cu rre nt [A ] VGS, Gate-Source Voltage [V] 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 VDS = 300V VDS = 120V VDS = 480V ※ Note : ID = 2.0 A V G S, Ga te- So ur ce V olt ag e [ V] QG, Total Gate Charge [nC] 10-1 100 101 0 200 400 600 800 Coss Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd ※ Notes : 1. VGS = 0 V 2. f = 1 MHzCrss Ciss Ca pa cit an ce [p F] VDS, Drain-Source Voltage [V] 0 1 2 3 4 5 6 0 3 6 9 12 15 18 VGS = 20V VGS = 10V ※ Note : TJ = 25℃ R D S( ON ) [Ω ], Dr ain -S ou rce O n- Re sis tan ce ID, Drain Current [A] 10-1 100 101 10-2 10-1 100 VGS Top : 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ I D, D ra in Cu rre nt [A ] VDS, Drain-Source Voltage [V] Typical Characteristics Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature Figure 2. Transfer CharacteristicsFigure 1. On-Region Characteristics ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSW 2N 60B / SSI2N 60B -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ※ Notes : 1. VGS = 10 V 2. ID = 1.0 A R D S( ON ) , ( No rm ali ze d) Dr ain -S ou rce O n- Re sis tan ce TJ, Junction Temperature [ oC] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA BV DS S , (N orm ali ze d) Dr ain -S ou rce B rea kd ow n V olt ag e TJ, Junction Temperature [ oC] 1 0 -5 1 0 -4 1 0 -3 1 0 -2 1 0 -1 1 0 0 1 0 1 1 0 -2 1 0 -1 1 0 0 ※ N o te s : 1 . Z θ JC ( t) = 2 .32 ℃ /W M a x . 2 . D u ty Fa c to r, D = t1/t2 3 . T JM - T C = P D M * Z θ JC( t) s in g le p u ls e D = 0 .5 0 .0 2 0 .2 0 .0 5 0 .1 0 .0 1 Z θ JC (t ), T h e rm a l R e sp o n se t1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] 25 50 75 100 125 150 0.0 0.4 0.8 1.2 1.6 2.0 I D, D ra in Cu rre nt [A ] TC, Case Temperature [℃] 100 101 102 103 10-2 10-1 100 101 DC 10 ms 1 ms 100 µs Operation in This Area is Limited by R DS(on) ※ Notes : 1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse I D, D ra in Cu rre nt [A ] VDS, Drain-Source Voltage [V] Typical Characteristics (Continued) Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs Case Temperature Figure 7. Breakdown Voltage Variation vs Temperature Figure 8. On-Resistance Variation vs Temperature Figure 11. Transient Thermal Response Curve t1 PDM t2 Rev. B, November 2001©2001 Fairchild Semiconductor Corporation SSW 2N 60B / SSI2N 60B Charge VGS 10V Qg Qgs Qgd 3mA VGS DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT Charge VGS 10V Qg Qgs Qgd 3mA VGS DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT VGS VDS 10% 90% td(on) tr t on t off td(off) tf VDD 10V VDS RL DUT RG VGS VGS VDS 10% 90% td(on) tr t on t off td(off) tf VDD 10V VDS RL DUT RG VGS EAS = L IAS2----2 1 -------------------- BVDSS - VDD BVDSS VDD VDS BVDSS t p VDD IAS VDS (t) ID (t) Time 10V DUT RG L I D t p EAS = L IAS2----2 1EAS = L IAS2----2 1---- 2 1 -------------------- BVDSS - VDD BVDSS VDD VDS BVDSS t p VDD IAS VDS (t) ID (t) Time 10V DUT RG LL I DI D t p Gate Charge Test Circuit & Waveform Resistive Switching Test Circuit & Waveforms Unclamped Inductive Switching Test Circuit & Waveforms ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSW 2N 60B / SSI2N 60B Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT VDS + _ Driver RG Same Type as DUT VGS • dv/dt controlled by RG • ISD controlled by pulse period VDD L I SD 10V VGS ( Driver ) I SD ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop VSD IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width Gate Pulse Period -------------------------- DUT VDS + _ Driver RG Same Type as DUT VGS • dv/dt controlled by RG • ISD controlled by pulse period VDD LL I SD 10V VGS ( Driver ) I SD ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop VSD IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width Gate Pulse Period --------------------------D = Gate Pulse Width Gate Pulse Period -------------------------- Rev. B, November 2001©2001 Fairchild Semiconductor Corporation SSW 2N 60B / SSI2N 60B Package Dimensions 10.00 ±0.20 10.00 ±0.20 (8.00) (4.40) 1.27 ±0.10 0.80 ±0.10 0.80 ±0.10 (2XR0.45) 9.90 ±0.20 4.50 ±0.20 0.10 ±0.15 2.40 ±0.20 2. 54 ± 0. 30 15 .3 0 ±0 .3 0 9. 20 ±0 .2 0 4. 90 ±0 .2 0 1. 40 ±0 .2 0 2. 00 ±0 .1 0 (0. 75 ) (1. 75 ) (7. 20 ) 0°~ 3° 1. 20 ±0 .2 0 9. 20 ±0 .2 0 15 .3 0 ±0 .3 0 4. 90 ±0 .2 0 (0. 40 ) 2.54 TYP 2.54 TYP 1.30 +0.10 –0.05 0.50 +0.10 –0.05 D2-PAK Dimensions in Millimeters ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSW 2N 60B / SSI2N 60B Package Dimensions (Continued) 9.90 ±0.20 2.40 ±0.20 4.50 ±0.20 1.27 ±0.10 1.47 ±0.10 (45 °) 0.80 ±0.10 10.00 ±0.20 2.54 TYP2.54 TYP 13 .0 8 ±0 .2 0 9. 20 ±0 .2 0 1. 20 ±0 .2 0 10 .0 8 ±0 .2 0 M AX 13 .4 0 M AX 3 .0 0 (0. 40 ) (1. 46 ) (0. 94 ) 1.30 +0.10 –0.05 0.50 +0.10 –0.05 I2-PAK Dimensions in Millimeters ©2001 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 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