CY68013

CY7C68013 EZ-USB FX2™ USB Microcontroller 1.0 EZ-USB FX2 Features • Single-chip integrated USB 2.0 Transceiver, SIE, and Enhanced 8051 Microprocessor • Software: 8051 code runs from: — Internal RAM, which is downloaded via USB — Internal RAM, which is loaded from EEPROM — External memory device (128 pin package • Four programmable BULK/INTERRUPT/ ISOCHRONOUS endpoints — Buffering options: double, triple and quad • 8- or 16-bit external data interface • GPIF — Allows direct connection to most parallel interface — Programmable waveform descriptors and configu- ration registers to define waveforms — Supports multiple Ready (RDY) inputs and Control (CTL) outputs • Integrated, industry standard enhanced 8051: — Up to 48-MHz clock rate — Four clocks per instruction cycle — Two USARTS — Three counter/timers — Expanded interrupt system — Two data pointers • Supports bus-powered applications by using renumer- ation • 3.3V operation • Smart Serial Interface Engine • Vectored USB interrupts • Separate data buffers for the SETUP and DATA portions of a CONTROL transfer • Integrated I2C-compatible controller, runs at 100 or 400 kHz • 48-MHz, 24-MHz, or 12-MHz 8051 operation • Four integrated FIFOs — Brings glue and FIFOs inside for lower system cost — Automatic conversion to and from 16-bit buses — Master or slave operation — FIFOs can use externally supplied clock or asyn- chronous strobes — Easy interface to ASIC and DSP ICs • Special autovectors for FIFO and GPIF interrupts • Up to 40 general-purpose I/Os • Four package options—128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP • Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP A dd re s s (1 6) x20 PLL /0.5 /1.0 /2.0 8051 Core 12/24/48 MHz, four clocks/cycle I2C Compatible VCC 1.5k D+ D– Ad dr e ss (16 ) / Da ta B u s (8) FX2 GPIF CY Smart USB 1.1/2.0 Engine USB 2.0 XCVR 8.5 kB RAM 4 kB FIFO Integrated full- and high-speed XCVR Additional I/Os (24) ADDR (9) CTL (6) RDY (6) 8/16 Da ta (8) 24-MHz Ext. XTAL Up to 96 MBytes/s burst rate General programmable I/F to ASIC/DSP or bus standards such as ATAPI, EPP, etc. Abundant I/O including two USARTS High-performance micro using standard tools with lower-power options Master connected for full speed Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-08012 Rev. *E Revised February 8, 2005 Enhanced USB core Simplifies 8051 core “Soft Configuration” Easy firmware changes FIFO and endpoint memory (master or slave operation) Figure 1-1. Block Diagram CY7C68013 Cypress’s EZ-USB FX2 is the world’s first USB 2.0 integrated microcontroller. By integrating the USB 2.0 trans- ceiver, SIE, enhanced 8051 microcontroller, and a program- mable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer rates of 56 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low- cost 8051 microcontroller in a package as small as a 56 SSOP. Because it incorporates the USB 2.0 transceiver, the FX2 is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded micro- controller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. 2.0 Applications • DSL modems • ATA interface • Memory card readers • Legacy conversion devices • Cameras • Scanners • Home PNA • Wireless LAN • MP3 players • Networking. The “Reference Designs” section of the cypress website provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit http://www.cypress.com for more information. 3.0 Functional Overview 3.1 USB Signaling Speed FX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000: • Full speed, with a signaling bit rate of 12 Mbps • High speed, with a signaling bit rate of 480 Mbps FX2 does not support the low-speed signaling mode of 1.5 Mbps. 3.2 8051 Microprocessor The 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.8051 Clock Frequency FX2 has an on-chip oscillator circuit that uses an external 24-MHz (±100 ppm) crystal with the following characteristics: • Parallel resonant • Fundamental mode • 500-µW drive level • 20–33 pF (5% tolerance) load capacitors. An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. The CLKOUT pin, which can be tri-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency—48, 24, or 12 MHz. 3.2.1 USARTS FX2 contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multi- plexed with port pins. UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230-KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230-KBaud operation. Note. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively. 3.2.2 Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical FX2 functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard, enhanced 8051 registers. The two SFR rows that end with “0” and “8” contain bit-addres- sable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not imple- mented in FX2. Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using the MOVX instruction). Document #: 38-08012 Rev. *E Page 2 of 48 CY7C68013 3.3 I2C-compatible Bus FX2 supports the I2C-compatible bus as a master only at 100/400 kbps. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even if no I2C-compatible device is connected. 3.4 Buses All packages: 8- or 16-bit “FIFO” bidirectional data bus, multi- plexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus. 3.5 USB Boot Methods During the power-up sequence, internal logic checks the I2C- compatible port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2 enumerates using internally stored descriptors. The default ID values for FX2 are VID/PID/DID (0x04B4, 0x8613, 0xxxyy). Note. The I2C-compatible bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise 3.6 ReNumeration™ Because the FX2’s configuration is soft, one chip can take on the identities of multiple distinct USB devices. When first plugged into USB, the FX2 enumerates automati- cally and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step has occurred. Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1, the firmware will. 3.7 Bus Powered Applications Bus powered applications require the FX2 to enumerate in a unconfigured mode with less then 100 mA. To do this, the FX2 must enumerate in the full speed mode and then, when configured, renumerate in high speed mode. For an example of the benefits and limitations of this renumeration process see the application note titled “Bus Powered Enumeration with FX2”. Table 3-1. Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1 SP EXIF INT2CLR IOE SBUF1 2 DPL0 MPAGE INT4CLR OEA 3 DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7 PCON 8 TCON SCON0 IE IP T2CON EICON EIE EIP 9 TMOD SBUF0 A TL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L B TL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H C TH0 reserved EP68FIFOFLGS TL2 D TH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F reserved AUTOPTRSETUP GPIFSGLDATLNOX Table 3-2. Default ID Values for FX2 Default VID/PID/DID Vendor ID 0x04B4 Cypress Semiconductor Prod ID 0x8613 EZ-USB FX2 Device release 0xXXYY Depends on revision (0x04 for Rev E) Document #: 38-08012 Rev. *E Page 3 of 48 this detection method does not work properly. CY7C68013 3.8 Interrupt System 3.8.1 INT2 Interrupt Request and Enable Registers FX2 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See FX2 TRM for more details. 3.8.2 USB-Interrupt Autovectors The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the FX2 provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a “jump” instruction to the USB Interrupt service routine. The FX2 jump instruction is encoded as shown in Table 3-3. If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the FX2 substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page. Table 3-3. INT2 USB Interrupts USB Interrupt Table for INT2 Priority INT2VEC Value Source Notes 1 00 SUDAV SETUP Data Available 2 04 SOF Start of Frame (or microframe) 3 08 SUTOK Setup Token Received 4 0C SUSPEND USB Suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high-speed operation 7 18 EP0ACK FX2 ACK’d the CONTROL Handshake 8 1C reserved 9 20 EP0-IN EP0-IN ready to be loaded with data 10 24 EP0-OUT EP0-OUT has USB data 11 28 EP1-IN EP1-IN ready to be loaded with data 12 2C EP1-OUT EP1-OUT has USB data 13 30 EP2 IN: buffer available. OUT: buffer has data 14 34 EP4 IN: buffer available. OUT: buffer has data 15 38 EP6 IN: buffer available. OUT: buffer has data 16 3C EP8 IN: buffer available. OUT: buffer has data 17 40 IBN IN-Bulk-NAK (any IN endpoint) 18 44 reserved 19 48 EP0PING EP0 OUT was Pinged and it NAK’d 20 4C EP1PING EP1 OUT was Pinged and it NAK’d 21 50 EP2PING EP2 OUT was Pinged and it NAK’d 22 54 EP4PING EP4 OUT was Pinged and it NAK’d 23 58 EP6PING EP6 OUT was Pinged and it NAK’d 24 5C EP8PING EP8 OUT was Pinged and it NAK’d 25 60 ERRLIMIT Bus errors exceeded the programmed limit 26 64 reserved 27 68 reserved 28 6C reserved 29 70 EP2ISOERR ISO EP2 OUT PID sequence error 30 74 EP4ISOERR ISO EP4 OUT PID sequence error 31 78 EP6ISOERR ISO EP6 OUT PID sequence error 32 7C EP8ISOERR ISO EP8 OUT PID sequence error Document #: 38-08012 Rev. *E Page 4 of 48 CY7C68013 3.8.3 FIFO/GPIF Interrupt (INT4) Just as the USB Interrupt is shared among 27 individual USB- interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 3-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. If Autovectoring is enabled (AV4EN = 1 in the INTSETUP register), the FX2 substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2 pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service routine. 3.9 Reset and Wakeup 3.9.1 Reset Pin An input pin (RESET#) resets the chip. This pin has hysteresis and is active LOW. The internal PLL stabilizes approximately 200 µs after VCC has reached 3.3V. Typically, an external RC network (R = 100k, C = 0.1 µF) is used to provide the RESET# signal. 3.9.2 Wakeup Pins The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscil- lator restarts and after the PLL stabilizes, and the 8051 receives a wakeup interrupt. This applies whether or not FX2 is connected to the USB. The FX2 exits the power down (USB suspend) state using one of the following methods: • USB bus signals resume The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. 3.10 Program/Data RAM 3.10.1 Size The FX2 has eight kbytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to allow the 8051 to access it as both program and data memory. No USB control registers appear in this space. Two memory maps are shown in the following diagrams: Figure 3-1 Internal Code Memory, EA = 0 Figure 3-2 External Code Memory, EA = 1. 3.10.2 Internal Code Memory, EA = 0 This mode implements the internal eight-kbyte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces. Only the internal eight kbytes and scratch pad 0.5 kbytes RAM spaces have the following access: • USB download • USB upload • Setup data pointer • I2C-compatible interface boot load. 3.10.3 External Code Memory, EA = 1 The bottom eight kbytes of program memory is external, and therefore the bottom eight kbytes of internal RAM is accessible only as data memory. Table 3-4. Individual FIFO/GPIF Interrupt Sources Priority INT4VEC Value Source Notes 1 80 EP2PF Endpoint 2 Programmable Flag 2 84 EP4PF Endpoint 4 Programmable Flag 3 88 EP6PF Endpoint 6 Programmable Flag 4 8C EP8PF Endpoint 8 Programmable Flag 5 90 EP2EF Endpoint 2 Empty Flag 6 94 EP4EF Endpoint 4 Empty Flag 7 98 EP6EF Endpoint 6 Empty Flag 8 9C EP8EF Endpoint 8 Empty Flag 9 A0 EP2FF Endpoint 2 Full Flag 10 A4 EP4FF Endpoint 4 Full Flag 11 A8 EP6FF Endpoint 6 Full Flag 12 AC EP8FF Endpoint 8 Full Flag 13 B0 GPIFDONE GPIF Operation Complete 14 B4 GPIFWF GPIF Waveform Document #: 38-08012 Rev. *E Page 5 of 48 • External logic asserts the WAKEUP pin • External logic asserts the PA3/WU2 pin. CY7C68013 Figure 3-1. Internal Code Memory, EA = 0 Inside FX2 Outside FX2 7.5 kbytes US B regs and 4k EP buffers (RD#,WR#) 0.5 kbytes RAM Data (RD#,WR#)* (OK to populate data memory here—RD#/WR# strobes are not active) 48 kbytes External Data Memory (RD#,WR#) (Ok to populate data memory here—RD#/WR# strobes are not active) Eight kbytes RAM Code and Data (PSEN#,RD#,WR#)* 56 kbytes External Code Memory (PSEN#) (OK to populate program memory here— PSEN# strobe is not active) *SUDPTR, USB upload/download, I2C-compatible interface boot access FFFF E200 E1FF E000 1FFF 0000 Data Code Inside FX2 Outside FX2 7.5 kbytes USB regs and 4k EP buffers (RD#,WR#) 0.5 kbytes RAM Data (RD#,WR#)* (OK to populate data memory here—RD#/WR# strobes are not active) 48 kbytes External Data Memory (RD#,WR#) (Ok to populate data memory here—RD#/WR# strobes are not active) Eight kbytes RAM Data (RD#,WR#)* 64 kbytes External Code Memory (PSEN#) *SUDPTR, USB upload/download, I2C-compatible interface boot access FFFF E200 E1FF E000 1FFF 0000 Data Code Document #: 38-08012 Rev. *E Page 6 of 48 Figure 3-2. External Code Memory, EA = 1 CY7C68013 3.11 Register Addresses 3.12 Endpoint RAM 3.12.1 Size • 3 × 64 bytes (Endpoints 0 and 1) • 8 × 512 bytes (Endpoints 2, 4, 6, 8) 3.12.2 Organization • EP0 Bidirectional endpoint zero, 64-byte buffer • EP1IN, EP1OUT 64-byte buffers, bulk or interrupt • EP2,4,6,8 Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and 6 can be either double, triple, or quad buffered. For high- speed endpoint configuration options, see Figure 3-3. 3.12.3 Set-up Data Buffer A separate eight-byte buffer at 0xE6B8-0xE6BF holds the SETUP data from a CONTROL transfer. 3.12.4 Endpoint Configuration (High-speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. To the left of the vertical line, the user may pick different configurations for EP2&4 and EP6&8, since none of the 512-byte buffers are combined between these endpoint groups. An example endpoint config- uration would be: EP2—1024 double buffered; EP6—512 quad buffered. To the right of the vertical line, buffers are shared between EP2–8, and therefore only entire columns may be chosen. FFFF F000 E800 E7FF E7C0 E7BF E780 E77F E740 E73F E700 E6FF E600 E480 E47F E400 E3FF E200 E1FF E000 E5FF EFFF 4 kbytes EP2-EP8 buffers (8 × 512) 2 kbytes RESERVED 64 bytes EP1IN 64 bytes EP1OUT 64 bytes EP0 IN/OUT 64 bytes RESERVED 256 bytes Registers 384 bytes RESERVED 128 bytes GPIF Waveforms 512 bytes RESERVED 512 bytes 8051 xdata RAM Document #: 38-08012 Rev. *E Page 7 of 48 CY7C68013 3.12.5 Default Full-Speed Alternate Settings 3.12.6 Default High-Speed Alternate Settings Table 3-5. Default Full-Speed Alternate Settings[1,2] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 512 512 512 512 512 512 512 512 512 512 EP2 EP2 EP2 EP2 EP2 EP2 EP4 EP6 EP8 EP6 EP6 EP6 EP8 EP8 EP0 IN&OUT EP1 IN EP1 OUT Figure 3-3. Endpoint Configuration Table 3-6. Default High-Speed Alternate Settings[1, 2] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk[3] 64 int 64 int ep1in 0 512 bulk[3] 64