Spartan-6系列芯片清单

7 100 102 8 x 8 mmCPG196 100 100 100 13 x 13 mmCSG225 160120 17 x 17 mmFT(G)256 160 20 x 20 mmTQG144 Package Area Maximum User I/O: SelectIO™ Interface Pins (GTP Transceivers) (7) Part Number Logic Cells (2) CLB Flip-Flops Maximum Distributed RAM (Kbits) Block RAM (18K bits each) Total Block RAM (Kbits) (3) Clock Manager Tiles (CMT) (4) Maximum Single-Ended Pins Maximum Differential Pairs DSP48A1 Slices (5) GTP Low-Power Transceivers Commercial XC6SLX4 600 3,840 4,800 75 12 216 2 120 60 8 Memory Controller Blocks 0 — -2, -3 Configuration Memory (Mbits) 2.7 Slices (1) Logic Resources Memory Resources Clock Resources I/O Resources Embedded Hard IP Resources Speed Grades Configuration PCI Express® Endpoint Block — Industrial -L1, -2 XC6SLX9 1,430 9,152 11,440 90 32 576 2 200 100 16 2 — -2, -3 2.7 — -L1, -2 XC6SLX16 2,278 14,579 XC6SLX25 3,758 24,051 XC6SLX45 6,822 43,661 XC6SLX100 15,822 101,261 XC6SLX150 23,038 147,443 XC6SLX25T 3,758 24,051 XC6SLX75T XC6SLX100T 15,822 101,261 XC6SLX150T 23,038 147,443 Spartan-6 LX FPGAs Optimized for Lowest Cost Logic, DSP, and Memory (1.2 Volt, 1.0 Volt) Optimized for Low Cost Logic, DSP, and Memory with High Speed Serial Connectivity (1.2 Volt) 18,224 136 32 576 2 232 116 32 2 — -2, -3 2.7 — -L1, -2 30,064 229 52 936 2 266 133 38 2 — -2, -3 4.4 — -L1, -2 54,576 401 116 2,088 4 358 179 58 4 — -2, -3 7.7 — -L1, -2 XC6SLX75 11,662 74,637 93,296 692 172 3,096 6 400 200 132 4 — -2, -3 19.6 — -L1, -2 11,662 74,637 93,296 692 172 3,096 6 320 160 132 4 8 -2, -3 19.6 1 -2 126,576 976 268 4,824 6 480 240 180 4 — -2, -3 17.1 — -L1, -2 184,304 1,355 268 4,824 6 570 285 180 4 — -2, -3 28.0 — -L1, -2 30,064 229 52 936 2 250 125 38 2 2 -2, -3 4.4 1 -2 XC6SLX45T 6,822 43,661 54,576 401 116 2,088 4 296 148 58 2 4 -2, -3 7.7 1 -2 126,576 976 268 4,824 6 490 245 180 4 8 -2, -3 17.1 1 -2 184,304 1,355 268 4,824 6 530 265 180 4 8 -2, -3 28.0 1 -2 15 x 15 mmCSG324 200 232 226 19 x 19 mmCSG484 310 310 218 320 330 190 (2) 190 (4) 290 (4) 290 (4) 290 (4) 290 (4) 23 x 23 mmFG(G)484 186 186186 27 x 27 mmFG(G)676 358 400 31 x 31 mmFG(G)900 480 498 570 320 (8) 376 (8) 490 (8) 396 (8) 266 316 TBD 326 338 250 (2) 296 (4) TBD 296 (4) 296 (4) 530 (8) Chip Scale Packages (CSG): Pb-free wire-bond chip scale BGA (0.8 mm ball spacing) TQFP Packages (TQG): Pb-free thin QFP (0.5 mm lead spacing) Chip Scale Packages (CPG): Pb-Free wire-bond BGA (0.5 mm ball spacing) FGA Packages (FTG): Pb and Pb-free wire-bond fine-pitch thin BGA (1.0 mm ball spacing) FGA Packages (FGG): Pb and Pb-free wire-bond fine-pitch BGA (1.0 mm ball spacing) Notes: 1. Each Spartan-6 FPGA CLB contains four LUTs and eight flip-flops. 2. Spartan-6 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6-input LUT architecture. 3. Block RAMS are fundamentally 18Kb in size. Each block can also be used as two independent 9Kb blocks. 4. Each CMT contains two DCMs and one PLL. 5. Each DSP48A1 slice contains an 18x18 multiplier, an adder and an accumulator. 6. Preliminary product information, subject to change. Please contact your Xilinx representative for the latest information. 7. Due to the transceivers in the LXT devices, the LX pmouts are not compatible with the LX device pmouts. Spartan-6 LXT FPGAs XilinX SPArTAn®-6 FAmily FPGAs – 2Q2009 Spartan-6 Family FPGAs Important: Verify all data in this document with the device data sheets found at www.xilinx.com 8 XC3S50A / AN Extended Spartan-3A Family Optimized for Lowest Total Cost XC3S200A / AN XC3S400A / AN XC3S1400A / ANXC3S700A / ANPart Number 50K 200K 400K 700K 1400K 704 1,792 3,584 5,888 11,264 1,408 3,584 7,168 11,776 22,528CLB Flip-Flops 11 28 56 92 176Maximum Distributed RAM (Kbits) 3 16 20 20 32 54 288 360 360 576 – / 627 – / 3,054 – / 2,380 – / 5,779 – / 12,251 2 4 4 8 8 144 / 108 248 / 195 311 372 502 64 / 50 112 / 90 142 165 227 LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL15 Class I, HSTL15 Class III, HSTL18 Class I, HSTL18 Class II, HSTL18 Class III, PCI 3.3V 32/64bit 33MHz, PCI 3.3V 64bit/66MHz, PCI-X 3.3V, SSTL3 Class I, SSTL3 Class II, SSTL2 Class I, SSTL2 Class II, SSTL18 Class I, SSTL18 Class II, Bus LVDS, LVDS25 & 33, LVPECL25 & 33, Mini-LVDS25 & 33, RSDS25 & 33, TMDS33, PPDS25 & 33 3 16 20 20 32 Block RAM Blocks (18k bits each) Total Block RAM (Kbits) User Flash (Kbits) (3) Digital Clock Managers (DCMs) Maximum Single Ended I/Os Maximum Differential I/O Pairs I/O Standards Supported Multipliers/DSP48A Blocks -4, -5 -4, -5 -4, -5 -4, -5 -4, -5Commercial -4 -4 -4 -4 -4Industrial XC3SD1800A 1800K 3400K 16,640 33,280 260 84 1,512 — 8 519 227 84 (4) -4, -5 -4, -4L (5) XC3SD3400A 23,872 47,744 1,584 4,032 8,064 13,248 25,344Logic Cells 37,440 53,712 373 126 2,268 — Yes Yes Yes Yes YesSingle Chip Option No No 8 469 213 126 (4) -4, -5 -4,-4L (5) 0.4Configuration Memory Bits (Kbits) 1.2 1.9 2.7 4.8 8.2 11.7 Slices (2) Logic Resources Memory Resources Non-Volatile Capability Clock Resources I/O Resources Embedded Hard IP Resources Speed Grades Configuration YesDevice DNA Security Yes Yes Yes Yes Yes Yes 108 / 108TQ144 22 x 22 mm 144 / – (7)FT256 17 x 17 mm 195 / 195 195 / – (7) 161 / – (7) 161 / – (7) FG320 19 x 19 mm 248 / – (7) 251 / – (7) FG400 21 x 21 mm 311 / 311 311 / – (7) FG484 23 x 23 mm 372 / 372 375 / – (7) CS484 19 x 19 mm 309 (5) 309 (5) FG676 27 x 27 mm 502 / 502 519 469 System Gates (1) Package (6) Size Maximum User I/Os TQFP Packages (TQ): thin QFP (0.5 mm lead spacing) 68 / – (7)VQ100 16 x 16 mm 68 / – (7) VQFP Packages (VQ): very thin QFP (0.5 mm lead spacing) FGA Packages (FT): wire-bond fine-pitch thin BGA (1.0 mm ball spacing) Chip Scale Packages (CS): wire-bond chip-scale BGA (0.8 mm ball spacing) FGA Packages (FG): wire-bond fine-pitch BGA (1.0 mm ball spacing) 1. System Gates include 20%-30% of CLBs used as RAMs 2. Each slice comprises two 4-input logic function generators (LUTs), two storage elements, wide-function multiplexers, and carry logic 3. Spartan-3AN User Flash is the space left in the on-chip Flash after a portion is used to store configuration bitstream 4. Integrated in the DSP48A slices (Advanced Multiply Accumulate element) 5. The L low-power option is exclusively available in CS(G)484 package and Industrial temperature range 6. All products available Pb-free and RoHS-Compliant, check datasheet for Pb package availability 7. Package not available in non-volatile Spartan-3AN family Notes: XilinX SPArTAn® SerieS FPGAs – 2Q2009 Spartan-3A, 3An & 3A DSP FPGAs Important: Verify all data in this document with the device data sheets found at www.xilinx.com 9 1. System Gates include 20%-30% of CLBs used as RAMs. 2. Each slice comprises two 4-input logic function generators (LUTs), two storage elements, wide-function multiplexers, and carry logic. 3. All products available Pb-free and RoHS-Compliant. 4. Available only in VQG100 package. VQG100 and VQ100 have identical pinouts. Notes: XC3S50 Spartan-3 FPGAs Optimized for High Density and High I/O Designs Spartan-3E FPGAs Logic Optimized XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000Part Number 768 1,920 3,584 7,680 13,312 20,480 50K 200K 400K 1000K 1500K 2000K 1,728 4,320 8,064 17,280 29,952 46,080Logic Cells 1,536 3,840 7,168 15,360 26,624 40,960CLB Flip-Flops 4 12 16 24 32 40 72 216 288 432 576 720 2 4 4 4 4 4 124 173 264 391 487 565 56 76 116 175 221 270 LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, GTL, GTL+, HSTL15 Class I, HSTL15 Class III, HSTL18 Class I, HSTL18 Class II, HSTL18 Class III, PCI 3.3V 32/64bit 33MHz, SSTL2 Class I, SSTL2 Class II, SSTL18 Class I, Bus LVDS, LDT (ULVDS), LVDS_ext, LVDS25 & 33, LVPECL25, RSDS25 4 12 16 24 32 40 63VQ100 16 x 16 mm 63 66 66 664 89CP132 8 x 8 mm 83 92 92 Block RAM Blocks (18k bits each) Total Block RAM (Kbits) Digital Clock Managers (DCMs) Maximum Single Ended I/Os Maximum Differential I/O Pairs I/O Standards Supported Dedicated Multipliers -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5Commercial -4 -4 -4 -4 -4 -4 XC3S4000 27,648 4000K 62,208 55,296 96 1,728 4 633 300 96 -4, -5 -4Industrial XC3S5000 33,280 5000K 74,880 66,560 104 1,872 4 633 300 104 -4, -5 -4 XC3S100E 960 100K 2,160 1,920 4 72 2 108 40 4 -4, -5 -4 XC3S250E 2,448 250K 5,508 4,896 12 216 4 172 68 12 -4, -5 -4 XC3S500E 4,656 500K 1200K 1600K 10,476 9,312 20 360 4 232 92 20 -4, -5 -4 XC3S1200E XC3S1600E 8,672 19,512 17,344 28 504 8 304 124 LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL18 Class I, HSTL18 Class III, PCI 3.3V 32/64bit 33MHz, PCI 3.3V 64bit/66MHz, PCI-X 3.3V, SSTL2 Class I, SSTL18 Class I, Bus LVDS, LVDS25, LVPECL25, Mini-LVDS25, RSDS25 28 -4, -5 -4 14,752 33,192 29,504 12 30 56 120 208 320Maximum Distributed RAM (Kbits) 432 520 15 38 73 136 231 36 648 8 376 156 36 -4, -5 -4 0.4 1.0 1.7 3.2 5.2 7.7 11.3Configuration Memory Bits (Mbits) 13.3 0.6 1.4 2.3 3.8 6.0 Slices (2) Logic Resources Memory Resources Clock Resources I/O Resources Embedded Hard IP Resources Configuration Speed Grades 97TQ144 22 x 22 mm 97 97 108 108 124PQ208 30.6 x 30.6 mm 141 141 158 158 FT256 17 x 17 mm 173 173 173 172 190 190 FG320 19 x 19 mm 221 221 221 232 250 250 FG400 21 x 21 mm 304 304 FG456 23 x 23 mm 264 333 333 333 FG484 23 x 23 mm 376 FG676 27 x 27 mm 391 487 489 489 489 FG900 31 x 31 mm 565 633 633 System Gates (1) Package (3) Area Maximum User I/Os VQFP Packages (VQ): very thin QFP (0.5 mm lead spacing) Chip Scale Packages (CP): wire-bond chip-scale BGA (0.5 mm ball spacing) TQFP Packages (TQ): thin QFP (0.5 mm lead spacing) PQFP Packages (PQ): wire-bond plastic QFP (0.5 mm lead spacing) FGA Packages (FT): wire-bond fine-pitch thin BGA (1.0 mm ball spacing) FGA Packages (FG): wire-bond chip-scale BGA (1.0 mm ball spacing) Spartan-3 & 3e FPGAs XilinX SPArTAn® SerieS FPGAs – 2Q2009 Important: Verify all data in this document with the device data sheets found at www.xilinx.com