EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 1 -
EDA 技术与 VHDL 实验参考程序
实验一 1.用 vhdl语言设计 2选 1多路选择器。
Library ieee;
Use ieee.std_logic_1164.all;
Entity mux21a is
Port(a,b,s: in bit;
Y:out bit);
End mux21a;
Architecture one of mux21a is
Begin
Y<=a when s='0' else b;
End architecture one;
2.将此二选一多路选择器看成是一个元件 mux21a,利用元件例化语句描述图所示双 2选 1
多路选择器。
Library ieee;
Use ieee.std_logic_1164.all;
Entity muxk is
Port (a1,a2,a3,s0,s1:in std_logic;
outy: out std_logic);
End muxk;
Architecture bhv of muxk is
Component mux21a
Port(a,b,s:in std_logic;
Y:out std_logic);
End component;
Signal tmp:std_logic;
Begin
U1:mux21a port map(a=>a2,b=>a3,s=>s0,y=>tmp);
U2:mux21a port map(a=>a1,b=>tmp,s=>s1,y=>outy);
End architecture bhv;
实验二 1.用 vhdl语言设计D边沿触发器。
Library ieee;
Use ieee.std_logic_1164.all;
Entity dff1 is
Port(clk,d:in std_logic;
Q:out std_logic);
End;
Architecture bhv of dff1 is
Signal q1:std_logic;
Begin
Process(clk,q1)
Begin
If clk'event and clk='1' then q1<=d;
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 2 -
End if; end process;
Q<=q1; end bhv;
2.用 vhdl语言设计 D锁存器。
Library ieee;
Use ieee.std_logic_1164.all;
Entity dff2 is
Port(clk,d:in std_logic;
Q:out std_logic);
End;
Architecture bhv of dff2 is
Begin
Process(clk,d) begin
If clk='1' then q<=d; end if;
End process; end bhv;
实验三 1.用 vhdl设计含异步清零和同步时钟使能的十进制加法计数器。
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity cnt10 is
Port(clk,rst,en:in std_logic;
Cq:out std_logic_vector(3 downto0);
Cout:out std_logic);
End cnt10;
Architecture behav of cnt10 is
Begin
Process(clk,rst,en)
Variable cqi:std_logic_vector(3 downto0);
Begin
If rst='1' then cqi:=(others=>'0');
Elsif clk'event and clk='1' then
If en='1' then
If cqi<9 then cqi:=cqi+1;
Else cqi:=(others=>'0'); end if;
End if; end if;
If cqi=9 then cout<='1';
Else cout<='0'; end if;
Cq<=cqi;
End process; end behav;
2.用 vhdl设计含异步清零和同步时钟使能的十进制加减可控计数器。
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity dcnt10 is
Port(clk,rst,en,s:in std_logic;
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 3 -
Cq:out std_logic_vector(3 downto0);
Cout:out std_logic);
End dcnt10;
Architecture behav of dcnt10 is
Begin
Process(clk,rst,en,s)
Variable cqi:std_logic_vector(3 downto0);
Begin
If rst='1' then cqi:=(others=>'0');
Elsif clk'event and clk='1' then
If en='1' then
If s='1' then
If cqi<9 then cqi:=cqi+1;
Else cqi:=(others=>'0'); end if;
Elsif s='0' then
If cqi>0 then cqi:=cqi-1;
Else cqi:="1001";end if;
End if; end if; end if;
If cqi=9 and s='1' then cout<='1';
Elsif cqi=0 and s='0' then cout<='1';
Else cout<='0'; end if;
Cq<=cqi;
End process; end behav;
实验四 1.用 vhdl语言设计七段数码显示译码器,实现 16进制数的译码显示。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY DECL7S IS
PORT (A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
END ;
ARCHITECTURE oneOF DECL7S IS
BEGIN
PROCESS( A )
BEGIN
CASE A IS
WHEN "0000" => LED7S <= "0111111" ;
WHEN "0001" => LED7S <= "0000110" ;
WHEN "0010" => LED7S <= "1011011" ;
WHEN "0011" => LED7S <= "1001111" ;
WHEN "0100" => LED7S <= "1100110" ;
WHEN "0101" => LED7S <= "1101101" ;
WHEN "0110" => LED7S <= "1111101" ;
WHEN "0111" => LED7S <= "0000111" ;
WHEN "1000" => LED7S <= "1111111" ;
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 4 -
WHEN "1001" => LED7S <= "1101111" ;
WHEN "1010" => LED7S <= "1110111" ;
WHEN "1011" => LED7S <= "1111100" ;
WHEN "1100" => LED7S <= "0111001" ;
WHEN "1101" => LED7S <= "1011110" ;
WHEN "1110" => LED7S <= "1111001" ;
WHEN "1111" => LED7S <= "1110001" ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END ;
2.用 vhdl语言描述图所示计数、译码显示电路。
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity cnt4b_decl7s is
Port( clock0.rst0,ena0: in std_logic;
Cout0:out std_logic;
Led:out std_logic_vector(6 downto 0));
End;
Architecture one of cnt4b_decl7s is
Component cnt4b
Port(clk,rst,en:in std_logic;
Cq:out std_logic_vector(3 downto0);
Cout:out std_logic);
End component;
Component decl7s
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
End component;
Signal tmp:std_logic_vector(3 downto 0);
Begin
U1:cnt4b portmap(clk=>clock0,rst=>rst0,en=>ena0,cout=>cout0,cq=>tmp);
U2:decl7s port map(a=>tmp,led7s=>led);
End architecture one;
实验五 1.用 vhdl语言设计 8位数码扫描显示电路,显示输出数据直接在程序中给出。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity show1 is
port(clk:in std_logic;
led7s:out std_logic_vector(6 downto0);
s1_8:out std_logic_vector(7 downto0));
end entity show1;
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 5 -
architecture one of show1 is
signal a:std_logic_vector(2 downto0):="000";
begin
p_js:process(clk)
begin
if clk'event and clk='1' then
if a<7 then a<=a+1;
else a<="000";
end if;
end if;
end process p_js;
p_xt:process(a)
begin
case a is
when "000" => s1_8<="00000001";
when "001" => s1_8<="00000010";
when "010" => s1_8<="00000100";
when "011" => s1_8<="00001000";
when "100" => s1_8<="00010000";
when "101" => s1_8<="00100000";
when "110" => s1_8<="01000000";
when "111" => s1_8<="10000000";
whenothers => null;
end case;
end process p_xt;
p_ym:process(a)
begin
case a is
when "000" => led7s<="0000110";
when "001" => led7s<="1001111";
when "010" => led7s<="1101101";
when "011" => led7s<="0000111";
when "100" => led7s<="1101111";
when "101" => led7s<="1111100";
when "110" => led7s<="1011110";
when "111" => led7s<="1110001";
whenothers =>null;
end case;
end process p_ym;
end architecture one;
2.修改上述程序,增加 8个 4位锁存器作为输出显示数据缓冲器,由外部输入 8个待显示的
十六进制数。
library ieee;
use ieee.std_logic_1164.all;
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 6 -
use ieee.std_logic_unsigned.all;
entity show2 is
port(clk,load,en:in std_logic;
din:in std_logic_vector(3 downto 0);
led7s:out std_logic_vector(6 downto0);
bits:out std_logic_vector(7 downto 0));
end entity show2;
architecture behav of show2 is
signal cnt:integer range 0 to 7;
signal tmp,d1,d2,d3,d4,d5,d6,d7,d8:std_logic_vector(3 downto 0);
begin
p_zz:process(load)
variable cn:std_logic_vector(2 downto 0);
begin
if load='1' and load'event then
case cn is
when "000" => d1<=din;
when "001" => d2<=din;
when "010" => d3<=din;
when "011" => d4<=din;
when "100" => d5<=din;
when "101" => d6<=din;
when "110" => d7<=din;
when "111" => d8<=din;
whenothers=>null;
end case;
cn:=cn+1;
end if;
end process p_zz;
p_js:process(clk)
begin
if clk'event and clk='1' then
if cnt<7 then cnt<=cnt+1;
else cnt<=0;
end if;
end if;
end process p_js;
p_xt:process(cnt,d1,d2,d3,d4,d5,d6,d7,d8,en)
begin
case cnt is
when0=>if en='1' then tmp<=d1;bits<="00000001"; else bits<="00000000"; end if;
when1=>if en='1' then tmp<=d2;bits<="00000010"; else bits<="00000000"; end if;
when2=>if en='1' then tmp<=d3;bits<="00000100"; else bits<="00000000"; end if;
when3=>if en='1' then tmp<=d4;bits<="00001000"; else bits<="00000000"; end if;
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 7 -
when4=>if en='1' then tmp<=d5;bits<="00010000"; else bits<="00000000"; end if;
when5=>if en='1' then tmp<=d6;bits<="00100000"; else bits<="00000000"; end if;
when6=>if en='1' then tmp<=d7;bits<="01000000"; else bits<="00000000"; end if;
when7=>if en='1' then tmp<=d8;bits<="10000000"; else bits<="00000000"; end if;
whenothers=>null;
end case;
end process p_xt;
p_ym:process(tmp)
begin
case tmp is
WHEN "0000" => LED7S <= "0111111" ;
WHEN "0001" => LED7S <= "0000110" ;
WHEN "0010" => LED7S <= "1011011" ;
WHEN "0011" => LED7S <= "1001111" ;
WHEN "0100" => LED7S <= "1100110" ;
WHEN "0101" => LED7S <= "1101101" ;
WHEN "0110" => LED7S <= "1111101" ;
WHEN "0111" => LED7S <= "0000111" ;
WHEN "1000" => LED7S <= "1111111" ;
WHEN "1001" => LED7S <= "1101111" ;
WHEN "1010" => LED7S <= "1110111" ;
WHEN "1011" => LED7S <= "1111100" ;
WHEN "1100" => LED7S <= "0111001" ;
WHEN "1101" => LED7S <= "1011110" ;
WHEN "1110" => LED7S <= "1111001" ;
WHEN "1111" => LED7S <= "1110001" ;
WHEN OTHERS => NULL ;
end case;
end process p_ym;
end architecture behav;
实验六 1.设计一个 8位数控分频器。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dvf is
port(clk:in std_logic;
d:in std_logic_vector(7 downto 0);
fout:out std_logic);
end entity dvf;
architecture one of dvf is
signal full:std_logic;
begin
p_reg:process(clk)
variable cnt8:std_logic_vector(7 downto 0);
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 8 -
begin
if clk'event and clk='1' then
if cnt8="11111111" then
cnt8:=d; full<='1';
else cnt8:=cnt8+1; full<='0';
end if;
end if;
end process p_reg;
p_div:process(full)
variable cnt2:std_logic;
begin
if full'event and full='1' then
cnt2:=not cnt2;
if cnt2='1' then fout<='1';
else fout<='0';
end if; end if;
end process p_div;
end architecture one;
2.将 8位数控分频器扩展为 16位数控分频器。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dvf16 is
port(clk:in std_logic;
d:in std_logic_vector(15 downto 0);
fout:out std_logic);
end entity dvf16;
architecture one of dvf16 is
signal full:std_logic;
begin
p_reg:process(clk)
variable cnt16:std_logic_vector(15 downto 0);
begin
if clk'event and clk='1' then
if cnt16="1111111111111111" then
Cnt16:=d; full<='1';
else cnt16:=cnt16+1; full<='0';
end if;
end if;
end process p_reg;
p_div:process(full)
variable cnt2:std_logic;
begin
if full'event and full='1' then
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 9 -
cnt2:=not cnt2;
if cnt2='1' then fout<='1';
else fout<='0';
end if; end if;
end process p_div;
end architecture one;
实验七 1.设计一个 8位序列信号检测器。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SCHK IS
PORT(DIN,CLK,CLR:IN STD_LOGIC;
AB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END schk;
ARCHITECTURE behav OF SCHK IS
SIGNAL Q: INTEGER RANGE 0 TO 8;
SIGNAL D: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
D<="11100101";
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN Q<=0;
ELSIF CLK'EVENTAND CLK='1' THEN
CASE Q IS
WHEN 0=> IF DIN=D(7)THEN Q<=1;ELSE Q<=0;END IF;
WHEN 1=> IF DIN=D(6)THEN Q<=2;ELSE Q<=0;END IF;
WHEN 2=> IF DIN=D(5)THEN Q<=3;ELSE Q<=0;END IF;
WHEN 3=> IF DIN=D(4)THEN Q<=4;ELSE Q<=0;END IF;
WHEN 4=> IF DIN=D(3)THEN Q<=5;ELSE Q<=0;END IF;
WHEN 5=> IF DIN=D(2)THEN Q<=6;ELSE Q<=0;END IF;
WHEN 6=> IF DIN=D(1)THEN Q<=7;ELSE Q<=0;END IF;
WHEN 7=> IF DIN=D(0)THEN Q<=8;ELSE Q<=0;END IF;
WHEN OTHERS=>Q<=0;
END CASE;
END IF;
END PROCESS;
PROCESS(Q)
BEGIN
IF Q=8 THEN AB<="1010";
ELSE AB<="1011";
END IF;
END PROCESS;
END behav;
2.将 8位待测预置数作为外部输入信号,即可以随时改变序列检测器中的比较数据。写出此
程序的符号化单进程有限状态机。
EDA技术与 VHDL实验程序 CIE@XTU 06通信 Peng Cheng pc830@qq.com 2008-11 - 10 -
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SCHK IS
PORT(DIN,CLK,CLR:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
AB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END schk;
ARCHITECTURE behav OF SCHK IS
SIGNAL Q: INTEGER RANGE 0 TO 8;
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN Q<=0;
ELSIF CLK'EVENTAND CLK='1' THEN
CASE Q IS
WHEN 0=> IF DIN=D(7)THEN Q<=1;ELSE Q<=0;END IF;
WHEN 1=> IF DIN=D(6)THEN Q<=2;ELSE Q<=0;END IF;
WHEN 2=> IF DIN=D(5)THEN Q<=3;ELSE Q<=0;END IF;
WHEN 3=> IF DIN=D(4)THEN Q<=4;ELSE Q<=0;END IF;
WHEN 4=> IF DIN=D(3)THEN Q<=5;ELSE Q<=0;END IF;
WHEN 5=> IF DIN=D(2)THEN Q<=6;ELSE Q<=0;END IF;
WHEN 6=> IF DIN=D(1)THEN Q<=7;ELSE Q<=0;END IF;
WHEN 7=> IF DIN=D(0)THEN Q<=8;ELSE Q<=0;END IF;
WHEN OTHERS=>Q<=0;
END CASE;
END IF;
IF Q=8 THEN AB<="1010";
ELSE AB<="1011";
END IF;
END PROCESS;
END behav;
实验一
实验二
实验三
实验四
实验五
实验六
实验七
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