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首页 如何综合安全的状态机

如何综合安全的状态机.pdf

如何综合安全的状态机

azxuxiaowei
2012-03-14 0人阅读 举报 0 0 0 暂无简介

简介:本文档为《如何综合安全的状态机pdf》,可适用于IT/计算机领域

DesigningSafeVerilogStateMachinesCopyright,SynplicityIncDesigningSafeVerilogStateMachineswithSynplifyIntroductionOneofthestrengthsofSynplifyistheFiniteStateMachinecompilerThisisapowerfulfeaturethatnotonlyhastheabilitytoautomaticallydetectstatemachinesinthesourcecode,andimplementthemwitheithersequential,gray,oronehotencodingButalsoperformareachabilityanalysistodetermineallthestatesthatcouldpossiblybereached,andoptimizeawayallstatesandtransitionlogicthatcannotbereachedThus,producingahighlyoptimalfinalimplementationofthestatemachineInthevastmajorityofsituationsthisbehaviorisdesirableThereareoccasions,however,whentheremovalofunreachablestatesisnotacceptableOneclearexampleiswhenthefinalcircuitwillbesubjectedtoaharshoperatingenvironment,suchasspaceapplicationswheretheremaybehighlevelsofradiationInthepresenceofhighlevelsofradiation,storageelements(flipflops)havebeenknowntochangestateduetoalphaparticlehitsIfasinglebitofastateregisterwheretosuddenlychangevalue,theresultingstatemaybeinvalidIftheinvalidstatesandtransitionlogichadbeenremoved,thecircuitmaynevergetbacktoavalidstateBydefaultSynplifywillcreatestatemachinesthatareoptimizedforspeedandareaThisapplicationnotewilluseanexamplestatemachinedesigntoshowthedefaultsmallfastimplementationItwillalsodemonstratehowtotradeoffsomeofthatspeedareatoproducehighlyreliablestatemachinesusingSynplifyExample:AssumethatthetransitiondiagraminfigureistobeimplementedasaonehotFSM:Fighp注释但是也有情况是移去用不到的状态是有害的本页已使用福昕阅读器进行编辑。福昕软件(C)版权所有仅供试用。ഀDesigningSafeVerilogStateMachinesCopyright,SynplicityIncOnepossibleRTLimplementationwouldbe:moduleFSM(clk,in,rst,out)inputclk,rst,inoutput:out`defines'b`defines'b`defines'b`defines'b`defines'breg:outreg:state*synthesissynencoding="onehot"*reg:nextstatealways(posedgeclkorposedgerst)if(rst)state<=`selsestate<=nextstatealways(stateorin)case(state)`s:beginout<='bif(in)nextstate<=`selsenextstate<=`send`s:beginout<='bif(in)nextstate<=`selsenextstate<=`send`s:beginout<='bif(in)nextstate<=`selsenextstate<=`send`s:beginout<='bif(in)nextstate<=`selsenextstate<=`send`s:beginout<='bif(in)nextstate<=`selsenextstate<=`senddefault:beginout<='bnextstate<=`sDesigningSafeVerilogStateMachinesCopyright,SynplicityIncendendcaseendmoduleNote:TheÒsynencodingÓattributeisusedtospecifythatthisstatemachineshouldbeencodedasonehotTherearedefinedstates(S,S,S,S,andS),allofwhicharereachableSincetheencodingstyleisonehot,thereareundefined(andunreachable)statesthatarecoveredbytheÒdefaultÓbranchofthecasestatementThestateregisterresetstostateSTheÒdefaultÓcasespecifiesatransitiontostateSKeepinmindthatthiscircuitwillneverreachtheÒdefaultÓbranchwithoutsomeexternalinfluencesuchasanalphaparticlehitoraphysicaldefectinthetargetpartRegardingcodingstyle,parameterstatementscouldhavebeenusedinsteadofdefinestatementsThestatevaluesdefinedinthesourcecodedescribeasequentialencoding,however,thesynencodingattributedirectstheFSMcompilertoimplementthisdesignasaonehotstatemachineThefinalcircuitwillhavethestateencodings:S=,S=,S=,S=,S=Thematerialcoveredinthisapplicationnoteappliestoallsupportedencodingstyles,onehot,sequential,andgrayDefaultImplementation:IfSynplifyisusedtosynthesizethisdesignasis,theresultisanoptimizedstatemachinewiththetransitionlogicforunreachablestatesremovedThefinalimplementationisbasicallyashiftregisterWherethestateregisterresetstothestate(S),andtheoutputofstatebitistheinputtostatebit,theoutputofstatebitistheinputtostatebit,andsoonThisisshowninfigureusingtheTechnologyViewinHDLAnalystDesigningSafeVerilogStateMachinesCopyright,SynplicityIncThisisaveryoptimalresultforbothtimingandareaInanormaloperatingenvironmentthiscircuitwillfunctionperfectlySuppose,however,thatthiscircuitistobeplacedinahostileoperatingenvironmentwherearegistercouldspontaneouslychangevalueduetoanalphaparticlehit,orsomeotherreasonWhatwouldhappenifthisstatemachineendedupinthestateThenexttransitionwouldshiftallthestatebitsresultinginthestateTheresultbeingthatthisFSMwouldeffectivelybestuckinthestateÒSafeÓImplementation:Tohandlethistypeofproblem,theFSMcompilerinSynplifyhasaspecialencodingdirective,ÒsafeÓ,thatwilladdlogicsuchthatifthestatemachineshouldeverreachaninvalidstate,itwillbeforcedtotheresetstateThisbehaviorhastheadvantageofavoidinganypossibleÒhangÓconditions,wherethestatemachineisunabletogetbacktoavalidstate,whilehavingminimalimpactonthetimingofthecircuitToenablethisfeaturesimplychangethevalueofthesynencodingattributefrom:reg:state*synthesissynencoding="onehot"*to:reg:state*synthesissynencoding="safe,onehot"*Note:ThesynencodingattributecanalsobeappliedintheSCOPEgraphicalconstrainteditorordirectlyintheconstraint(sdc)fileUsingthefollowingsyntax:defineattribute{state*}synencoding{safe,onehot}Synthesizingthisdesignwillresultinacircuitthathasthestatetransitionlogicimplementedexactlyasshowninfigureabove,withtheadditionofthecircuitryinfigureaddedtotheresetlogicDesigningSafeVerilogStateMachinesCopyright,SynplicityIncIfaninvalidstateisdetected,thestateillegalpiperegisterissetonthenextrisingclockedgeOnthefallingedgeoftheclock,thestateillegalpiperegisterissetInstanceGORstheoriginalresetsignalÒrstÓwiththenewrecoverylogicTheoutputofinstanceGdrivestheclearpresetpinsofthestatebits,forcingthecircuittothe(valid)resetstateOncethisvalidstateisreached,thenextrisingedgeoftheclockwillclearthestateillegalpiperegister,thenextfallingedgeoftheclockwillclearthestateillegalpiperegisterandnormaloperationwillbeginNotethattheresultofthisrecoverylogic,theoutputofstateillegalpipe,isregisteredonthefallingedgeoftheclocktopreventanyharzardousconditionsthatcouldresultfromremovingtheresetsignaltooclosetotheactiveclockedgeofthestateregistersTherecoverylogicdiscussedaboveisgeneratedfortheexamplecircuitwhichhappenstohaveanasynchronousresetIfthecircuithadasynchronousresetinstead,thelogicimplementedwouldbeslightlydifferentSupposetheregisterdefinitionwaschangedfrom:always(posedgeclkorposedgerst)if(rst)state<=`selsestate<=nextstateto:always(posedgeclk)if(rst)state<=`selsestate<=nextstateForthissynchronousresetimplementation,thecircuitryinfigurewouldbeaddedtotheresetlogic:DesigningSafeVerilogStateMachinesCopyright,SynplicityIncTherecoverylogicdiscussedaboveisgeneratedfortheexamplecircuitwhichhappenstohaveanasynchronousresetIfthecircuithadasynchronousresetinstead,thelogicimplementedwouldbeslightlydifferentSupposetheregisterdefinitionwaschangedfrom:always(posedgeclkorposedgerst)if(rst)state<=`selsestate<=nextstateto:always(posedgeclk)if(rst)state<=`selsestate<=nextstateIfaninvalidstateisdetected,thestateillegalpiperegisterissetonthenextrisingclockedgeInstanceGORstheoriginalresetsignalÒrstÓwiththenewrecoverylogicOnthenextpositiveclockedge,thestateregisterwillswitchtothe(valid)resetstateOncethisvalidstateisreached,thenextrisingedgeoftheclockwillclearthestateillegalpiperegister,andnormaloperationwillbeginInboththeasynchronousandsynchronousresetcase,ifthecircuitshouldeverreachaninvalidstate(stateforexample),therecoverylogicwillbeactivatedresetingthestateregisterbacktothestate(S)OncetheFSMisbacktothevalidstateof(S),normaloperationofthestatemachinecanresumeNoticethatuponenteringaninvalidstatethiscircuitwillrecovertothestate(S)notthestate(S)asdescribedintheÒdefaultÓbranchofthecasestatementThisimplementationeliminatesthepossibilityofthestatemachinegettingÒstuckÓinaninvalidstateandnotreturningtoavalidstateThisproblemishandledwithveryminimalimpactonthetimingofthecircuitHowever,aspointedoutabove,thetransitionoutofaninvalidstateisnotimplementedexactlyasdescribedintheÒdefaultÓbranchofthesourcecodeThisdeviationfromthedefinedÒdefaultÓbranchbehavioronlyoccursforDesigningSafeVerilogStateMachinesCopyright,SynplicityIncinvalidstatesIftheÒdefaultÓcasecontainedanyvalidstatetransitionstheywouldbeimplementedasdescribedinthesourcecodeÒExactÓImplementation:ItispossibletogetanimplementationofthecircuitthatfullyimplementstheÒdefaultÓbranchifitisnecessarytodosoThisrequiresdisablingthereachabilityanalysisofthestatemachine,whichisdonebyturningofftheFSMcompiler,andexplicitlydefiningthedesiredstateencodingsThiscanhaveasignificantaffectontheareaandtimingofthecircuitTogetafullimplementationoftheÒdefaultÓcasechangethestateregisterdescriptionfrom:`defines'b`defines'b`defines'b`defines'b`defines'breg:outreg:state*synthesissynencoding="onehot"*reg:nextstateto:`defines'b`defines'b`defines'b`defines'b`defines'breg:state*synthesissynpreserve=*reg:nextstateNote:Thestateregisterisdefinedasbitsinsteadofbits,andthestateencodingshavebeenexplicitlydefinedasonehotThisisdoneinordertomakecomparisonstothecircuitsintheprevioussectionswhichwereimplementedasonehotItisnotarequirementfortheencodingtobechangedtoonehotinordertogetafullimplementationoftheÒdefaultÓcase,anyencodingwillworkfineAsynpreserveattributeisappliedtothestateregistertodisabletheFSMcompilerThesynencodingattributeisnolongerneededbecausetheFSMcompilerisdisabledTherestofthecoderemainsunchangedFigureusestheRTLviewofHDLAnalysttoshowthattheÒdefaultÓcaseisfullyimplementedDesigningSafeVerilogStateMachinesCopyright,SynplicityIncTheinstancesnextstate,nextstate,nextstate,nextstate,andnextstatedecodethecurrentstate(S,S,S,S,Srespectively)Theinstancesun,un,andunimplementthenextstatelogicforstateS(bitofthestateregister)Thefunctionis((~InS)|(InS))Thefunctionforstatebits,,andareverysimilarBit,however,hasanextratermgeneratedbyinstanceunThistermchecksiftheFSMiscurrentlyinavalidstateIfso,thefunction((~InS)|(InS))isusedIfnot,bitisforcedhighmakingthenextstate(S)asdescribedintheÒdefaultÓbranchoftheoriginalsourcecodeSummary:Tosummarize,SynplifycontainsapowerfulFSMcompilerwhichbydefaultwillproducestatemachineimplementationsthatarehighlyoptimialinregardstoareaandtimingIfrecoveryfromaninvalidstateisimportanttheÒsafeÓfeaturecanbeusedtoforcethestatemachinetotheresetstateifaninvalidstateisreached,withminimalimpactontimingandareaofthecircuitThisimplementationoftransitioningoutofaninvalidstatemaydifferfromwhatisexplicitlydescribedinthesourcecodeFormostdesignsthisisanacceptabledeviation,sincethesetransitionsarebydefinitionnotvalidIftheseinvalidstatetransitionsmustbehandledexactlyasdescribedbythesourcecode,theFSMcompilercanbedisabledHowever,thismayresultinasubstantialimpactontimingandareaToquantifytheimpactontimingandarea,thethreeimplementationsofthisstatemachineweresynthesizedtargetinganAlteraFlexkpartandaXilinxVirtexpartTheestimatedtimingandarearesultsreportedbySynplifyaredisplayedintablebelowTargetAlteraFlexkÐEPFKAXilinxVirtexÐXCVnsLCsRegsnsLUTsRegsDefaultSafeFullDefaultTab

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