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ADE7878英文手册.pdf

ADE7878英文手册.pdf

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简介:本文档为《ADE7878英文手册pdf》,可适用于电子通讯领域,主题内容包含PolyphaseMultifunctionEnergyMeteringICADEADEADEADERevEInformationfurnished符等。

Polyphase Multifunction Energy Metering IC ADE7854/ADE7858/ADE7868/ADE7878 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2010–2011 Analog Devices, Inc. All rights reserved. FEATURES Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards Compatible with 3-phase, 3- or 4-wire (delta or wye), and other 3-phase services Supplies total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858 only), and apparent energy, and fundamental active/reactive energy (ADE7878 only) on each phase and on the overall system Less than 0.1% error in active and reactive energy over a dynamic range of 1000 to 1 at TA = 25C Less than 0.2% error in active and reactive energy over a dynamic range of 3000 to 1 at TA = 25C Supports current transformer and di/dt current sensors Dedicated ADC channel for neutral current input (ADE7868 and ADE7878 only) Less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at TA = 25C Supplies sampled waveform data on all three phases and on neutral current Selectable no load threshold levels for total and fundamental active and reactive powers, as well as for apparent powers Low power battery mode monitors phase currents for antitampering detection (ADE7868 and ADE7878 only) Battery supply input for missing neutral operation Phase angle measurements in both current and voltage channels with a typical 0.3 error Wide-supply voltage operation: 2.4 V to 3.7 V Reference: 1.2 V (drift 10 ppm/C typical) with external overdrive capability Single 3.3 V supply 40-lead lead frame chip scale package (LFCSP), Pb-free Operating temperature: 40C to +85C Flexible I2C, SPI, and HSDC serial interfaces APPLICATIONS Energy metering systems GENERAL DESCRIPTION The ADE7854/ADE7858/ADE7868/ADE7878 are high accuracy, 3-phase electrical energy measurement ICs with serial interfaces and three flexible pulse outputs. The ADE78xx devices incorporate second-order sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), a digital integrator, reference circuitry, and all of the signal processing required to perform total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858), and apparent energy measurement and rms calcu- lations, as well as fundamental-only active and reactive energy measurement (ADE7878) and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The DSP program is stored in the internal ROM memory. The ADE7854/ADE7858/ADE7868/ADE7878 are suitable for measuring active, reactive, and apparent energy in various 3-phase configurations, such as wye or delta services, with both three and four wires. The ADE78xx devices provide system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2, and CF3 logic outputs provide a wide choice of power information: total active, reactive, and apparent powers, or the sum of the current rms values, and fundamental active and reactive powers. The ADE7854/ADE7858/ADE7868/ADE7878 contain wave- form sample registers that allow access to all ADC outputs. The devices also incorporate power quality measurements, such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement, and angles between phase voltages and currents. Two serial interfaces, SPI and I2C, can be used to communicate with the ADE78xx. A dedicated high speed interface, the high speed data capture (HSDC) port, can be used in conjunction with I2C to provide access to the ADC outputs and real-time power information. The ADE7854/ADE7858/ADE7868/ADE7878 also have two interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled interrupt event has occurred. For the ADE7868/ADE7878, three specially designed low power modes ensure the continuity of energy accumulation when the ADE7868/ADE7878 is in a tam- pering situation. See for a quick reference chart listing each part and its functions. The ADE78xx are available in the 40-lead LFCSP, Pb-free package. Table 1 Table 1. Part Comparison Part No. WATT VAR IRMS, VRMS, and VA di/dt Fundamental WATT and VAR Tamper Detect and Low Power Modes ADE7878 Yes Yes Yes Yes Yes Yes ADE7868 Yes Yes Yes Yes No Yes ADE7858 Yes Yes Yes Yes No No ADE7854 Yes No Yes Yes No No ADE7854/ADE7858/ADE7868/ADE7878 Rev. E | Page 2 of 96 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Revision History ............................................................................... 3  Functional Block Diagrams............................................................. 4  Specifications..................................................................................... 8  Timing Characteristics .............................................................. 11  Absolute Maximum Ratings.......................................................... 14  Thermal Resistance .................................................................... 14  ESD Caution................................................................................ 14  Pin Configuration and Function Descriptions........................... 15  Typical Performance Characteristics ........................................... 17  Test Circuit ...................................................................................... 19  Terminology .................................................................................... 20  Power Management........................................................................ 21  PSM0—Normal Power Mode (All Parts) ................................ 21  PSM1—Reduced Power Mode (ADE7868, ADE7878 Only) 21  PSM2—Low Power Mode (ADE7868, ADE7878 Only) ....... 21  PSM3—Sleep Mode (All Parts) ................................................ 22  Power-Up Procedure.................................................................. 24  Hardware Reset........................................................................... 25  Software Reset Functionality .................................................... 25  Theory of Operation ...................................................................... 26  Analog Inputs.............................................................................. 26  Analog-to-Digital Conversion.................................................. 26  Current Channel ADC............................................................... 27  di/dt Current Sensor and Digital Integrator .............................. 29  Voltage Channel ADC ............................................................... 30  Changing Phase Voltage Datapath........................................... 31  Power Quality Measurements................................................... 32  Phase Compensation ................................................................. 37  Reference Circuit........................................................................ 39  Digital Signal Processor............................................................. 39  Root Mean Square Measurement............................................. 40  Active Power Calculation.......................................................... 44  Reactive Power Calculation—ADE7858, ADE7868, ADE7878 Only.............................................................................................. 49  Apparent Power Calculation..................................................... 54  Waveform Sampling Mode ....................................................... 57  Energy-to-Frequency Conversion............................................ 57  No Load Condition .................................................................... 61  Checksum Register..................................................................... 63  Interrupts..................................................................................... 64  Serial Interfaces .......................................................................... 65  ADE7878 Evaluation Board...................................................... 72  Die Version.................................................................................. 72  Silicon Anomaly ............................................................................. 73  ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues ............................................................................................ 73  Functionality Issues.................................................................... 73  Section 1. ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues.................................................................... 74  Registers List ................................................................................... 75  Outline Dimensions ....................................................................... 93  Ordering Guide .......................................................................... 93  ADE7854/ADE7858/ADE7868/ADE7878 Rev. E | Page 3 of 96 REVISION HISTORY 4/11—Rev. D to Rev. E Changes to Input Clock FrequencyParameter, Table 2 ..............10 Changes to Current RMS Offset Compensation Section ..........42 Changes to Voltage RMS Offset Compensation Section ...........44 Changes to Note 2, Table 30...........................................................77 Changes to Address 0xE707, Table 33 ..........................................80 Changes to Table 45 ........................................................................87 Changes to Table 46 ........................................................................88 Changes to Bit Location 7:3, Default Value, Table 54.................92 2/11—Rev. C to Rev. D Changes to Figure 1...........................................................................4 Changes to Figure 2...........................................................................5 Changes to Figure 3...........................................................................6 Changes to Figure 4...........................................................................7 Changes to Table 2 ............................................................................8 Changed SCLK Edge to HSCLK Edge, Table 5 ...........................13 Change to Current Channel HPF Section ...................................28 Change to di/dt Current Sensor and Digital Integrator Section ..............................................................................................30 Changes to Digital Signal Processor Section ...............................39 Changes to Figure 59 ......................................................................44 Changes to Figure 62 ......................................................................47 Changes to Figure 65 ......................................................................49 Changes to Figure 66 ......................................................................52 Changes to Line Cycle Reactive Energy Accumulation Mode Section and to Figure 67.................................................................53 No Load Detection Based On Total Active, Reactive Powers Section ..............................................................................................61 Change to Equation 50 ...................................................................63 Changes to the HSDC Interface Section ......................................70 Changes to Figure 87 and Figure 88 .............................................71 Changes to Figure 89 ......................................................................72 Changes to Table 30 ........................................................................77 11/10—Rev. B to Rev. C Change to Signal-to-Noise-and-Distortion Ratio, SINAD Parameter, Table 1 .............................................................................9 Changes to Figure 18 ......................................................................18 Changes to Figure 22 ......................................................................19 Changes to Silicon Anomaly Section............................................72 Added Table 28 to Silicon Anomaly Section, Renumbered Tables Sequentially ..........................................................................73 8/10—Rev. A to Rev. B Changes to Figure 1 ..........................................................................4 Changes to Figure 2 ..........................................................................5 Changes to Figure 3 ..........................................................................6 Changes to Figure 4 ..........................................................................7 Change to Table 8............................................................................16 Changes to Power-Up Procedure Section....................................23 Changes to Equation 6 and Equation 7........................................33 Changes to Equation 17 .................................................................43 Changes to Active Power Offset Calibration Section.................45 Changes to Figure 63 ......................................................................46 Changes to Reactive Power Offset Calibration Section .............49 Changes to Figure 82 ......................................................................65 Added Silicon Anomaly Section, Renumbered Tables Sequentially......................................................................................71 3/10—Rev. 0 to Rev. A Added ADE7854, ADE7858, and ADE7878 .................. Universal Reorganized Layout ........................................................... Universal Added Table 1, Renumbered Sequentially.....................................1 Added Figure 1, Renumbered Sequentially ...................................3 Added Figure 2 ..................................................................................4 Added Figure 3 ..................................................................................5 Changes to Specifications Section ..................................................7 Changes to Figure 9 ........................................................................14 Changes to Table 8 ..........................................................................14 Changes to Typical Performance Characteristics Section .........16 Changes to Figure 22 ......................................................................18 Changes to the Power Management Section ...............................20 Changes to the Theory of Operation Section..............................25 Changes to Figure 31 and Figure 32 .............................................27 Change to Equation 28 ...................................................................47 Changes to Figure 83 ......................................................................66 Changes to Figure 86 ......................................................................68 Changes to the Registers List Section...........................................72 Changes to Ordering Guide...........................................................91 2/10—Revision 0: Initial Version ADE7854/ADE7858/ADE7868/ADE7878 Rev. E | Page 4 of 96 FUNCTIONAL BLOCK DIAGRAMS PG A 1 PG A 1 PG A 1 PG A 3 PG A 3 PG A 3 1. 2V R EF D IG IT A L SI G N A L PR O C ES SO R AV G A IN A PH C A L H PF D IS [2 3: 0] H PF A IG A IN H PF D IS [2 3: 0] D IG IT A L IN TE G RA TO R H PF PO R LD O LD O X2 A IR M S LP F A IR M SO S X2 AV R M S LP F LP F AV R M SO S A VA G A IN A W G A IN D FC C Fx D EN : D FC C Fx D EN : D FC C Fx D EN : 5 24 26 25 17 4 7 8 9 2212 13 14 19 18 39373836322935343332 27 28 23 6 SP I/I 2 C I2 C R ES ET R EF IN /O U T VD D A G N D AV D D D VD D D G N D C LK IN C LK O U T IA P IA N VA P IB P IB N VB P IC P IC N VC P VN PM 0 PM 1 C F1 C F2 C F3 /H SC LK IR Q 0 IR Q 1 SC LK /S C L M O SI /S DA M IS O /H SD SS /H SA H SD C A D E7 85 4 A D C A D C A D C A D C A D C A D C 08510-204 TO TA L A C TI VE /A PP A R EN T EN ER G IE S A N D V O LT A G E/ C U R R EN T R M S C A LC U LA TI O N F O R PH A SE C (S EE P H A SE A F O R D ET A IL ED D A TA P A TH ) TO TA L A C TI VE /A PP A R EN T EN ER G IE S A N D V O LT A G E/ C U R R EN T R M S C A LC U LA TI O N F O R PH A SE B (S EE P H A SE A F O R D ET A IL ED D A TA P A TH ) PH A SE A , PH A SE B , A N D PH A SE C D A TA A W A TT O S Figure 1. ADE7854 Functional Block Diagram ADE7854/ADE7858/ADE7868/ADE7878 Rev. E | Page 5 of 96 PG A 1 PG A 1 PG A 1 PG A 3 PG A 3 PG A 3 1. 2V R EF D IG IT A L SI G N A L PR O C ES SO R C O M PU TA TI O N A L B LO C K F O R TO TA L R EA C TI VE P O W ER AV G A IN A PH C A L H PF D IS [2 3: 0] H PF A IG A IN H PF D IS [2 3: 0] D IG IT A L IN TE G RA TO R H PF PO R LD O LD O X2 A IR M S LP F A IR M SO S X2 AV R M S LP F LP F AV R M SO S A VA G A IN A VA R G A IN A VA R O S D FC C F1 D EN : D FC C F2 D EN : D FC C F3 D EN : 5 24 26 25 17 4 7 8 9 2212 13 14 19 18 39373836322935343332 27 28 23 6 SP I/I 2 C I2 C R ES ET R EF IN /O U T VD D A G N D AV D D D VD D D G N D C LK IN C LK O U T IA P IA N VA P IB P IB N VB P IC P IC N VC P VN PM 0 PM 1 C F1 C F2 C F3 /H SC LK IR Q 0 IR Q 1 SC LK /S C L M O SI /S DA M IS O /H SD SS /H SA H SD C A D E7 85 8 A D C A D C A D C A D C A D C A D C 08510-203 TO TA L A C TI VE /R EA C TI VE / A PP A R EN T/ EN ER G IE S A N D VO LT A G E/ C U R R EN T R M S C A LC U LA TI O N F O R P H A SE B (S EE P H A SE A F O R D ET A IL ED D A TA P A TH ) TO TA L A C TI VE /R EA C TI VE / A PP A R EN T/ EN ER G IE S A N D VO LT A G E/ C U R R EN T R M S C A LC U LA TI O N F O R P H A SE C (S EE P H A SE A F O R D ET A IL ED D A TA P A TH ) PH A SE A , PH A SE B , A N D PH A SE C D A TA A W G A IN A W A TT O S Figure 2. ADE7858 Functional Block Diagram ADE7854/ADE7858/ADE7868/ADE7878 Rev. E | Page 6 of 96 PG A 1 PG A 1 PG A 1 PG A 3 PG A 3 PG A 3 1. 2V R EF TO TA L A C TI VE /R EA C TI VE / A PP A R EN T/ EN ER G IE S A N D VO LT A G E/ C U R R EN T R M S C A LC U LA TI O N F O R P H A SE B (S EE P H A SE A F O R D ET A IL ED D A TA P A TH ) TO TA L A

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